Search Results (52)

Memristors with resistive switching capabilities are vital for information storage and brain-inspired computing, making them a key focus in current research. This study demonstrates non-volatile analog resistive switching behavior in Al/TiO_x/TiN/Si(n⁺⁺)/Al memristive devices. Analog resistive switching offers gradual, controllable conductance changes, which are essential for mimicking brain-like synaptic behavior, unlike digital/abrupt switching. The amorphous titanium oxide (TiO_x) active layer was deposited using the pulsed-DC reactive magnetron sputtering technique. The impact of increasing the oxide thickness on the electrical performance of the memristors was investigated. Electrical characterizations revealed stable, forming-free analog resistive switching, achieving endurance beyond 300 DC cycles. The charge conduction mechanisms underlying the current–voltage (I–V) characteristics are analyzed in detail, revealing the presence of ohmic behavior, Schottky emission, and space-charge-limited conduction (SCLC). Experimental results indicate that increasing the TiO_x film thickness from 31 to 44 nm leads to a notable change in the current conduction mechanism. The results confirm that the memristors have good stability (>1500 s) and are capable of exhibiting excellent long-term potentiation (LTP) and long-term depression (LTD) properties. The analog switching driven by oxygen vacancy-induced barrier modulation in the TiO_x/TiN interface is explained in detail, supported by a proposed model. The remarkable switching characteristics exhibited by the TiO_x-based memristive devices make them highly suitable for artificial synapse applications in neuromorphic computing systems. Full article

Memristors, as the fourth fundamental circuit element, have attracted significant interest for their potential in analog signal processing, computing, and memory storage technologies. However, physical memristor implementations still face challenges in reproducibility, scalability, and integration with standard CMOS processes. Memristor emulator circuits, implemented using analog, digital, and mixed components, have emerged as practical alternatives, offering tunability, cost effectiveness, and compatibility with existing fabrication technologies for research and prototyping. This review paper provides a comprehensive analysis of recent advancements in memristor emulator design methodologies, including active and passive analog circuits, digital implementations, and hybrid approaches. A critical evaluation of these emulation techniques is conducted based on several performance metrics, including maximum operational frequency range, power consumption, and circuit topology. Additional parameters are also taken into account to ensure a comprehensive assessment. Furthermore, the paper examines promising healthcare applications of memristor and memristor emulators, focusing on their integration into biomedical systems. Finally, key challenges and promising directions for future research in memristor emulator development are outlined. Overall, the research presented highlights the promising future of memristor emulator technology in bridging the gap between theoretical memristor models and practical circuit implementations. Full article

Devices with tunable characteristics and parameters are used in many technical fields. Such devices can be based on memristors, which serve as programmable potentiometers. The quality of the tuning is higher by means of memristors than with mechanical and digital potentiometers. We investigate a bandpass filter in the form of an active Wien bridge with a memristor. The filter is analyzed with the help of the nodal voltage method. The dependence of the resonance frequency on the parameters of the Wien circuit, the dependence of the quality factor, and the filter gain at resonant frequency on the parameters of the voltage divider are obtained. The dependences of the resonant frequency, quality factor, and gain at the resonant frequency on the parameters of the Wien filter were formed. The tuning of the main frequency features (the filter gain, quality factor, and resonance frequency) is shown to be independent. Under different values of memristance, the frequency features result from a simulation in LTspice. These features are less than 1 percent different from the corresponding features obtained analytically. Thus, the high precision of modeling and tuning of the frequency characteristics of the memristive Wien filter is demonstrated. Full article

Moore’s Law is being challenged, as the use of transistors has limitations in terms of physical materials, energy consumption, performance, and economics. To continue Moore’s Law, people have put forward many ideas, one of which is to find smaller devices to replace CMOS transistors. Memristor-based digital logic circuits open new avenues for exploring advanced computing architectures. In this paper, a biomemristor with the structure of Al/gelatin:Au NPs/Al/gelatin was fabricated using gelatin as the substrate and the host material of the dielectric layer. The device has a large switching current ratio, good stability, and physical transient characteristics. The device can be dissolved by soaking in deionized water for 5 min. In addition, the device successfully realizes the functions of NAND and NOR logic gates. It provides an effective method for research on green electronic devices with logic functions. Full article

The rapid advancement of artificial intelligence (AI) technologies has significantly increased the demand for high-performance computational hardware. Memristor-based compute-in-memory (CIM) technology, also known as resistive random-access memory (RRAM)-based CIM technology, shows great potential for addressing the data transfer bottleneck and supporting high-performance computing (HPC). In this paper, a multi-scale thermal model is developed to evaluate the temperature distribution in RRAM-based CIM chips and the influence of various factors on thermal behavior. The results indicate that hotspot temperatures can be mitigated by reducing the epoxy molding compound (EMC) thickness, increasing the substrate thickness, and lowering boundary thermal resistance. Moreover, optimizing the layout of analog computing circuits and digital circuits can reduce the maximum temperature by up to 4.04 °C. Furthermore, the impact of temperature on the conductance of RRAM devices and the inference accuracy of RRAM-based CIM chips is analyzed. Simulation results reveal that thermal-induced accuracy loss in CIM chips is significant, but the computation correction method effectively reduces the accuracy loss from 66.4% to 1.4% at 85 °C. Full article

In-memory sensing and computing devices integrate the functionalities of sensors, memory, and processors, offering advantages such as low power consumption, high bandwidth, and zero latency, making them particularly suitable for simulating synaptic behavior in biological neural networks. As the pace of digital transformation accelerates, the demand for efficient information processing technologies is increasing, and in-memory sensing and computing devices show great potential in AI, machine learning, and edge computing. In recent years, with the continuous advancement of infrared detector technology, infrared in-memory sensing and computing devices have also seen new opportunities for development. This article reviews the latest research progress in infrared in-memory sensing and computing devices. It first introduces the working principles and performance metrics of in-memory sensing and computing devices, then discusses in detail transistors and memristor-type devices with infrared band response, and finally looks forward to the development prospects of the field. Through innovation in new semiconductor materials and structures, the development trajectory of infrared in-memory sensing and computing devices has been significantly expanded, providing new impetus for the development of a new generation of information technology. Full article

This paper presents a novel approach to in situ memristive learning by training spiking neural networks (SNNs) entirely within the circuit using memristor emulators in SPICE. The circuit models neurons using Lapicque neurons and employs pulse-based spike encoding to simulate spike-timing-dependent plasticity (STDP), a key learning mechanism in SNNs. The Lapicque neuron model operates according to the Leaky Integrate-and-Fire (LIF) model, which is used in this study to model spiking behavior in memristor-based SNNs. More exactly, the first memristor emulator in PySpice, a Python library for circuit simulation, was developed and integrated into a memristive circuit capable of in situ learning, named the “In Situ Memristive Learning Method for Pattern Classification”. This novel technique enables time-based computation, where neurons accumulate incoming spikes and fire once a threshold is reached, mimicking biological neuron behavior. The proposed method was rigorously tested on three diverse datasets: XPUE, a custom non-dominating 3 × 3 image dataset; a 3 × 5 digit dataset ranging from 0 to 5; and a resized 10 × 10 version of the Modified National Institute of Standards and Technology (MNIST) dataset. The neuromorphic circuit achieved successful pattern learning across all three datasets, outperforming comparable results from other in situ training simulations on SPICE. The learning process harnesses the cumulative effect of memristors, enabling the network to learn a representative pattern for each label efficiently. This advancement opens new avenues for neuromorphic computing and paves the way for developing autonomous, adaptable pattern classification neuromorphic circuits. Full article

This paper addresses critical gaps in the digital implementations of fractional-order memelement emulators, particularly given the challenges associated with the development of solid-state devices using nanomaterials. Despite the potentials of these devices for industrial applications, the digital implementation of fractional-order models has received limited attention. This research contributes to bridging this knowledge gap by presenting the FPGA realization of the memelements based on a universal voltage-controlled circuit topology. The digital emulators successfully exhibit the pinched hysteresis behaviors of memristors, memcapacitors, and meminductors, showing the retention of historical states of their constitutive electronic variables. Additionally, we analyze the impact of the fractional-order parameters and excitation frequencies on the behaviors of the memelements. The design methodology involves using Xilinx System Generator for DSP blocks to lay out the architectures of the emulators, with synthesis and gate-level implementation performed on the Xilinx Artix-7 AC701 Evaluation kit, where resource utilization on hardware accounts for about $1\%$ of available hardware resources. Further hardware analysis shows successful timing validation and low power consumption across all designs, with an average on-chip power of 0.23 Watts and average worst negative slack of 0.6 ns against a 5 ns constraint. We validate these results with Matlab 2020b simulations, which aligns with the hardware models. Full article

The development of hardware-based cognitive computing systems critically hinges upon the integration of memristor devices capable of versatile weight expression across a spectrum of resistance levels while preserving consistent electrical properties. This investigation aims to explore the practical implementation of a digit recognition system utilizing memristor devices with minimized weighting levels. Through the process of weight quantization for digits represented by 25 or 49 input signals, the study endeavors to ascertain the feasibility of digit recognition via neural network computation. The integration of memristor devices into the system architecture is poised to streamline the representation of the resistors required for weight expression, thereby facilitating the realization of neural-network-based cognitive systems. To minimize the information corruption in the system caused by weight quantization, we introduce the concept of “weight range” in this work. The weight range is the range between the maximum and minimum values of the weights in the neural network. We found that this has a direct impact on weight quantization, which reduces the number of digits represented by a weight below a certain level. This was found to help maintain the information integrity of the entire system despite the reduction in weight levels. Moreover, to validate the efficacy of the proposed methodology, quantized weights are systematically applied to an array of double-layer neural networks. This validation process involves the construction of cross-point array circuits with dimensions of 25 × 10 and 10 × 10, followed by a meticulous examination of the resultant changes in the recognition rate of randomly generated numbers through device simulations. Such endeavors contribute to advancing the understanding and practical implementation of hardware-based cognitive computing systems leveraging memristor devices and weight quantization techniques. Full article

This study explores memristor-based true random number generators (TRNGs) through their evolution and optimization, stemming from the concept of memristors first introduced by Leon Chua in 1971 and realized in 2008. We will consider memristor TRNGs coming from various entropy sources for producing high-quality random numbers. However, we must take into account both their strengths and weaknesses. The comparison with CMOS-based TRNGs will serve as an illustration that memristor TRNGs stand out due to their simpler circuits and lower power consumption— thus leading us into a case study involving electroless YMnO₃ (YMO) memristors as TRNG entropy sources that demonstrate good security properties by being able to produce unpredictable random numbers effectively. The end of our analysis sees us pinpointing challenges: post-processing algorithm optimization coupled with ensuring reliability over time for memristor-based TRNGs aimed at next-generation security applications. Full article

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications. Full article

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor–CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network’s controller. Firstly, the input neurons perform preprocessing for the DVS camera’s events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply–Accumulate (MAC) calculations according to the memristor’s current–voltage relationship. The hidden and output neurons can convert the crossbar’s column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network’s controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network’s performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme. Full article

The traditional von Neumann architecture of computers, constrained by the inherent separation of processing and memory units, faces challenges, for instance, memory wall issue. Neuromorphic computing and in-memory computing offer promising paradigms to overcome the limitations of additional data movement and to enhance computational efficiency. In this work, transfer-free flexible memristors based on hexagonal boron nitride films were proposed for analog neuromorphic and digital memcomputing. Analog memristors were prepared; they exhibited synaptic behaviors, including paired-pulse facilitation and long-term potentiation/depression. The resistive switching mechanism of the analog memristors were investigated through transmission electron microscopy. Digital memristors were prepared by altering the electrode materials, and they exhibited reliable device performance, including a large on/off ratio (up to 10⁶), reproducible switching endurance (>100 cycles), non-volatile characteristic (>60 min), and effective operating under bending conditions (>100 times). Full article

Arrays of memristive devices coupled with photosensors can be used for capturing and processing visual information, thereby realizing the concept of “in-sensor computing”. This is a promising concept associated with the development of compact and low-power machine vision devices, which is crucial important for bionic prostheses of eyes, on-board image recognition systems for unmanned vehicles, computer vision in robotics, etc. This concept can be applied for the creation of a memristor based neuromorphic analog machine vision systems, and here, we propose a new architecture for these systems in which captured visual data are fed to a spiking artificial neural network (SNN) based on memristive devices without analog-to-digital and digital-to-analog conversions. Such an approach opens up the opportunities of creating more compact, energy-efficient visual processing units for wearable, on-board, and embedded electronics for such areas as robotics, the Internet of Things, and neuroprosthetics, as well as other practical applications in the field of artificial intelligence. Full article

Recently, the application of memristors in chaotic systems has been extensively studied. Unfortunately, there is limited literature on the introduction of discrete memristors into chaotic maps, especially into non-classical multidimensional maps. For this reason, this paper establishes a new three-dimensional parabolic chaotic map model; in order to improve the complexity and randomness of the map, it is coupled with a square-charge-controlled discrete memristor to design a new four-dimensional memristive hyperchaotic map. Firstly, the stability of the two maps is discussed. And their dynamical properties are compared using Lyapunov exponential spectra and bifurcation diagrams. Then, the phase diagram and iteration sequence of the 4D memristive hyperchaotic map are obtained. Meanwhile, we investigate the hyperchaotic states, the transient chaos, state transfer and attractor coexistence phenomena of the four-dimensional memristive map. In particular, the special state transfer phenomenon of switching from a periodic attractor to a quasi-periodic attractor and the special coexistence phenomenon of a quasi-periodic attractor coexisting with a quasi-periodic attractor around fixed points are found, which have not been observed in other systems. Finally, the phase-track diagrams and iterative sequence diagrams of the four-dimensional memristive map are verified on a digital experimental platform, revealing its potential for practical applications. Full article