# FPGA Realization of a Fractional-Order Model of Universal Memory Elements

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

_{2}) sandwiched between two electrodes of platinum with its switching mechanism identified to exhibit the synaptic-like behaviors of those of a neuron in the brain [7]. The memristor’s ability to change its resistance in response to inputs makes it a promising component for future electronic technologies.

- (i)
- The low-cost FPGA realization of the fractional-order memristor, memcapacitor, and meminductor designed using VHDL blocks of Xilinx System Generator for DSP. The design can achieve the theoretical behaviors of memelements including PHL, which can be enhanced by lowering the fractional orders in high-excitation frequencies.
- (ii)
- A demonstration of the JTAG hardware co-simulation of the design showing real-time testing of the memelement-based systems as well as behavioral HDL netlist tests. The results of the hardware experiments are in close alignment with the numerical results from Matlab.

## 2. Mathematical Models of Universal Emulators for Memelements

**Fractional-order memristor (FOMR)**

**Fractional-order Memcapacitor (FOMC)**

**Fractional-order Meminductor (FOMI)**

**Characteristics of Memelements**

- (1)
- For a continuous periodic current or voltage input, the memdevices exhibit a pinched hysteresis loop at the associative state variable origin: $v-i$ in the case of a memristor, $q-v$ in the case of a memcapacitor, and $\varphi -i$ in the case of a meminductor.
- (2)
- At increased frequency of the input voltage or current, the pinched hysteresis collapses and tends towards linearity, demonstrating the behavior of a linear resistor, capacitor, and inductor in each case.

## 3. Design of FOME

**FOMR:**

**FOMC:**

**FOMI:**

**Samples Stored as LUT and Frequency Impact**

## 4. Experimental Test Results

**FOMR Fingerprint**

**FOMC Fingerprint**

**FOMI Fingerprint**

**Resource, Timing and Power Analysis**

## 5. Discussion

## 6. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## Abbreviations

AM | Analog Multiplier |

BRAM | Block Random Access Memory |

BUFG | Global Clock Buffer |

DSP | Digital Signal Processor |

DVCC | Distributed Voltage and Current Control |

FF | Flip-Flop |

FOC | Fractional-Order Capacitor |

FOMC | Fractional-Order Memcapacitor |

FOME | Fractional-Order Memelement |

FOMI | Fractional-Order Meminductor |

FOMR | Fractional-Order Memristor |

FPGA | Field Programmable Gate Array |

HDL | Hardware description language |

IO | Input–Output |

JTAG | Joint Test Action Group |

LUT | Lookup Table |

PHL | Pinched Hysteresis Loop |

VHDL | Very High-Speed Integrated Circuit Hardware Description Language |

TNS | Total Negative Slack |

WNS | Worst Negative Slack |

## References

- Pershin, Y.V.; Ventra, M.D. Memory effects in complex materials and nanoscale systems. Adv. Phys.
**2011**, 60, 145–227. [Google Scholar] [CrossRef] - Ventra, M.D.; Pershin, Y.V. Memristors and Memelements; Springer: Berlin/Heidelberg, Germany, 2023. [Google Scholar] [CrossRef]
- Chua, L. Memristor-The missing circuit element. IEEE Trans. Circuit Theory
**1971**, 18, 507–519. [Google Scholar] [CrossRef] - Chua, L. If It’s Pinched It’s a Memristor; Springer: New York, NY, USA, 2014; pp. 17–90. [Google Scholar] [CrossRef]
- Ventra, M.D.; Pershin, Y.V.; Chua, L.O. Circuit Elements With Memory: Memristors, Memcapacitors, and Meminductors. Proc. IEEE
**2009**, 97, 1717–1724. [Google Scholar] [CrossRef] - Kim, H.; Sah, M.P.; Yang, C.; Cho, S.; Chua, L.O. Memristor Emulator for Memristor Circuit Applications. IEEE Trans. Circuits Syst. I Regul. Pap.
**2012**, 59, 2422–2431. [Google Scholar] [CrossRef] - Strukov, D.B.; Snider, G.S.; Stewart, D.R.; Williams, R.S. The missing memristor found. Nature
**2008**, 453, 80–83. [Google Scholar] [CrossRef] - Petras, I.; Chen, Y. Fractional-order circuit elements with memory. In Proceedings of the 13th International Carpathian Control Conference (ICCC), IEEE, High Tatras, Slovakia, 28–31 May 2012; pp. 552–558. [Google Scholar] [CrossRef]
- Demasius, K.U.; Kirschen, A.; Parkin, S. Energy-efficient memcapacitor devices for neuromorphic computing. Nat. Electron.
**2021**, 4, 748–756. [Google Scholar] [CrossRef] - Zhu, Y.; He, Y.; Chen, C.; Zhu, L.; Mao, H.; Zhu, Y.; Wang, X.; Yang, Y.; Wan, C.; Wan, Q. HfZrOx-based capacitive synapses with highly linear and symmetric multilevel characteristics for neuromorphic computing. Appl. Phys. Lett.
**2022**, 120, 113504. [Google Scholar] [CrossRef] - Hwang, S.; Yu, J.; Song, M.S.; Hwang, H.; Kim, H. Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing. Adv. Sci.
**2023**, 10, 2303817. [Google Scholar] [CrossRef] - Hong, Q.; Chen, H.; Sun, J.; Wang, C. Memristive Circuit Implementation of a Self-Repairing Network Based on Biological Astrocytes in Robot Application. IEEE Trans. Neural Netw. Learn. Syst.
**2022**, 33, 2106–2120. [Google Scholar] [CrossRef] - Wu, X.; Dang, B.; Wang, H.; Wu, X.; Yang, Y. Spike-Enabled Audio Learning in Multilevel Synaptic Memristor Array-Based Spiking Neural Network. Adv. Intell. Syst.
**2022**, 4, 2100151. [Google Scholar] [CrossRef] - Wang, X.; Yu, J.; Jin, C.; Iu, H.H.C.; Yu, S. Chaotic oscillator based on memcapacitor and meminductor. Nonlinear Dyn.
**2019**, 96, 161–173. [Google Scholar] [CrossRef] - Yuan, F.; Li, Y. A chaotic circuit constructed by a memristor, a memcapacitor and a meminductor. Chaos Interdiscip. J. Nonlinear Sci.
**2019**, 29, 101101. [Google Scholar] [CrossRef] - Wang, G.; Zang, S.; Wang, X.; Yuan, F.; Iu, H.H.C. Memcapacitor model and its application in chaotic oscillator with memristor. Chaos Interdiscip. J. Nonlinear Sci.
**2017**, 27, 013110. [Google Scholar] [CrossRef] - Jiang, Y.; Li, C.; Zhang, C.; Lei, T.; Jafari, S. Constructing Meminductive Chaotic Oscillator. IEEE Trans. Circuits Syst. II Express Briefs
**2023**, 70, 2675–2679. [Google Scholar] [CrossRef] - Li, C.; Hu, M.; Li, Y.; Jiang, H.; Ge, N.; Montgomery, E.; Zhang, J.; Song, W.; Dávila, N.; Graves, C.E.; et al. Analogue signal and image processing with large memristor crossbars. Nat. Electron.
**2017**, 1, 52–59. [Google Scholar] [CrossRef] - Flak, J.; Poikonen, J.K. Solid-State Memcapacitors and Their Applications; Springer: Berlin/Heidelberg, Germany, 2019; pp. 1211–1228. [Google Scholar] [CrossRef]
- Poddar, S.; Zhang, Y.; Gu, L.; Zhang, D.; Zhang, Q.; Yan, S.; Kam, M.; Zhang, S.; Song, Z.; Hu, W.; et al. Down-Scalable and Ultra-fast Memristors with Ultra-high Density Three-Dimensional Arrays of Perovskite Quantum Wires. Nano Lett.
**2021**, 21, 5036–5044. [Google Scholar] [CrossRef] - Lammie, C.; Eshraghian, J.K.; Lu, W.D.; Azghadi, M.R. Memristive Stochastic Computing for Deep Learning Parameter Optimization. IEEE Trans. Circuits Syst. II Express Briefs
**2021**, 68, 1650–1654. [Google Scholar] [CrossRef] - Woo, K.S.; Kim, J.; Han, J.; Choi, J.M.; Kim, W.; Hwang, C.S. A High-Speed True Random Number Generator Based on a Cu x Te 1-x Diffusive Memristor. Adv. Intell. Syst.
**2021**, 3, 2100062. [Google Scholar] [CrossRef] - Du, C.; Cai, F.; Zidan, M.A.; Ma, W.; Lee, S.H.; Lu, W.D. Reservoir computing using dynamic memristors for temporal information processing. Nat. Commun.
**2017**, 8, 2204. [Google Scholar] [CrossRef] - Wang, Z.; Li, C.; Song, W.; Rao, M.; Belkin, D.; Li, Y.; Yan, P.; Jiang, H.; Lin, P.; Hu, M.; et al. Reinforcement learning with analogue memristor arrays. Nat. Electron.
**2019**, 2, 115–124. [Google Scholar] [CrossRef] - Yang, J.; Hu, L.; Shen, L.; Wang, J.; Cheng, P.; Lu, H.; Zhuge, F.; Ye, Z. Optically driven intelligent computing with ZnO memristor. Fundam. Res.
**2024**, 4, 158–166. [Google Scholar] [CrossRef] - Mehonic, A.; Sebastian, A.; Rajendran, B.; Simeone, O.; Vasilaki, E.; Kenyon, A.J. Memristors—From In-Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio-Inspired Computing. Adv. Intell. Syst.
**2020**, 2, 2000085. [Google Scholar] [CrossRef] - Hussain, T.; Abbas, H.; Youn, C.; Lee, H.; Boynazarov, T.; Ku, B.; Jeon, Y.; Han, H.; Lee, J.H.; Choi, C.; et al. Cellulose Nanocrystal Based Bio-Memristor as a Green Artificial Synaptic Device for Neuromorphic Computing Applications. Adv. Mater. Technol.
**2022**, 7, 2100744. [Google Scholar] [CrossRef] - Chaurasiya, R.; Shih, L.C.; Chen, K.T.; Chen, J.S. Emerging higher-order memristors for bio-realistic neuromorphic computing: A review. Mater. Today
**2023**, 68, 356–376. [Google Scholar] [CrossRef] - Fu, T.; Liu, X.; Gao, H.; Ward, J.E.; Liu, X.; Yin, B.; Wang, Z.; Zhuo, Y.; Walker, D.J.F.; Yang, J.J.; et al. Bioinspired bio-voltage memristors. Nat. Commun.
**2020**, 11, 1861. [Google Scholar] [CrossRef] - Xia, Q.; Yang, J.J. Memristive crossbar arrays for brain-inspired computing. Nat. Mater.
**2019**, 18, 309–323. [Google Scholar] [CrossRef] - Najem, J.S.; Hasan, M.S.; Williams, R.S.; Weiss, R.J.; Rose, G.S.; Taylor, G.J.; Sarles, S.A.; Collier, C.P. Dynamical nonlinear memory capacitance in biomimetic membranes. Nat. Commun.
**2019**, 10, 3239. [Google Scholar] [CrossRef] - Mohamed, M.G.A.; Kim, H.; Cho, T.W. Modeling of Memristive and Memcapacitive Behaviors in Metal-Oxide Junctions. Sci. World J.
**2015**, 2015, 910126. [Google Scholar] [CrossRef] - Dinavahi, A.; Yamamoto, A.; Harris, H.R. Physical evidence of meminductance in a passive, two-terminal circuit element. Sci. Rep.
**2023**, 13, 1817. [Google Scholar] [CrossRef] - Alharbi, A.G.; Chowdhury, M.H. Memristor Emulator Circuits; Springer: Berlin/Heidelberg, Germany, 2021. [Google Scholar] [CrossRef]
- Tasneem, S.; Sharma, P.K.; Ranjan, R.K.; Khateb, F. Electronically Tunable Memristor Emulator Implemented Using a Single Active Element and Its Application in Adaptive Learning. Sensors
**2023**, 23, 1620. [Google Scholar] [CrossRef] - Bhardwaj, K.; Srivastava, M. Wide-band compact floating memristor emulator configuration with electronic/resistive adjustability. Microelectron. J.
**2021**, 117, 105284. [Google Scholar] [CrossRef] - Ghosh, P.K.; Riam, S.Z.; Ahmed, M.S.; Sundaravadivel, P. CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications. Electronics
**2023**, 12, 1654. [Google Scholar] [CrossRef] - Stavrinides, S.G.; Picos, R.; Corinto, F.; Chawa, M.M.A.; de Benito, C. Implementing memristor emulators in hardware. In Proceedings of the Mem-Elements for Neuromorphic Circuits with Artificial Intelligence Applications; Volos, C., Pham, V.T., Eds.; Academic Press: London, UK, 2021; pp. 17–40, Volume Advances in Nonlinear Dynamics and Chaos (ANDC). [Google Scholar]
- Sah, M.P.; Yang, C.; Kim, H.; Chua, L. A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators. Sensors
**2012**, 12, 3587–3604. [Google Scholar] [CrossRef] - Martinez-Rincon, J.; Pershin, Y.V. Bistable Nonvolatile Elastic-Membrane Memcapacitor Exhibiting a Chaotic Behavior. IEEE Trans. Electron Devices
**2011**, 58, 1809–1812. [Google Scholar] [CrossRef] - Fouda, M.; Radwan, A. Charge controlled memristor-less memcapacitor emulator. Electron. Lett.
**2012**, 48, 1454. [Google Scholar] [CrossRef] - Sah, M.P.; Yang, C.; Budhathoki, R.K.; Kim, H.; Yoo, H.J. Implementation of a Memcapacitor Emulator with Off-the-Shelf Devices. Electron. Electr. Eng.
**2013**, 19, 54–58. [Google Scholar] [CrossRef] - Konal, M.; Kacar, F.; Babacan, Y. Electronically controllable memcapacitor emulator employing VDCCs. AEU Int. J. Electron. Commun.
**2021**, 140, 153932. [Google Scholar] [CrossRef] - Han, J.; Song, C.; Gao, S.; Wang, Y.; Chen, C.; Pan, F. Realization of the Meminductor. ACS Nano
**2014**, 8, 10043–10047. [Google Scholar] [CrossRef] - Qingjiang, L.; Khiat, A.; Salaoru, I.; Papavassiliou, C.; Hui, X.; Prodromakis, T. Memory Impedance in TiO2 based Metal-Insulator-Metal Devices. Sci. Rep.
**2014**, 4, 4522. [Google Scholar] [CrossRef] - Biolkova, V.; Biolek, D.; Biolek, Z. Pinched hysteretic loops of ideal memristors, memcapacitors and meminductors must be ‘self-crossing’. Electron. Lett.
**2011**, 47, 1385–1387. [Google Scholar] [CrossRef] - Wang, S.F. The gyrator for transforming nano memristor into meminductor. Circuit World
**2016**, 42, 197–200. [Google Scholar] [CrossRef] - Romero, F.J.; Escudero, M.; Medina-Garcia, A.; Morales, D.P.; Rodriguez, N. Meminductor Emulator Based on a Modified Antoniou’s Gyrator Circuit. Electronics
**2020**, 9, 1407. [Google Scholar] [CrossRef] - Lin, R.; Shi, G.; Qiao, F.; Wang, C.; Wu, S. Research progress and applications of memristor emulator circuits. Microelectron. J.
**2023**, 133, 105702. [Google Scholar] [CrossRef] - Gupta, R.K.; Choudhry, M.S.; Saxena, V.; Taran, S. A Single MOS-Memristor Emulator Circuit. Circuits Syst. Signal Process.
**2024**, 43, 54–73. [Google Scholar] [CrossRef] - Zhou, L.; Wang, C.; Qin, H.; Wang, Q. A 300 MHz MOS-only memristor emulator. AEU Int. J. Electron. Commun.
**2023**, 162, 154593. [Google Scholar] [CrossRef] - Petráš, I. Oscillators Based on Fractional-Order Memory Elements. Fractal Fract.
**2022**, 6, 283. [Google Scholar] [CrossRef] - Ross, B. The development of fractional calculus 1695–1900. Hist. Math.
**1977**, 4, 75–89. [Google Scholar] [CrossRef] - He, S.; Zhan, D.; Wang, H.; Sun, K.; Peng, Y. Discrete Memristor and Discrete Memristive Systems. Entropy
**2022**, 24, 786. [Google Scholar] [CrossRef] - Xu, B.; Geng, H.; Jiang, L.; Zou, S.; Chen, K.; Liu, Z. FPGA Implementation of Memristor Emulators Using Fractional Order Calculus: A High-Precision Reconfigurable Approach. IEEE Trans. Circuits Syst. I Regul. Pap.
**2024**, 71, 1615–1627. [Google Scholar] [CrossRef] - Li, Y.; Xie, L.; Zheng, C.; Yu, D.; Eshraghian, J.K. Modeling and hardware implementation of universal interface-based floating fractional-order mem-elements. Chaos Interdiscip. J. Nonlinear Sci.
**2023**, 33, 013141. [Google Scholar] [CrossRef] - Valsa, J.; Dvořák, P.; Friedl, M. Network Model of the CPE. Radioengineering
**2011**, 20, 619–626. [Google Scholar] - Voth, J.M.; Sturtevant, G.H. Digital engineering: Expanding the advantage. J. Mar. Eng. Technol.
**2022**, 21, 355–363. [Google Scholar] [CrossRef] - Wang, X.; Wang, Y.; Shi, X.; Gao, L.; Li, P. A probabilistic multimodal optimization algorithm based on Buffon principle and Nyquist sampling theorem for noisy environment. Appl. Soft Comput.
**2021**, 104, 107068. [Google Scholar] [CrossRef]

**Figure 2.**Square symmetric diagram of all-known fundamental electronic elements. Source: own elaboration.

**Figure 3.**Digital FOMR: (

**a**) the complete design of the emulator, (

**b**) the fractional integral of the input voltage ${V}_{AB}$ configuration in its steady-state response, (

**c**) the hardware co-simulation block, and (

**d**) an evaluation with a voltage source. Source: own elaboration.

**Figure 4.**Digital FOMC: (

**a**) the complete design of the emulator, (

**b**) the hardware co-simulation block, and (

**c**) an evaluation with a voltage source. Source: own elaboration.

**Figure 5.**Digital FOMI: (

**a**) the complete design of the emulator, (

**b**) the digital integer-order integrator, (

**c**) the hardware co-simulation block, and (

**d**) an evaluation with a voltage source. Source: own elaboration.

**Figure 6.**Dynamics of ${J}^{\alpha}\left(A{\omega}^{-1}sin\left(\omega t\right)\right)$ for f = 7 kHz, $\alpha $ = 0.95, A = 1.5 V, and step size = $1\times {10}^{-6}$.

**Figure 7.**(

**a**) $v-i$ characteristics of FOMR for different excitation frequencies of f = 0.4 kHz, 0.8 kHz, and 1.2 kHz when $\alpha $ = 0.95. (

**a**) Matlab. (

**b**) Hardware Co-simulation. Source: own elaboration.

**Figure 8.**(

**a**) $v-i$ characteristics of FOMR for different order values $\alpha $ = 0.90, 0.95, and 1 when f = 0.4 kHz. (

**a**) Matlab. (

**b**) Hardware Co-simulation. Source: own elaboration.

**Figure 9.**$q-v$ characteristics of FOMC for different excitation frequencies of f = 1.5 kHz, 2 kHz, and 2.5 kHz when $\alpha $ = 0.95. (

**a**) Matlab. (

**b**) Hardware Co-simulation. Source: own elaboration.

**Figure 10.**(

**a**) $q-v$ characteristics of FOMC for different order values $\alpha $ = 0.90, 0.95, and 1 when f = 2.5 kHz. (

**a**) Matlab. (

**b**) Hardware Co-simulation. Source: own elaboration.

**Figure 11.**(

**a**) $\varphi -i$ characteristics of FOMI for different excitation frequencies of f = 5 kHz, 6 kHz, and 7 kHz when $\alpha $ = 0.95. (

**a**) Matlab. (

**b**) Hardware Co-simulation. Source: own elaboration.

**Figure 12.**(

**a**) $\varphi -i$ characteristics of FOMI for different order values $\alpha $ = 0.90, 0.95, and 1 when f = 5 kHz. (

**a**) Matlab. (

**b**) Hardware Co-simulation. Source: own elaboration.

System | Metric | LUT (133,800) | FF (267,600) | DSP (740) | I/O (400) | BUFG (32) | BRAM (365) |
---|---|---|---|---|---|---|---|

FOMR | Resource | 5030 | 319 | 4 | 66 | 2 | 0 |

Utilization | 3.76 % | 0.12 % | 0.54 % | 16.50 % | 6.25 % | 0.00 % | |

FOMC | Resource | 2128 | 149 | 5 | 91 | 1 | 0 |

Utilization | 1.59 % | 0.06 % | 0.68 % | 22.75 % | 3.13 % | 0.00 % | |

FOMI | Resource | 1103 | 120 | 8 | 102 | 2 | 0 |

Utilization | 0.82 % | 0.04 % | 1.08 % | 25.50 % | 6.25 % | 0.00 % |

Resource | Available | FOMR | FOMC | FOMI |
---|---|---|---|---|

LUT | 134,600 | 4914 (3.67 %) | 2053 (1.53 %) | 883 (0.66 %) |

FF | 269,200 | 294 (0.11 %) | 163 (0.06 %) | 105 (0.04 %) |

DSP | 740 | 0 (0.00 %) | 0 (0.00 %) | 0 (0.00 %) |

IO | 400 | 51 (12.75 %) | 51 (12.75 %) | 51 (12.75 %) |

BUFG | 32 | 1 (3.13 %) | 1 (3.13 %) | 1 (3.13 %) |

Timing Analysis | FOMR | FOMC | FOMI |
---|---|---|---|

Worst Negative Slack (WNS) | 0.095 ns | 0.233 ns | 1.458 ns |

Total Negative Slack (TNS) | 0 ns | 0 ns | 0 ns |

Number of Failing Endpoints | 0 | 0 | 0 |

Total Number of Endpoints | 333 | 179 | 40 |

Power Analysis | FOMR | FOMC | FOMI |
---|---|---|---|

Total On-Chip Power | 0.194 W | 0.186 W | 0.3 W |

Junction Temperature | 25.4 °C | 25.3 °C | 25.6 °C |

Thermal Margin | 59.6 °C | 59.7 °C | 59.4 °C |

Effective Thermal Resistance | 1.9 °C/W | 1.9 °C/W | 1.9 °C/W |

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**MDPI and ACS Style**

Afolabi, O.-M.; Adeyemi, V.-A.; Tlelo-Cuautle, E.; Nuñez-Perez, J.-C.
FPGA Realization of a Fractional-Order Model of Universal Memory Elements. *Fractal Fract.* **2024**, *8*, 605.
https://doi.org/10.3390/fractalfract8100605

**AMA Style**

Afolabi O-M, Adeyemi V-A, Tlelo-Cuautle E, Nuñez-Perez J-C.
FPGA Realization of a Fractional-Order Model of Universal Memory Elements. *Fractal and Fractional*. 2024; 8(10):605.
https://doi.org/10.3390/fractalfract8100605

**Chicago/Turabian Style**

Afolabi, Opeyemi-Micheal, Vincent-Ademola Adeyemi, Esteban Tlelo-Cuautle, and Jose-Cruz Nuñez-Perez.
2024. "FPGA Realization of a Fractional-Order Model of Universal Memory Elements" *Fractal and Fractional* 8, no. 10: 605.
https://doi.org/10.3390/fractalfract8100605