Search Results (7)

Quasi-single-stage AC/DC converters offer the advantages of fewer power devices, simplified control, and high power density in single-phase front-end applications. This paper presents a novel quasi-single-stage AC/DC topology employing magnetically integrated differential-mode coupled inductors to address the low power factor and large input current harmonics commonly observed in conventional single-phase quasi-single-stage converters. In addition, a burst mode switch is introduced to widen the operating range of the converter by regulating the DC link voltage under light-load conditions. The operating principles and power flow of the proposed converter in both normal and burst modes are analyzed, and the operating modes and equivalent circuit of the front-end power factor correction stage are discussed in detail. A 400 W experimental prototype is built to verify the feasibility of the proposed circuit. Under a 220 V AC input at full load, the prototype achieves a measured efficiency of 91.9%, a power factor greater than 0.99, and low input current total harmonic distortion. These results demonstrate that the proposed quasi-single-stage AC/DC converter can achieve high power factor and high efficiency with reduced component count and improved electromagnetic interference characteristics. Full article

Intelligence, surveillance, and reconnaissance (ISR) platforms and electric vertical take-off and landing (eVTOL) aircraft demand onboard power conversion systems that simultaneously achieve high gravimetric power density, robustness, and fault-tolerance. In this context, modular battery architectures based on per-string power electronic interfaces emerge as a key enabler for voltage regulation, fault isolation, and in-flight reconfiguration. However, the stringent mass and volume constraints of electric aviation place magnetic components among the primary limiting factors of converter scalability. This paper presents a design methodology for interleaved converters with coupled inductors that explicitly decompose common-mode, differential-mode, and uncoupled inductance components. The proposed approach enables independent adjustment of current ripple and dynamic response, allowing zero-voltage switching (ZVS) operation while ensuring stable and controllable behavior under close-loop current regulation. The methodology is experimentally validated on a 4 kW two-phase interleaved GaN-based boost converter operating at 500 kHz. Experimental results demonstrate a peak efficiency of 97%, with less than 1% variation across the operating range, and stable dynamic behavior under load transients. These results confirm the effectiveness of the proposed design methodology as a scalable solution for high-power-density, high-reliability power converters in electric aviation battery systems. Full article

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

As integrated electronic microsystems advance, their internal components demonstrate increasing miniaturization, higher-density integration, and, consequently, significantly enhanced performance. This paper presents an on-chip transformer balun. The balun has a combination of planar coupled inductors and filtering capacitors using integrated passive device (IPD) technology, giving it the advantages of a more compact circuit size and lower cost to achieve single-ended to differential function on glass substrates. Moreover, it can be integrated in systems by flip-chip. The die has a size of 1.81 mm × 1.36 mm with a −15 dB single-ended return loss bandwidth of 2.07 GHz to 4.30 GHz. Within this bandwidth, the maximum insertion loss is 2.56 dB, and the amplitude imbalance is less than 2.04 dB. The phase difference between the differential signals is 180 ± 14.02° and the common mode rejection ratio (CMRR) is above 19.08 dB. The balun has the potential of miniaturization for integration on package or through-glass interposers (TGIs). Full article

This paper proposes a control method to improve the dynamic performance of a two-phase DM (Differential Mode)-coupled boost converter designed for applications such as hybrid vehicles and railway systems. A conventional boost converter can be modified to a two-phase interleaved configuration to reduce current ripple and incorporate a differential mode (DM)-coupled inductor to reduce the volume of magnetic components, thereby achieving a decrease in cost and volume. However, when this converter is operated using a conventional PI controller, significant issues arise, particularly in the discontinuous conduction mode (DCM), where dynamic characteristics and response times are considerably slow. For a conventional boost converter, the steady-state duty cycle during DCM operation can be calculated analytically and used for feedforward compensation in a current-duty controller. In contrast, the duty cycle of a two-phase DM-coupled boost converter during DCM operation exhibits non-linear behavior depending on input/output voltages and load conditions, making analytical computation infeasible. To address this, steady-state duty cycle data is extracted through experiments and simulations, and a Look-Up Table is constructed to perform feedforward compensation. Given the multiple input and output specifications, multiple Look-Up Tables are required, leading to excessive MCU (Micro Controller Unit) computation load. The proposed correction algorithm enables feedforward compensation in the DCM region with a single Look-Up Table for all input and output specifications, achieving improvements in dynamic characteristics and reducing MCU computational load. This method achieves a reduction in settling time by up to 77 ms, with a minimum improvement of 10 ms, thereby significantly enhancing the responsiveness of the converter. Full article

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified $f_T$-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/$\sqrt{Hz}$, core DC power consumption is 7.84 mW from a $V_{DDTIA}$ of 1.6 V and core area is 39 µm × 26 µm. Full article

High-order switched DC-DC converters, such as SEPIC, Ćuk and Zeta, are classic energy processing elements, which can be used in a wide variety of applications due to their capacity to step-up and/or step-down voltage characteristic. In this paper, a novel methodology for analyzing the previous converters operating in discontinuous conduction mode (DCM) is applied to obtain full-order dynamic models. The analysis is based on the fact that inductor currents have three differentiated operating sub-intervals characterized by a third one in which both currents become equal, which implies that the current flowing through the diode is zero (DCM). Under a small voltage ripple hypothesis, the currents of all three converters have similar current piecewise linear shapes that allow us to use a graphical method based on the triangular shape of the diode current to obtain the respective non-linear average models. The models’ linearization around their steady-state operating points yields full-order small-signal models that reproduce accurately the dynamic behavior of the corresponding switched model. The proposed methodology is applicable to the proposed converters and has also been extended to more complex topologies with magnetic coupling between inductors and/or an $RC$ damping network in parallel with the intermediate capacitor. Several tests were carried out using simulation, hardware-in-the-loop, and using an experimental prototype. All the results validate the theoretical models. Full article