A Novel Quasi-Single-Stage High-Efficiency and High-Power-Factor AC/DC Converter ^†

Abstract

Quasi-single-stage AC/DC converters offer the advantages of fewer power devices, simplified control, and high power density in single-phase front-end applications. This paper presents a novel quasi-single-stage AC/DC topology employing magnetically integrated differential-mode coupled inductors to address the low power factor and large input current harmonics commonly observed in conventional single-phase quasi-single-stage converters. In addition, a burst mode switch is introduced to widen the operating range of the converter by regulating the DC link voltage under light-load conditions. The operating principles and power flow of the proposed converter in both normal and burst modes are analyzed, and the operating modes and equivalent circuit of the front-end power factor correction stage are discussed in detail. A 400 W experimental prototype is built to verify the feasibility of the proposed circuit. Under a 220 V AC input at full load, the prototype achieves a measured efficiency of 91.9%, a power factor greater than 0.99, and low input current total harmonic distortion. These results demonstrate that the proposed quasi-single-stage AC/DC converter can achieve high power factor and high efficiency with reduced component count and improved electromagnetic interference characteristics.

1. Introduction

In modern data centers, the front-end AC/DC power supply unit usually adopts a two-stage architecture: a power factor correction (PFC) stage converts the 220 V AC mains into a regulated 400 V DC bus, and an isolated DC/DC stage then steps this bus down to 48 V for the server motherboard [1]. Harmonic pollution generated by such power electronic equipment degrades power quality and may reduce the stability of power systems and connected loads [2]; therefore, front-end converters are required to comply with harmonic standards such as IEC 61000-3-2 by shaping the input current to be nearly sinusoidal and limiting current distortion [3]. This two-stage arrangement allows the PFC and DC/DC stages to be designed and controlled independently, which simplifies meeting power-quality requirements and reduces the interaction between input and output harmonics.

However, the separate control loops, sensing circuits, and multiple magnetic components increase complexity, volume, and cost, and limit the achievable power density. To address these issues, many single-stage and quasi-single-stage AC/DC converters have been proposed [4,5,6,7,8,9], in which the PFC function is combined with the DC/DC stage and some switches are shared, enabling a more compact power stage and simpler overall control. Among various active PFC circuits, boost-type converters are commonly used in front-end stages because they offer simple control and gate driving, continuous switching over the entire line cycle, and an input current power factor close to unity [10,11,12,13]. In most quasi-single-stage designs, a boost-type PFC stage is integrated with a soft-switching LLC resonant converter, so that both the input current and the output voltage can be regulated simultaneously [14,15,16,17,18,19].

Representative quasi-single-stage boost–LLC topologies are reported in [15,16,17,19]. In [15], a quasi-single-stage boost+LLC converter is realized by integrating the boost PFC part and the LLC resonant part. Because the boost stage operates with a fixed duty cycle of 0.5 in open loop, the bus voltage $V_{\mathrm{bus}}$ is higher than twice the peak input voltage and varies significantly over the input range, which increases device stress and complicates component selection. A topology that directly integrates the half-bridge LLC switches and the rectifier bridge is presented in [16]. Its operating principle is similar to that of [15], but it still suffers from a high and weakly regulated bus voltage and relatively complex control. A quasi-single-stage AC/DC converter based on a Class-E power amplifier is proposed in [17]. This topology uses a transformer to provide isolation and transfer reactive energy for power factor correction, but the transformer coupling introduces a dead interval in the input current, resulting in excessive RMS current stress and relatively high loss. In [19], a quasi-single-stage AC/DC converter based on a boundary-conduction-mode (BCM) boost circuit and an LLC resonant converter is proposed. Two BCM boost circuits share a single boost inductor and are integrated with the half-bridge LLC switches to realize MC. However, the additional diodes increase cost and conduction losses, and the high bus voltage makes this topology suitable only for relatively low-power applications.

To alleviate the high bus-voltage problem, both topological improvements and advanced control strategies have been investigated [19,20,21]. For example, [22] proposes a dual-loop feedback strategy combining pulse-frequency modulation and interleaved asymmetric pulse-width modulation for a quasi-single-stage interleaved boost–LLC AC/DC converter derived from an interleaved boost PFC cell and a full-bridge LLC resonant cell. This method can effectively stabilize the bus voltage, but it introduces significant distortion in the input current waveform.

In addition to circuit topology and control, the magnetic components also play a critical role in the power density of front-end AC/DC converters. PFC inductors, isolation transformers, and input electromagnetic interference (EMI) filters usually occupy considerable volume and introduce additional losses, which further reduce overall efficiency. To mitigate these drawbacks, several EI-core-based magnetic integration schemes have been proposed to integrate multiple magnetic elements into a single structure, thereby improving converter power density and efficiency [23,24,25].

To overcome the aforementioned drawbacks while maintaining high efficiency, this paper proposes a new quasi-single-stage AC/DC topology employing a set of magnetically integrated differential-mode coupled inductors. The coupled inductors serve simultaneously as the boost inductors of the PFC stage and as a differential-mode EMI filter, thereby improving the input current quality and power density. In addition, a line-synchronized burst mode is introduced between the PFC and LLC stages to limit the high bus voltage under high-line, light-load conditions and to extend the high-efficiency operating range. While earlier reports focused on the fundamental topology and preliminary hardware verification, this paper delivers a far more exhaustive investigation. Key enhancements include in-depth theoretical modeling of the PFC mechanism, optimized design criteria for magnetic components and resonant networks, and a formalized control logic for burst mode operation. Moreover, the experimental scope has been significantly broadened to validate the converter’s performance under diverse operating conditions, providing a thorough assessment of both conversion efficiency and power quality (THD).

While recent quasi-single-stage AC/DC converters have achieved high efficiency, they often rely on discrete magnetic components and struggle with DC bus voltage soaring under light-load conditions. To address these challenges, this work proposes a quasi-single-stage Boost-LLC converter with the following primary contributions:

• Innovative Magnetic Integration: A single EI-core architecture is designed to consolidate interleaved boost and coupled inductors. This integration achieves significant volume reduction and mitigates core losses through inherent magnetic flux cancellation.
• Enhanced Light-Load Regulation: A zero-crossing-triggered burst mode control strategy ($Q_3$) is introduced. It actively clamps the DC bus voltage within a safe margin during high-line, light-load operation while ensuring high power factor and low THD.
• Comprehensive Modeling and Design: A detailed theoretical framework is established to analyze the power-flow characteristics in both normal and burst modes, providing systematic design guidelines for the LLC resonant tank and the integrated magnetic units.
• Experimental Validation: The proposed concepts are verified on a 400 W prototype. Experimental results demonstrate a peak efficiency of 91.9%, a PF exceeding 0.99, and superior thermal stability, confirming the practical viability of the integrated design.

The remainder of this paper is organized as follows. Section 2 presents the operating principles and power-flow characteristics. Section 3 details the theoretical analysis and design methodology for the parameters and integrated magnetics. Section 4 reports the experimental results, followed by the conclusion in Section 5.

2. Proposed Novel Quasi-Single-Stage AC/DC Converter

2.1. Circuit Topology

Figure 1 depicts the architecture of the presented high-power-factor quasi-single-stage AC/DC converter. As illustrated by the detailed schematic in Figure 2, the system integrates an interleaved Boost PFC front-end with a half-bridge series resonant back-end.

The front-end stage is designed as a soft-switching power factor corrector. This section features differential-mode coupled inductors ($L_{T1},L_{T2}$), auxiliary boost inductors ($L_{d1},L_{d2}$), and active switches ($Q_1$–$Q_3$), along with diodes ($D_1$–$D_4$) and clamping capacitors ($C_{d1},C_{d2}$). To achieve a compact design with enhanced power density, $L_{d1}$ and $L_{d2}$ are physically embedded within the magnetic structures of $L_{T1}$ and $L_{T2}$, respectively. Additionally, the incorporation of a burst switch ($Q_3$) allows the converter to maintain regulated operation across a significantly extended load range.

The downstream stage utilizes a half-bridge series resonant configuration, which shares primary switches $Q_1$ and $Q_2$ with the PFC stage to minimize the total component count. This resonant network comprises a bus capacitor $C_{Bus}$, a resonant inductor $L_r$, and a resonant capacitor $C_r$. A center-tapped transformer $T_1$, followed by rectifier diodes $D_5$–$D_6$ and an output filter capacitor $C_o$, provides the stabilized DC power to the load R.

2.2. Operation Principle of the Proposed AC/DC Converter

This section details the steady-state behavior of the proposed AC/DC topology, specifically during the normal operating phase where the burst switch $Q_3$ remains in a state of continuous conduction. To establish a clear theoretical framework and trace the energy flow accurately, a simplified model utilizing ideal components is adopted. In this analytical approach, we neglect the conduction voltage drops and switching losses of all semiconductors, while the equivalent series resistance of passive components—such as inductors and capacitors—is considered infinitesimal relative to the circuit impedance.

Owing to the operational symmetry between the positive and negative regions of the input line cycle, the following discussion focuses on the positive half-cycle to characterize the overall converter performance. Figure 3 displays the primary voltage and current waveforms during this stable operation. Based on these periodic transitions, the high-frequency switching cycle is partitioned into six discrete operating stages, with their corresponding topological configurations and equivalent current paths illustrated in Figure 4.

Mode 1 ($t_0$–$t_3$): Prior to $t_0$, $Q_1$ achieves ZVS turn-on. In this interval, the input power is rectified by $D_1$ and $D_4$ to charge $C_{Bus}$, establishing the DC link voltage $V_B$. Due to magnetic coupling, $i_{D1}$ increases linearly with slope $\alpha$ while $i_{D4}$ decreases, maintaining $i_{D4}>i_{D1}$. Simultaneously, $V_B$ excites the resonant tank ($L_r,C_r,L_m$). With $i_{Lr}>i_{Lm}$, the secondary diode $D_5$ conducts, clamping the transformer primary to $n{V}_o$ and causing $i_{Lm}$ to rise at $n{V}_o/L_m$. The resonant frequency is defined as $f_r=1/\left(2\pi \sqrt{L_r{C}_r}\right)$. During this stage, $i_{Lr}$ reverses at $t_1$, and $i_{Q3}$ crosses zero at $t_2$ as $i_{D1}$ exceeds $i_{D4}$. The mode concludes at $t_3$ when $i_{D4}$ reaches zero.

Mode 2 ($t_3$–$t_4$): With $Q_1$ still conducting, the resonant tank behavior remains consistent with Mode 1. Since $i_{D4}$ has reached zero, the differential-mode coupling is inactive. Consequently, $i_{D1}$ (which equals $i_{Q3}$) continues to rise but at a reduced slope $\beta$ ($\beta <\alpha$). This interval terminates at $t_4$ when $i_{Lr}$ matches $i_{Lm}$.

Mode 3 ($t_4$–$t_6$): At $t_4$, $D_5$ achieves ZCS turn-off while $Q_1$ remains on. The circuit enters a triple resonance phase involving $L_r$, $L_m$, and $C_r$, with the frequency shifting to $f_r=1/\left(2\pi \sqrt{(L_r+L_m)C_r}\right)$. Following $Q_1$ turn-off at $t_5$, the dead time begins. During this stage, as $i_{Lr}$ equals $i_{Lm}$, power transfer to the secondary side is suspended. The magnetizing current $i_{Lm}$ facilitates ZVS for $Q_2$ by charging the junction capacitance of $Q_1$ and discharging that of $Q_2$. This mode concludes at $t_6$ upon the conduction of $Q_2$.

Mode 4 ($t_6$–$t_9$): At $t_6$, $V_{dsQ2}$ drops to zero, enabling ZVS turn-on for $Q_2$. As $i_{Lr}$ exceeds $i_{Lm}$, the secondary diode $D_6$ conducts, clamping the transformer primary to $-n{V}_o$ and forcing $i_{Lm}$ to decrease at a rate of $n{V}_o/L_m$. During this interval, $i_{Lr}$ reverses at $t_7$. By $t_8$, $i_{Q3}$ crosses zero and reverses direction as $i_{D4}$ surpasses $i_{D1}$. This mode terminates at $t_9$ when $i_{D1}$ reaches zero.

Mode 5 ($t_9$–$t_{10}$): During this stage, $Q_2$ remains on with $i_{Q3}$ equal to $i_{D4}$. Similar to Mode 2, the resonant dynamics persist until $t_{10}$, when $i_{Lr}$ matches $i_{Lm}$, allowing $D_6$ to achieve ZCS turn-off.

Mode 6 ($t_{11}$–$t_{12}$): Following the turn-off of $Q_2$ at $t_{11}$, the circuit enters a dead-time interval. Analogous to Mode 3, the magnetizing current $i_{Lm}$ charges the junction capacitance of $Q_2$ and discharges that of $Q_1$, facilitating ZVS for the upcoming switching cycle. The operational sequence during the negative half-line cycle is symmetrical to that of the positive half-cycle and is therefore omitted here for brevity.

3. Analysis and Design of AC/DC Converter

3.1. Analysis of Pre-Stage Interleaved Boost PFC Circuit

In order to make the working principle of the quasi-single-stage AC/DC converter clearer, the simulation waveform and the equivalent circuit diagram of the front-stage converter are combined to illustrate its power factor correction ability. Based on the ideal component assumptions stated in Section 2, the mathematical relationship between the input current and circuit parameters can be derived analytically. This simplification neglects higher-order parasitic effects, allowing for a clear representation of the ripple-reduction mechanism and providing a theoretical basis for the optimization of the coupling coefficient k and voltage gain m.

Figure 5 illustrates the key current waveforms. The linear increase of $i_{Ld1}$ and $i_{Ld2}$ during switch conduction demonstrates the boost operation, while their ${180}^{\circ }$ phase shift confirms the ripple-reduction effect of the interleaved structure. To facilitate the theoretical analysis, the pre-stage equivalent circuit diagram is illustrated in Figure 6, in which inductors $L_{d1}$ and $L_{d2}$ are defined. Based on this, the detailed circuit model corresponding to each operating mode is presented in Figure 7.

Mode 1: This is shown in Figure 7a. Since the inductances of $L_{T1}$ and $L_{T2}$ are equal, they are expressed as $L_c$, and $M_c$ is the magnetic coupling coefficient. By applying Kirchhoff’s Voltage Law to the charging loops of the boost inductors, the corresponding mathematical expression for this process is as follows:

$$\left\{\begin{array}{c}{L}_d{\displaystyle \frac{\mathrm{d}{i}_{D1}}{\mathrm{d}t}}+L_c{\displaystyle \frac{\mathrm{d}{i}_{D1}}{\mathrm{d}t}}+M_c{\displaystyle \frac{\mathrm{d}{i}_{D2}}{\mathrm{d}t}}={\displaystyle \frac{v_{in}}{2}}\hfill \\ L_d{\displaystyle \frac{\mathrm{d}{i}_{D2}}{\mathrm{d}t}}+L_c{\displaystyle \frac{\mathrm{d}{i}_{D2}}{\mathrm{d}t}}+M_c{\displaystyle \frac{\mathrm{d}{i}_{D1}}{\mathrm{d}t}}=-V_B+{\displaystyle \frac{v_{in}}{2}}\hfill \end{array}\right.$$

(1)

Mode 2: This is shown in Figure 7b. In this mode, only one phase of the interleaved boost stage is conducting. The input current flows solely through the inductor $L_{d1}$ and the integrated magnetic branch. During this interval, $L_{d2}$ is disconnected from the charging loop, and the energy storage in the coupled inductors is governed by the single-phase conduction, as expressed by the following:

$$L_d{\displaystyle \frac{\mathrm{d}{i}_{D1}}{\mathrm{d}t}}+L_c{\displaystyle \frac{\mathrm{d}{i}_{D1}}{\mathrm{d}t}}={\displaystyle \frac{v_{in}}{2}}$$

(2)

Mode 3 and Mode 4 are similar to Mode 1 and Mode 2, respectively; therefore, their detailed descriptions are not repeated here. To simplify the analysis of the coupled inductors, the equations can be decoupled by calculating the sum and difference of the inductor currents. The simplified expressions can be obtained as follows:

$$\left\{\begin{array}{c}\left(L_d+L_c-M_c\right){\displaystyle \frac{\mathrm{d}\left(i_{D1}-i_{D2}\right)}{\mathrm{d}t}}=V_B\hfill \\ \left(L_d+L_c+M_c\right){\displaystyle \frac{\mathrm{d}\left(i_{D1}+i_{D2}\right)}{\mathrm{d}t}}=v_{in}-V_B\hfill \\ \left(L_d+L_c\right){\displaystyle \frac{\mathrm{d}{i}_{D1}}{\mathrm{d}t}}={\displaystyle \frac{v_{in}}{2}}\hfill \end{array}\right.$$

(3)

Assume that the current rate of change of the diode current in Mode 1 is $\alpha$ and $-\gamma$, and in Mode 2 is $\beta$. Combined with the discontinuous conduction mode (DCM) equations, the equations can be further transformed to the following:

$$\left\{\begin{array}{c}\left(L_d+L_c-M_c\right)\left(\alpha +\gamma \right)=V_B\hfill \\ \left(L_d+L_c+M_c\right)\left(\alpha -\gamma \right)=v_{in}-V_B\hfill \\ 2\left(L_d+L_c\right)\beta =v_{in}\hfill \\ \alpha D_1+\beta \left(0.5-D_1\right)=\gamma D_1\hfill \end{array}\right.$$

(4)

Consequently, $\alpha$, $\gamma$, $\beta$, and D can be denoted respectively as follows:

$$\left\{\begin{array}{c}\alpha ={\displaystyle \frac{(2V_{\overline{B}}-V_{\overline{m}})M_{ϵ}+V_{\overline{m}}(L_{\overline{d}}+L_{ϵ})}{2[{(L_{\overline{d}}+L_{ϵ})}^2-M_{ϵ}^2]}}\hfill \\ \gamma ={\displaystyle \frac{(2V_{\overline{B}}-V_{\overline{m}})(L_{\overline{d}}+L_{ϵ})+V_{\overline{m}}{M}_{ϵ}}{2[{(L_{\overline{d}}+L_{ϵ})}^2-M_{ϵ}^2]}}\hfill \\ \beta ={\displaystyle \frac{V_{\overline{m}}}{2(L_{\overline{d}}+L_{ϵ})}}\hfill \\ D={\displaystyle \frac{V_{\overline{m}}(L_{\overline{d}}+L_{ϵ}+M_{ϵ})}{2[(M_{ϵ}-L_{\overline{d}}-L_{ϵ})V_{\overline{m}}+2(L_{\overline{d}}+L_{ϵ})V_{\overline{B}}]}}\hfill \end{array}\right.$$

(5)

In summary, the inductor conduction time $T_{dis}$ is as follows:

$$T_{dis}=D{T}_s={\displaystyle \frac{V_{in}(L_d+L_c+M_c)T_s}{2[(M_c-L_d-L_c)V_{in}+2(L_d+L_c)V_B]}}$$

(6)

This expression of $T_{dis}$ is crucial for determining the average input current and ensures that the converter operates within the desired PFC range.

The currents $i_{D1}\left(t\right)$ and $i_{D2}\left(t\right)$ over one period are summarized in

Table 1. Analytical expressions of the diode currents $i_{D1}\left(t\right)$ and $i_{D2}\left(t\right)$ in different switching intervals.

Current	Interval	Mathematical Expression
$i_{D1}\left(t\right)$	$0\le t<T_{dis}$	${\displaystyle \frac{(2V_B-V_{in})M_c+V_{in}(L_d+L_c)}{2[{(L_d+L_c)}^2-M_c^2]}}t$
	$T_{dis}\le t<T_s/2$	${\displaystyle \frac{V_{in}}{2(L_d+L_c)}}t+{\displaystyle \frac{(2V_B-V_{in})(L_d+L_c)M_c+M_c^2{V}_{in}}{2(L_d+L_c)[{(L_d+L_c)}^2-M_c^2]}}{T}_{dis}$
	$T_s/2\le t<T_s/2+T_{dis}$	${\displaystyle \frac{(2V_B-V_{in})(L_d+L_c)+V_{in}{M}_c}{2[{(L_d+L_c)}^2-M_c^2]}}\left({\displaystyle \frac{T_s}{2}}+T_{dis}-t\right)$
	$T_s/2+T_{dis}\le t<T_s$	0
$i_{D2}\left(t\right)$	$T_s/2\le t<T_s/2+T_{dis}$	${\displaystyle \frac{(2V_B-V_{in})M_c+V_{in}(L_d+L_c)}{2[{(L_d+L_c)}^2-M_c^2]}}(t-T_s/2)$
	$T_s/2+T_{dis}\le t<T_s$	${\displaystyle \frac{V_{in}}{2(L_d+L_c)}}(t-T_s/2)-{\displaystyle \frac{(2V_B-V_{in})(L_d+L_c)M_c+M_c^2{V}_{in}}{2(L_d+L_c)[{(L_d+L_c)}^2-M_c^2]}}{T}_{dis}$
	$T_s\le t<T_s+T_{dis}$	${\displaystyle \frac{(2V_B-V_{in})(L_d+L_c)+V_{in}{M}_c}{2[{(L_d+L_c)}^2-M_c^2]}}(T_s+T_{dis}-t)$
	$T_s+T_{dis}\le t<3T_s/2$	0

.

The input current can be expressed as follows: $\left(i_{D1}\left(t\right)+i_{D2}\left(t\right)\right)/2$. Based on the integration of the inductor current in each mode and considering $L_c=M_c$, the average input current $I_{avg}$ in one high-frequency period can be obtained as follows:

$$\begin{array}{cc}\hfill I_{avg}& ={\displaystyle \frac{1}{T_s}}{\int }_0^{T_s}\left({\displaystyle \frac{i_{D1}\left(t\right)+i_{D2}\left(t\right)}{2}}\right)\mathrm{d}t\hfill \\ \hfill & ={\displaystyle \frac{Q(L_d+L_c)T_s{V}_{in}}{8L_c(2(L_d+L_c)V_B-L_d{V}_{in})}}\hfill \end{array}$$

(7)

where $V_{in}=V_{m}sin\left(\omega t\right)$. The RMS value of the input average current $I_{rms}$ is as follows:

$$\begin{array}{cc}\hfill I_{rms}& =\sqrt{{\displaystyle \frac{1}{\pi }}{\int }_0^{\pi }{I}_{avg}^2\mathrm{d}\theta }\hfill \\ \hfill & =\sqrt{{\displaystyle \frac{1}{\pi }}{\int }_0^{\pi }{\left({\displaystyle \frac{(2L_c+L_d)T_s{V}_b{V}_{in}}{8L_d(2(L_c+L_d)V_b-L_d{V}_{in})}}\right)}^2\mathrm{d}\theta }\hfill \end{array}$$

(8)

The average input power $P_{in}$ is obtained by integrating the instantaneous power over a half-line cycle as follows:

$$\begin{array}{cc}\hfill P_{in}& ={\displaystyle \frac{1}{\pi }}{\int }_0^{\pi }{V}_{in}{I}_{avg}\mathrm{d}\theta \hfill \\ \hfill & ={\displaystyle \frac{1}{\pi }}{\int }_0^{\pi }{\displaystyle \frac{(2L_c+L_d)T_s{V}_b{V}_m^2{sin}^2\theta }{8L_d(2(L_c+L_d)V_b-L_d{V}_{m}sin\theta )}}\mathrm{d}\theta \hfill \end{array}$$

(9)

Finally, the values of the power factor (PF) and THD at the input side are derived as follows:

$$\begin{array}{cc}\hfill \mathrm{PF}& ={\displaystyle \frac{P_{in}}{V_{1,rms}{I}_{rms}}}\hfill \\ \hfill & ={\displaystyle \frac{{\displaystyle \sqrt{{\displaystyle \frac{2}{\pi }}}{\int }_0^{\pi }\frac{{sin}^2\theta }{1+\frac{L_d}{L_c}-\frac{L_d}{L_c}\frac{V_m}{2V_b}|sin\theta |}\mathrm{d}\theta }}{{\displaystyle {\left[{\int }_0^{\pi }{\left(\frac{sin\theta }{1+\frac{L_d}{L_c}-\frac{L_d}{L_c}\frac{V_m}{2V_b}|sin\theta |}\right)}^2\mathrm{d}\theta \right]}^{1/2}}}}\hfill \end{array}$$

(10)

$$\mathrm{THD}={\displaystyle \frac{1}{\mathrm{PF}}}\sqrt{1-{\mathrm{PF}}^2}$$

(11)

The theoretical impact of design parameters on input performance is visualized in Figure 8 and Figure 9. Figure 8 confirms that an increasing coupling coefficient k effectively mitigates THD while maintaining a high PF, validating the integrated magnetic design. Similarly, Figure 9 demonstrates the sensitivity of PF and THD to the parameter m, suggesting that m must be optimized to ensure compliance with harmonic standards across the full operating range.

3.2. LLC Resonant Converter

The First Harmonic Approximation (FHA) method is adopted to analyze the steady-state characteristics of the LLC resonant converter [26,27,28]. Based on this analysis, the equivalent circuit model of the half-bridge LLC converter is derived, as shown in Figure 10.

The equivalent resistance $R_{ac}$ reflected to the primary side is derived from the transformer turns ratio n and the equivalent DC load resistance $R_{Ld}$ as follows:

$$R_{ac}={\displaystyle \frac{8n^2}{{\pi }^2}}{R}_{Ld}$$

(12)

Under different input and output conditions, the converter needs to change the switching frequency $f_s$ to obtain different gains, and maintain a stable target output by adjusting the gain to match different input conditions. The gain equation is derived as follows:

$$G(Q,K,f_n)=\left|{\displaystyle \frac{2V_p\left(t\right)}{V_{sq}\left(t\right)}}\right|=\left|{\displaystyle \frac{2V_o}{V_b}}\right|={\displaystyle \frac{1}{\sqrt{{\left(1+\frac{1}{K}·\left(1-\frac{1}{f_n^2}\right)\right)}^2+Q^2{\left(f_n-\frac{1}{f_n}\right)}^2}}}$$

(13)

Here, $f_n=f_s/f_r$ is the normalized frequency, $K=L_m/L_r$ is the inductance ratio, and $Q=\sqrt{L_r/C_r}/R_{ac}$ is defined as the system quality factor, which represents the ratio of energy stored in a single periodic resonator to the average power consumed.

Figure 11 shows the gain curve of different inductance ratios K under a fixed Q value. It is noteworthy that for smaller values of K, it is easier to achieve the same gain range. However, a wide-range frequency change will increase the control difficulty and affect the efficiency of the converter. Thus, the selection of the K value determines the turn-off current and the turn-off loss of the switch. From Figure 12, the gain curves corresponding to different Q values are obtained at a fixed inductance ratio $K=1$. It can be found that the gain of all curves at the resonant frequency point is 1 because the impedance of the resonant cavity is zero at this frequency. In addition, a proper K and Q are needed to achieve higher efficiency, ensuring the converter works below the resonant frequency across all operating conditions.

By relating the voltage gain in (13) to the equivalent load resistance reflected to the primary side, the output power $P_{LLC}$ can be expressed as follows:

$$P_{LLC}={\displaystyle \frac{V_o^2}{R_{Ld}}}={\displaystyle \frac{V_o^2\sqrt{\frac{V_b^2}{4n^2{V}_o^2}-{\left[1+\frac{1}{K}\left(1-\frac{1}{f_n^2}\right)\right]}^2}}{\frac{{\pi }^2}{8n^2}\sqrt{\frac{L_r}{C_r}}\left|f_n-\frac{1}{f_n}\right|}}$$

(14)

This equation quantifies the power delivery capability of the LLC stage as a function of the switching frequency and resonant tank parameters.

According to the power balance principle, the input power of the pre-stage PFC must equal the output power of the post-stage LLC. By equating these powers, the relationship between the DC bus voltage $V_B$ and the output power $P_{out}$ can be derived. As illustrated in Figure 13, the bus voltage increases significantly as the output power decreases. Specifically, at a constant output power, a smaller inductance ratio K results in a higher bus voltage.

It can be observed that under light-load conditions, the bus voltage exceeds the preset safety limit. Therefore, a burst switch $Q_3$ is introduced between the midpoint of the clamping capacitors and the midpoint of the half bridge. This switch regulates the PFC output voltage by intermittently cutting off the PFC stage, ensuring the circuit operates safely and efficiently under light-load conditions.

3.3. Analysis of Burst Mode Operation

Under high-line and light-load conditions, the converter faces the challenge of excessive DC bus voltage. To maintain the output voltage regulation, the LLC stage increases its switching frequency to reduce the gain. However, due to the power balance characteristics of the quasi-single-stage topology, the bus voltage $V_B$ tends to rise significantly, potentially exceeding the preset safety limit. To address this issue, the burst switch $Q_3$ is utilized to intermittently disconnect the PFC stage. When the bus voltage hits the upper threshold, $Q_3$ is turned off to cut off the input power; when the voltage drops to a lower threshold (e.g., the peak AC input voltage), $Q_3$ resumes conduction. Although this intermittent operation slightly sacrifices the power factor correction, it is essential for clamping the bus voltage within a safe operating range.

The implementation of the burst mode is illustrated in the control topology in Figure 14, with its dynamic operating waveforms presented in Figure 15. When the bus voltage $V_B$ reaches the upper threshold at $t_1$, the converter activates burst mode by disabling switch $Q_3$, thereby isolating the pre-stage PFC circuit. During this interval, the load is supported exclusively by the bus capacitor $C_{Bus}$, resulting in a linear decay of $V_B$ while the switching frequency is modulated to regulate the output. The system reverts to normal operation at $t_2$ when $V_B$ hits the lower threshold. To mitigate switching stress and EMI, the transition of $Q_3$ is synchronized with the line frequency, ensuring toggling occurs only at the zero-crossing points of the input AC voltage.

3.4. Design and Optimization of Integrated Magnetics

In the previous section, the optimal inductance ratio between the boost inductor $L_d$ and the differential-mode coupled inductor $L_T$ was analyzed theoretically. Based on these design requirements, the physical integration structure and winding arrangement of the magnetic components need to be designed to minimize volume and loss. To enhance power density, an EI core is selected to integrate the four inductors into a single module. Specifically, the coupled inductors $L_{T1}$ and $L_{T2}$ are wound around the center leg, while the boost inductors $L_{d1}$ and $L_{d2}$ are wound around the two outer legs. The detailed winding structure, which optimizes the inductor current and magnetic flux directions, is illustrated in Figure 16. This arrangement allows the outer leg windings to not only function as boost inductors but also compensate for the inductance of $L_T$, thereby achieving high integration density.

The equivalent magnetic circuit model for optimizing this integrated inductor is illustrated in Figure 17. In this model, $N_{11}$ and $N_{12}$ denote the number of turns for $L_{d1}$ (on the left outer leg) and $L_{T1}$ (on the center leg), respectively. Similarly, $N_{22}$ and $N_{21}$ represent the turns for $L_{d2}$ (on the right outer leg) and $L_{T2}$ (on the center leg). $\mathsf{\Phi }$ represents the magnetic flux in each leg, and $\mathcal{R}$ denotes the reluctance. To simplify the manufacturing process and improve practicality, a uniform air gap design is proposed, where the air gaps for the center leg and both outer legs are set to the same length.

Based on the equivalent magnetic circuit and applying Kirchhoff’s laws for magnetic circuits, the magnetic flux generated by the superposition of the windings on each leg can be derived. Assuming the reluctance of the magnetic core is negligible compared to the air gap reluctance, the flux expressions are as follows:

$$\left\{\begin{array}{c}{\mathsf{\Phi }}_{11}={\displaystyle \frac{N_{11}{i}_1}{{\mathcal{R}}_1+{\mathcal{R}}_2//{\mathcal{R}}_3}}=N_{11}{i}_1{\displaystyle \frac{{\mathcal{R}}_2+{\mathcal{R}}_3}{\mathsf{\Delta }}}\hfill \\ {\mathsf{\Phi }}_{12}={\displaystyle \frac{N_{12}{i}_1}{{\mathcal{R}}_3+{\mathcal{R}}_1//{\mathcal{R}}_2}}=N_{12}{i}_1{\displaystyle \frac{{\mathcal{R}}_1+{\mathcal{R}}_2}{\mathsf{\Delta }}}\hfill \\ {\mathsf{\Phi }}_{21}={\displaystyle \frac{N_{21}{i}_2}{{\mathcal{R}}_3+{\mathcal{R}}_1//{\mathcal{R}}_2}}=N_{21}{i}_2{\displaystyle \frac{{\mathcal{R}}_1+{\mathcal{R}}_2}{\mathsf{\Delta }}}\hfill \\ {\mathsf{\Phi }}_{22}={\displaystyle \frac{N_{22}{i}_2}{{\mathcal{R}}_2+{\mathcal{R}}_1//{\mathcal{R}}_3}}=N_{22}{i}_2{\displaystyle \frac{{\mathcal{R}}_2+{\mathcal{R}}_3}{\mathsf{\Delta }}}\hfill \end{array}\right.$$

(15)

where $\mathsf{\Delta }={\mathcal{R}}_1{\mathcal{R}}_2+{\mathcal{R}}_1{\mathcal{R}}_3+{\mathcal{R}}_2{\mathcal{R}}_3$. Under the combined action of the two inductor segment windings, the magnetic fluxes on the three magnetic columns are as follows:

$$\left\{\begin{array}{cc}\hfill {\mathsf{\Phi }}_1=& N_{12}{i}_1{\displaystyle \frac{{\mathcal{R}}_2}{\mathsf{\Delta }}}-N_{21}{i}_2{\displaystyle \frac{{\mathcal{R}}_2}{\mathsf{\Delta }}}+N_{22}{i}_2{\displaystyle \frac{{\mathcal{R}}_3}{\mathsf{\Delta }}}+N_{11}{i}_1{\displaystyle \frac{{\mathcal{R}}_3+{\mathcal{R}}_2}{\mathsf{\Delta }}}\hfill \\ \hfill {\mathsf{\Phi }}_2=& -N_{12}{i}_1{\displaystyle \frac{{\mathcal{R}}_1}{\mathsf{\Delta }}}+N_{21}{i}_2{\displaystyle \frac{{\mathcal{R}}_1}{\mathsf{\Delta }}}+N_{11}{i}_1{\displaystyle \frac{{\mathcal{R}}_3}{\mathsf{\Delta }}}+N_{22}{i}_2{\displaystyle \frac{{\mathcal{R}}_1+{\mathcal{R}}_3}{\mathsf{\Delta }}}\hfill \\ \hfill {\mathsf{\Phi }}_3=& -N_{22}{i}_2{\displaystyle \frac{{\mathcal{R}}_1}{\mathsf{\Delta }}}+N_{11}{i}_1{\displaystyle \frac{{\mathcal{R}}_2}{\mathsf{\Delta }}}+N_{12}{i}_1{\displaystyle \frac{{\mathcal{R}}_1+{\mathcal{R}}_2}{\mathsf{\Delta }}}-N_{21}{i}_2{\displaystyle \frac{{\mathcal{R}}_1+{\mathcal{R}}_2}{\mathsf{\Delta }}}\hfill \end{array}\right.$$

(16)

Subsequently, the voltage across the inductors can be expressed using Faraday’s law of induction. By substituting the flux equations into the voltage equations, the inductance matrix of the integrated component is obtained:

$$\left\{\begin{array}{c}{U}_1=N_{11}{\displaystyle \frac{d{\Phi }_1}{dt}}+N_{12}{\displaystyle \frac{d{\Phi }_3}{dt}}\hfill \\ U_2=N_{22}{\displaystyle \frac{d{\Phi }_2}{dt}}+N_{21}{\displaystyle \frac{d{\Phi }_3}{dt}}\hfill \end{array}\right.$$

(17)

$$\left(\begin{array}{c}{U}_1\\ U_2\end{array}\right)=\left(\begin{array}{cc}{L}_1& M_{12}\\ M_{21}& L_2\end{array}\right)\left(\begin{array}{c}{\displaystyle \frac{d{i}_1}{dt}}\\ {\displaystyle \frac{d{i}_2}{dt}}\end{array}\right)$$

(18)

$$\begin{array}{cc}\hfill L_1={\displaystyle \frac{1}{\mathsf{\Delta }}}[2N_{11}& N_{12}{R}_2+N_{12}^2(R_1+R_2)+N_{11}^2(R_2+R_3)]\hfill \\ \hfill L_2={\displaystyle \frac{1}{\mathsf{\Delta }}}[2N_{22}& N_{21}{R}_1+N_{21}^2(R_1+R_2)+N_{22}^2(R_1+R_3)]\hfill \\ \hfill M_{12}=& {\displaystyle \frac{1}{\mathsf{\Delta }}}[-N_{12}(N_{22}{R}_1+N_{21}(R_1+R_2))\hfill \\ & +N_{11}(-N_{21}{R}_2+N_{22}{R}_3)]\hfill \\ \hfill M_{21}=& {\displaystyle \frac{1}{\mathsf{\Delta }}}[-N_{12}(N_{22}{R}_1+N_{21}(R_1+R_2))\hfill \\ & +N_{11}(-N_{21}{R}_2+N_{22}{R}_3)]\hfill \end{array}$$

For a standard EI core, the cross-sectional area of the center leg is typically twice that of the outer legs. Consequently, under the condition of uniform air gap length, the reluctance of the outer legs is approximately twice that of the center leg, ${\mathcal{R}}_1={\mathcal{R}}_2=2{\mathcal{R}}_3=\mathcal{R}$. By substituting this geometric relationship and the turns ratio condition ($N_{11}=N_{22}=N_1$, $N_{12}=N_{21}=N_2$) into the general inductance matrix, the simplified expressions for self-inductance, mutual inductance, and the coupling coefficient are derived as follows:

$$\left\{\begin{array}{cc}\hfill L_1=L_2=L=& {\displaystyle \frac{3N_1^2+4N_1{N}_2+4N_2^2}{4R}}\hfill \\ \hfill M_{12}=M_{21}=M& ={\displaystyle \frac{-N_1^2+4N_1{N}_2+4N_2^2}{4R}}\hfill \end{array}\right.$$

(19)

$$k_c={\displaystyle \frac{M}{L}}={\displaystyle \frac{-N_1^2+4N_1{N}_2+4N_2^2}{3N_1^2+4N_1{N}_2+4N_2^2}}$$

(20)

According to (19), the winding turn ratio $N_2/N_1$ between the center leg and outer legs can be determined for a required coupling coefficient, providing a clear guideline for parameter design.

To verify the proposed design, an improved three-column coupled integrated model was established and analyzed using Ansys Maxwell electromagnetic simulation software. Figure 18 presents the simulation results of the magnetic flux density distribution under maximum input current conditions. It is evident that the optimized integration method results in a uniform magnetic flux distribution across the core, significantly improving the material utilization rate. This optimization effectively reduces the core volume and enhances the converter’s power density. Furthermore, the proposed design utilizes equal air gap lengths for all three legs, eliminating the need for complex high-precision grinding processes for different gap sizes.

Compared to conventional discrete implementations, the proposed integrated EI core consolidates the interleaved boost and coupled inductors, significantly reducing packaging volume and enhancing core utilization. Inherently, the interleaved operation induces magnetic flux cancellation within the shared core legs, which lowers the peak magnetic flux density and mitigates saturation risks. While detailed finite element modeling is omitted, the analytical evaluation of core losses and thermal distribution for such integrated magnetics is well-established, as demonstrated in [29,30]. Furthermore, the experimental prototype maintained a stable thermal equilibrium under continuous full-load conditions, empirically verifying the thermal reliability of the integrated design.

3.5. Design of Parameters

To verify the theoretical analysis, a 400 W experimental prototype was designed and built. The key specifications include a universal input voltage range of 110–220 V AC, a line frequency of 50 Hz, and a rated output voltage of 48 V.

3.5.1. Design of Boost Inductor

To achieve high efficiency, the switching frequency $f_s$ is set equal to the resonant frequency $f_r$ under the nominal input voltage of 220 V. As analyzed in the previous section, a larger inductance ratio k ($L_d/L_T$) improves the power factor correction performance. However, a larger k may also increase component stress and volume. Balancing power density, cost, and input current quality, k is chosen in the range of 0.15–0.2. Given the design conditions—input power $P_{in}=P_o$, bus voltage $V_b=360 \mathrm{V}$, and resonant frequency $f_r=300 \mathrm{kHz}$—the required boost inductance $L_d$ is calculated as follows:

$$L_d={\displaystyle \frac{1}{\pi }}{\int }_0^{\pi }{\displaystyle \frac{(2+k)T_s{V}_b{V}_{in}^2}{8P_o[2(1+k)V_b-k{v}_{in}]}}\mathrm{d}\theta \approx 45\mathsf{\mu }\mathrm{H}$$

(21)

The inductance calculated by the theoretical analysis represents the optimal parameter for a specific operating condition; however, the actual parameters must be determined by weighing all possible operating conditions. In the experimental prototype, the boost inductance $L_d$ is set to 46 $\mathsf{\mu }$$\mathrm{H}$, and the coupling inductance $L_T$ is set to 240 $\mathsf{\mu }$$\mathrm{H}$.

3.5.2. Design of DC Bus Capacitor

The design of the bus capacitor is primarily determined by the requirement to suppress the double-line-frequency voltage ripple. Assuming a unity power factor, the energy flowing into the bus capacitor $C_{Bus}$ from the input side can be expressed as follows:

$$\mathsf{\Delta }E={\int }_{t_1}^{t_2}\left[P_{in}\left(t\right)-P_{out}\left(t\right)\right]dt={\displaystyle \frac{P_{out}}{\omega }}$$

(22)

Consequently, the total energy variation in the bus capacitor is as follows:

$$\mathsf{\Delta }E={\displaystyle \frac{1}{2}}{C}_{Bus}(V_{C\_max}^2-V_{C\_min}^2)$$

(23)

By combining the above equations, the relationship between the capacitance $C_{Bus}$, the output power, and the voltage ripple can be established. To limit the bus voltage ripple $\mathsf{\Delta }{V}_{Bus}$ within 20 V at a maximum bus voltage of 420 V, the required capacitance is calculated as follows:

$$\begin{array}{cc}\hfill C_{Bus}& ={\displaystyle \frac{2P_{out}}{\omega (V_{C\_max}^2-V_{C\_min}^2)}}\hfill \\ \hfill & ={\displaystyle \frac{P_{out}}{\omega ·\mathsf{\Delta }{V}_{Bus}·V_{Bus}}}\approx 150\mathsf{\mu }\mathrm{F}\hfill \end{array}$$

(24)

In the prototype, two electrolytic capacitors (450 V, 100 $\mathsf{\mu }$$\mathrm{F}$) are connected in parallel to meet this requirement.

3.5.3. Parameters of LLC Resonant Converter

When the LLC resonant circuit operates at the resonant frequency $f_r$, the voltage gain is unity. Therefore, the turns ratio n of the transformer is determined by the nominal bus voltage and the output voltage:

$$n={\displaystyle \frac{1}{2}}{\displaystyle \frac{V_{dc\_nom}}{V_{out}}}={\displaystyle \frac{360}{2\times 48}}=3.75$$

(25)

Since the proposed converter adopts a half-bridge structure, the input voltage applied to the resonant tank is half of the bus voltage. Given that the bus voltage $V_B$ is regulated between 160 V and 420 V, the equivalent input voltage to the transformer varies from 80 V to 210 V. Consequently, the required voltage gain range M is calculated to be $M\in (0.86,2.25)$.

Based on the First Harmonic Approximation, the equivalent load impedance reflected to the primary side is calculated as $R_{ac}=66.54\mathsf{\Omega }$. To ensure ZVS across the entire operating range, the inductance ratio $\lambda$ ($L_r/L_m$) and the quality factor Q must be carefully designed. The normalized maximum operating frequency is set to $f_{n\_max}=1.4$. The inductance ratio $\lambda$ is calculated considering the no-load condition at the maximum input voltage:

$$\lambda ={\displaystyle \frac{1-M_{min}}{M_{min}}}{\displaystyle \frac{f_{n\_max}^2}{f_{n\_max}^2-1}}=0.236$$

(26)

Furthermore, to satisfy the ZVS condition under full load, the quality factor Q should be selected based on the following criteria:

$$\left\{\begin{array}{c}{Q}_{ZVS\_1}=95\%{\displaystyle \frac{\lambda }{M_{\max }}}\sqrt{{\displaystyle \frac{1}{\lambda }}+{\displaystyle \frac{M_{\max }^2}{M_{\max }^2-1}}}\hfill \\ Q_{ZVS\_2}={\displaystyle \frac{2}{\pi }}·{\displaystyle \frac{\lambda f_{n\_max}}{(\lambda +1)f_{n\_max}^2-\lambda }}{\displaystyle \frac{T_{Dead}}{R_{ac}{C}_{ZVS}}}\hfill \\ \Rightarrow Q_{ZVS}=0.31\hfill \\ Q_{ZVS}\le min\{Q_{ZVS\_1},Q_{ZVS\_2}\}\hfill \end{array}\right.$$

(27)

Finally, LLC resonant cavity parameters can be obtained. The key parameters of the prototype are summarized in

Table 2. Key parameters of the prototype.

Parameters	Value	Description
$D_{1-4}$	STPSC10065GY	High-voltage side rectifier diodes
$Q_{1-2}$	GS66508B	Switches of LLC half bridge
$Q_3$	OSG80R250F	Switch of burst mode
$D_{5-6}$	IPB020N10N5	Full-wave rectifier diodes
$L_{d1}$, $L_{d2}$	46$\mathsf{\mu }$$\mathrm{H}$	Boost inductors
$L_{T1}$, $L_{T2}$	240$\mathsf{\mu }$$\mathrm{H}$	Coupling inductors
$C_{d1}$, $C_{d2}$	1$\mathsf{\mu }$$\mathrm{F}$	Clamping capacitors
$C_{bus}$	100$\mathsf{\mu }$$\mathrm{F}$× 2	Bus capacitors
$L_r$	$10.4$$\mathsf{\mu }$$\mathrm{H}$	Resonant inductor
$L_m$	$52.5$$\mathsf{\mu }$$\mathrm{H}$	Magnetizing inductor

below.

4. Control Strategy and Experimental Results

4.1. Control Strategy

The digital control flowchart implemented on the TMS320F28379D platform (Texas Instruments, Dallas, TX, USA) is illustrated in Figure 19. The system continuously samples four key variables: output voltage, output current, input voltage, and bus voltage. Following digital signal processing, a protection routine first checks for over-current or over-voltage faults to ensure system safety. Subsequently, a determination model selects the operating mode. In normal mode, a single voltage loop employing a PI compensator regulates the output voltage by dynamically adjusting the switching frequency $f_s$ through pulse-frequency modulation control. The secondary-side synchronous rectification is independently managed by a UCC24624 controller (Texas Instruments, Dallas, TX, USA).

For the burst mode strategy, the control logic utilizes both frequency limits and bus voltage thresholds to trigger state transitions, ensuring switching actions occur at the input voltage zero-crossing points. When the load decreases, the closed-loop controller increases the switching frequency. If $f_s$ reaches the upper limit $f_{s\_max}$ (indicating minimal gain required) or the bus voltage exceeds the preset protection value, the controller waits for the next zero-crossing point of the input voltage to turn off the burst switch $Q_3$, effectively isolating the PFC stage.

During the burst off-state, the bus voltage $V_B$ drops, causing the controller to reduce $f_s$ to maintain the output voltage regulation. When $f_s$ drops to the lower limit $f_{s\_min}$ or $V_B$ falls to the nominal value, the controller detects the next zero-crossing point to turn on $Q_3$, resuming normal operation. This hysteresis control strategy effectively clamps the bus voltage within a safe range while minimizing switching stress and EMI.

The control architecture is structured as a closed-loop regulation system. The main control loop samples the output voltage $V_o$ and compares it with a reference $V_{ref}$; the resulting error is processed by a digital PI compensator to determine the switching frequency $f_s$, which serves as the modulation command for the PFM generator. From a stability perspective, the DCM operation of the PFC stage simplifies the plant into a first-order-like system and eliminates the Right-Half-Plane zero, ensuring inherent stability and a robust phase margin. Simultaneously, a supervisory logic monitors $V_B$ to manage the burst switch $Q_3$ during light-load conditions, effectively clamping the bus voltage without disturbing the primary frequency regulation loop.

4.2. Experimental Verification

In order to verify the feasibility and validity of the proposed topology and control strategy, a 400 W experimental prototype was designed and built in the laboratory. Its detailed parameters and the photograph are provided in Table 2 and Figure 20, respectively.

4.2.1. Steady-State Operation at Full Load

The experimental behavior at a nominal 220 V input and full-load condition is captured in Figure 21, where the converter operates in its standard mode. The synchronized waveforms of the input line voltage $v_{in}$, input current $i_{in}$, DC bus voltage $V_B$, and output voltage $V_o$ are presented over a complete line period. As indicated by Channel 1, the output potential is precisely regulated at 48 V. The input current $i_{in}$ in Channel 2 exhibits a highly sinusoidal profile, achieving a measured PF of 0.9968 and a THD of 4.16%. Additionally, the bus voltage maintains an average value of approximately 360 V with a peak-to-peak ripple of 20 V, which aligns perfectly with the design specifications. The overall system efficiency is recorded at 91.9%.

Figure 22 provides a detailed view of the front-end stage operation. The line-cycle and switching-cycle characteristics of $v_{in}$, $i_{in}$, and the boost inductor current $i_{Ld}$ are displayed in Figure 22a and Figure 22b, respectively. The observed DCM operation of $i_{Ld}$ validates the design objective and confirms the accuracy of the steady-state modeling presented in Section 3.

4.2.2. Soft-Switching Performance

The soft-switching characteristics are verified in Figure 23. The ZVS of the primary switch $Q_1$ is achieved, as the gate-source voltage $V_{gs}$ turns on after the drain–source voltage $V_{ds}$ drops to zero. The dead time of 55 ns is shown to be sufficient for realizing ZVS. Similarly, the ZCS of the secondary diode $D_5$ is clearly observed, as the voltage across the diode $V_{D5}$ falls only after the current $i_{D5}$ drops to zero, minimizing reverse recovery losses.

4.2.3. Burst Mode Operation

To evaluate the system’s performance at a reduced power level (25% load, 100 W), Figure 24 illustrates the converter operating in burst mode with a 220 V line input. The captured grid-cycle profiles demonstrate that despite the significant variations in switching frequency inherent to burst mode control, the output voltage remains tightly regulated at a steady 48 V. As depicted by the input current profile, deactivating the burst switch $Q_3$ effectively blocks the input current inflow, successfully decoupling the front-end stage from the grid. Furthermore, the DC bus voltage dynamics strictly follow the frequency-limit boundaries. Once the switching frequency $f_s$ hits the designed upper threshold, $Q_3$ turns off, causing $V_B$ to discharge linearly. Conversely, when $f_s$ drops to the lower limit, $Q_3$ reactivates, leading to an oscillatory rise in the bus voltage. Despite the intermittent power flow in burst mode, the zero-crossing-triggered synchronization ensures the input current follows the grid voltage phase. As indicated by the trends in

Table 3. Testing results under power variations (220 V AC).

${\mathit{P}}_{\mathbf{out}}$ (W)	PF	THD (%)	$\mathit{\eta }$ (%)
400	0.9968	4.14	91.85
380	0.9963	4.51	91.57
360	0.9963	4.46	91.12
340	0.9963	4.43	90.64
320	0.9961	4.50	90.14
300	0.9959	4.65	89.75
280	0.9953	4.92	89.13
260	0.9952	5.06	87.93

, the system maintains a high power factor (above 0.99) and a low THD (below 5.0%) even under light-load burst mode operation, which consistently complies with the IEC 61000-3-2 standards. Regarding EMI, the burst mode transitions are synchronized with the line voltage zero-crossings to minimize high $dv/dt$ and $di/dt$ at peak grid voltages. Combined with the inherent filtering of the integrated magnetic structure, the EMI emissions are effectively suppressed, ensuring reliable operation without significant high-frequency noise injection into the grid.

4.2.4. Dynamic Response

Figure 25 and Figure 26 demonstrate the transient response of the converter under load step changes. Figure 25 shows the transition between normal mode and burst mode when the load steps between 400 W and 250 W. Figure 26 shows the step response between 400 W and 300 W. In both cases, the output voltage remains stable with minimal fluctuation, validating the stability of the proposed control strategy and the seamless transition between operating modes.

4.2.5. Harmonics and Efficiency

Figure 27 shows the input current harmonics compared with those of the IEC 61000-3-2 Class C standard; the THD of the prototype satisfies the standard. Here, the input voltage is 220 V ac/50 Hz, and the prototype is in the full-load condition.

Table 3 lists the variations in the PF, THD, and efficiency as the system output power is reduced from 400 to 260 W. The PF value is always higher than 0.995 and the maximum PF value is 0.9968; the THD is always lower than 5.0% and the minimum THD is 4.14%. The maximum efficiency is 91.85%. To further justify this performance, a comprehensive loss breakdown was performed at the 400 W load based on analytical modeling and simulation verification. The total loss is calculated to be approximately $35.2$ W, aligning with the measured 91.85% efficiency. The magnetic losses ($13.4$ W, 38%) were estimated using the improved Steinmetz equation for the integrated EI core, taking into account the flux cancellation in the shared magnetic paths. Semiconductor conduction losses ($11.3$ W, 32%) were derived from the RMS currents and the $R_{ds\left(on\right)}$ of the MOSFETs, while switching losses ($8.8$ W, 25%) were extracted from PLECS/Simulink simulations, which confirmed the realization of ZVS for the LLC primary switches. The remaining $1.7$ W (5%) is attributed to auxiliary power consumption and sampling resistors.

Table 4. System characteristics with respect to the input voltage (full load).

${\mathit{V}}_{\mathbf{in}}$ (VAC)	PF	THD (%)	$\mathit{\eta }$ (%)
180	0.9985	2.83	92.76
190	0.9983	2.97	92.74
200	0.9981	3.09	92.60
210	0.9977	3.26	92.47
220	0.9968	4.14	91.84
230	0.9960	4.94	91.46
240	0.9956	5.56	90.43
250	0.9949	6.41	90.41

lists the variations in the PF, THD, and efficiency as the system input voltage is increased from 180 to 250 V in the full-load state. The PF value is always higher than 0.99 and the maximum PF value is 0.9985; the THD is always lower than 6.41% and the minimum THD is 2.83%. The maximum efficiency is 92.8%.

Table 5. Testing results under power variations (110 V AC).

${\mathit{P}}_{\mathbf{out}}$ (W)	PF	THD (%)	$\mathit{\eta }$ (%)
180	0.9996	1.25	90.47
170	0.9994	1.67	88.92
160	0.9994	1.75	88.57
150	0.9993	1.84	88.01
140	0.9993	2.04	87.44
130	0.9993	2.34	87.01
120	0.9990	2.63	86.39
110	0.9952	2.97	85.63
100	0.9986	3.49	84.69

lists the variations in the PF, THD, and efficiency as the system output power is reduced from 180 to 100 W. The PF is always higher than 0.995 and the maximum PF value is 0.9996; the THD is always lower than 3.5% and the minimum THD is 1.25%. The maximum efficiency is 90.5%.

To further demonstrate the advantages of the proposed quasi-single-stage AC/DC converter, a comprehensive performance comparison with several recent integrated topologies is summarized in

Table 6. Performance comparison with recent integrated topologies.

Parameters	Proposed	Furqan [31]	Martiš [32]	Park [33]
Application	1-$\varphi$ Front-end	1-$\varphi$ EV Charger	3-$\varphi$ AC/DC	DC/DC Resonant
Topology	Quasi-single	Quasi-single	Quasi-single	Two-stage (LLC)
Switch Count	3	4	6	4
Magnetic Core	1 (Integrated)	1 (Integrated)	1 (Integrated)	1 (Integrated)
Integration Aim	$L_{boost}$ + DM-CI	Leakage + Trans.	$L_r$ + Trans.	$L_r$ + Trans.
Power Factor	>0.99	0.982	0.998	N/A
THD	<3.8%	<5.0%	<3.0%	N/A
Power Density	High (Integrated)	Medium	Medium	Low (Two-stage)
Regulation	Burst Mode	PFM	PFM + PS	PFM
Peak Efficiency	91.9%	94.8%	96.1%	96.5%

. It can be observed that the proposed design achieves the minimum switch count (only 3 switches) and high power density while maintaining a high power factor ($>0.99$) and competitive THD. This comparison clearly highlights the superior performance and integration of the proposed topology compared to existing state-of-the-art solutions.

5. Conclusions

Based on the traditional quasi-single-stage AC/DC converter, this paper proposes a novel topology structure with an interleaved boost PFC and a half-bridge LLC converter into a single stage. A DCM interleaved boost circuit can achieve the requirement of input current tracking the input voltage automatically. Integration of switches does not affect the soft-switching characteristics of LLC, which helps the converter achieve higher efficiency. Furthermore, a burst switch is introduced to extend the operating range, ensuring stable regulation under light-load conditions. In terms of magnetic design, the proposed EI-core structure integrates the boost and coupled inductors into a single module, significantly improving the power density. A 400 W experimental prototype was developed to demonstrate the theoretical analysis. The measured results show a PF of 0.9968, the THD of 4.14%, and the efficiency of 91.9% under the full-load condition. The high consistency between these experimental metrics and the theoretical predictions confirms that the assumption of ideal components is reasonable and maintains sufficient accuracy for the design and optimization of the proposed converter.