Search Results (22)

Aperiodic pseudo-random impulse (APPI) trains represent deterministic yet reproducible sequences that mimic the irregularity of natural processes. They allow complete control over inter-spike intervals (ISIs) and pulse widths (PWs). Such signals are increasingly relevant for low-probability-of-intercept (LPI) communications, radar testing, and biomedical applications, where controlled variability mitigates adaptation and enhances stimulation efficiency. This paper presents a modular APPI generator implemented on an Arduino Mega platform, featuring programmable statistical models for ISI (exponential distribution) and PW (uniform distribution), dual-timing mechanisms (baseline loop and Timer/ISR, clear-timer on compare (CTC)), a real-time telemetry and software interface, and a safe output chain with opto-isolation and current limitation. The generator provides both reproducibility and tunable stochastic dynamics. Experimental validation includes jitter analysis, Kolmogorov–Smirnov tests, Q–Q plots, spectral and autocorrelation analysis, and load integration using a constant-current source with compliance margins. The results demonstrate that the Timer/ISR (CTC) implementation achieves significantly reduced jitter compared to the baseline loop, while maintaining the statistical fidelity of ISI and PW distributions, broad spectral characteristics, and fast decorrelation. Experimental verification was extended across a wider parameter space (λ = 0.1–100 Hz, PW = 10 µs–100 ms, 10 repetitions per condition), confirming robustness and repeatability. Experimental validation confirmed accurate Poisson/Uniform ISI generation, sub-millisecond jitter stability in the timer-controlled mode, robustness across λ = 0.1–100 Hz and PW = 10 µs–100 ms, and preliminary compliance with isolation and leakage limits. The accompanying Python GUI provides real-time control, telemetry, and data-logging capabilities. This work establishes a reproducible, low-cost, and open-source framework for APPI generation, with direct applicability in laboratory and field environments. Full article

Reliable forecasting of network QoS indicators such as latency, jitter, and packet loss is essential for managing real-time and risk-sensitive applications. This study addresses the challenge of uncertainty quantification in QoS prediction by proposing a Bayesian Regression-enhanced Long Short-Term Memory (BR-LSTM) framework. The method integrates Bayesian mean variance estimates into sequential LSTM learning to enable accurate point forecasts and well-calibrated confidence intervals. Experiments are conducted using a Mininet-based emulation platform that simulates dynamic esports network environments. The proposed model is benchmarked against ten probabilistic and deterministic baselines, including ARIMA, Gaussian Process Regression, Bayesian Neural Networks, and Monte Carlo Dropout LSTM. Results demonstrate that BR-LSTM achieves competitive accuracy while providing uncertainty intervals that improve decision confidence for Service-Level Agreement (SLA) management. The calibrated upper bound $(\mu +k\sigma )$  can be compared directly against SLA thresholds to issue early warnings and prioritize rerouting, pacing, or bitrate adjustments when the bound approaches or exceeds policy limits, while calibration controls false alarms and prevents unnecessary interventions. The findings highlight the potential of uncertainty-aware forecasting for intelligent information systems in latency-critical networks. Full article

Precise time interval generation is a cornerstone of modern measurement, automation, and distributed control systems, particularly within Internet of Things (IoT) architectures. This paper presents the design, implementation, and evaluation of a low-cost and high-precision time interval generator based on Complementary Metal-Oxide Semiconductor (CMOS) logic counters (Integrated Circuit (IC) IC 7493 and IC 4017) and inverter-based crystal oscillators (IC 74LS04). The proposed system enables frequency division from 1 MHz down to 1 Hz through a cascade of binary and Johnson counters, enhanced with digitally controlled multiplexers for output signal selection. Unlike conventional timing systems relying on expensive Field-Programmable Gate Array (FPGA) or Global Navigation Satellite System (GNSS)-based synchronization, this approach offers a robust, locally controlled reference clock suitable for IoT nodes without network access. The hardware is integrated with Arduino and ESP32 microcontrollers via General-Purpose Input/Output (GPIO) level interfacing, supporting real-time timestamping, deterministic task execution, and microsecond-level synchronization. The system was validated through Python-based simulations incorporating Gaussian jitter models, as well as real-time experimental measurements using Arduino’s micros() function. Results demonstrated stable pulse generation with timing deviations consistently below ±3 µs across various frequency modes. A comparative analysis confirms the advantages of this CMOS-based timing solution over Real-Time Clock (RTC), Network Time Protocol (NTP), and Global Positioning System (GPS)-based methods in terms of local autonomy, cost, and integration simplicity. This work provides a practical and scalable time reference architecture for educational, industrial, and distributed applications, establishing a new bridge between classical digital circuit design and modern Internet of Things (IoT) timing requirements. Full article

In the era of Industry 5.0, future wireless networks are increasingly shifting from traditional symmetric architectures toward heterogeneous and asymmetric paradigms, driven by the demand for diversified and dynamic services. This architectural evolution gives rise to complex and asymmetric flows, such as the coexistence of periodic and burst flows with varying latency, jitter, and deadline constraints, posing new challenges for deterministic transmission. Traditional time-sensitive networking (TSN) is well-suited for periodic flows but lacks the flexibility to effectively handle dynamic, asymmetric traffi. To address this limitation, we propose a two-stage asymmetric flow scheduling framework with dynamic deadline control, termed A-TSN. In the first stage, we design a Deep Q-Network-based Dynamic Injection Time Slot algorithm (DQN-DITS) to optimize slot allocation for periodic flows under varying network loads. In the second stage, we introduce the Dynamic Deadline Online (DDO) scheduling algorithm, which enables real-time scheduling for asymmetric flows while satisfying flow deadlines and capacity constraints. Simulation results demonstrate that our approach significantly reduces end-to-end latency, improves scheduling efficiency, and enhances adaptability to high-volume asymmetric traffic, offering a scalable solution for future deterministic wireless networks. Full article

The evolution of the internet towards supporting time-critical applications, such as industrial cyber-physical systems (CPSs) and autonomous systems, has created an urgent demand for networks capable of providing deterministic, low-latency communication. Autonomous vehicles represent a particularly challenging use case within this domain, requiring both reliability and determinism for massive data streams—a requirement that traditional Ethernet technologies cannot satisfy. This paper addresses this critical gap by proposing a comprehensive scheduling framework based on Time-Aware Shaping (TAS) within the Time-Sensitive Networking (TSN) standard. The framework features two key contributions: (1) a novel baseline scheduling algorithm that incorporates a sub-flow division mechanism to enhance schedulability for high-bandwidth streams, computing Gate Control Lists (GCLs) via an iterative SMT-based method; (2) a separate heuristic-based computation acceleration algorithm to enable fast, scalable GCL generation for large-scale networks. Through extensive simulations, the proposed baseline algorithm demonstrates a reduction in end-to-end latency of up to 59% compared to standard methods, with jitter controlled at the nanosecond level. The acceleration algorithm is shown to compute schedules for 200 data streams in approximately one second. The framework’s effectiveness is further validated on a real-world TSN hardware testbed, confirming its capability to achieve deterministic transmission with low latency and jitter in a physical environment. This work provides a practical and scalable solution for deploying deterministic communication in complex autonomous and cyber-physical systems. Full article

Time-Sensitive Networking (TSN) is an advance Ethernet paradigm designed to provide low delay, low jitter, and deterministic transmission time. The Cycling Queuing and Forwarding (CQF) mechanism is introduced in TSN as a scheduler to achieve precise communication. Multi-CQF, as an extension of CQF, supports the transmission of various traffic types by assigning different cycle lengths to each queue group. In its original form, Multi-CQF-based scheduling algorithms do not account for flow sorting, leading to increased transmission delays and reduced network efficiency as a network dynamically changes. To enhance the performance of Multi-CQF, this paper initially utilizes queuing theory to analyze and manage traffic, providing foundation solutions. Subsequently, Mixed Integer Programming (MIP) and the Variable Neighborhood Search Genetic Algorithm (VNS-GA) are employed to optimize transmission delay in small- and large-traffic TSN networks, respectively. MIP quickly seeks out the optimal scheduling solution for small-traffic TSN networks using branch-and-bound and linear programming techniques, while the VNS-GA improves efficiency and performance for large-traffic ones by continuously adjusting the search neighborhood strategy. Comparing with other existing schemes, computer simulation reveals that MIP reduces delay by approximately 13% on average in small-traffic TSN networks, while the VNS-GA achieves an average delay reduction of 7% in large-traffic ones. Full article

Time-triggered Ethernet combines time-triggered and event-triggered communication, and is suitable for fields with high real-time requirements. Aiming at the problem that the traditional scheduling algorithm is not effective in scheduling event-triggered messages, a message scheduling algorithm based on multi-agent reinforcement learning (MADDPG, Multi-Agent Deep Deterministic Policy Gradient) and a hybrid algorithm combining SMT (Satisfiability Modulo Theories) solver and MADDPG are proposed. This method aims to optimize the scheduling of event-triggered messages while maintaining the uniformity of time-triggered message scheduling, providing more time slots for event-triggered messages, and reducing their waiting time and end-to-end delay. Through the designed scheduling software, in the experiment, compared with the SMT-based algorithm and the traditional DQN (Deep Q-Network) algorithm, the new method shows better load balance and lower message jitter, and it is verified in the OPNET simulation environment that it can effectively reduce the delay of event-triggered messages. Full article

Time-sensitive applications require the End-to-End (E2E) delay of wireless networks to be deterministic. For example, control signals in industrial automation, intelligent transportation, and telemedicine must be transmitted to their destinations within the millisecond range, with delay jitter controlled within the microsecond range. To formulate effective policies for maintaining E2E delay within a small deterministic range, it is essential to estimate the probability density function (PDF) of E2E delay. Data-driven methods based on mixture density networks have been employed to estimate the PDF of E2E delay in wireless networks. However, in WiFi networks, the estimation results produced by existing methods exhibit significant discrepancies and fluctuations when compared to actual measurements. Motivated by this, an improved estimation method is proposed, where the delay PDF is divided into three segments with different functional expressions that are coupled together. Moreover, the parameter estimation process is implemented in two stages. First, the two division thresholds for the three segments of the PDF are calculated based on the variation trend of E2E delay measurements. Second, the remaining parameters are obtained through training using an improved mixture density network. Experimental results indicate that the E2E delay PDF obtained by the proposed method exhibits a smaller gap compared to actual measurements than existing methods. Specifically, the mean absolute errors and average fluctuation amplitudes of tail probabilities at certain delay values decrease by at least one order of magnitude. Moreover, the multiple-segmentation feature of the proposed method enhances its robustness in situations where measurement data are affected by low levels of Gaussian noise. Full article

Smart substations are an important trend in substation construction. With increasing data traffic, it is difficult for the traditional Ethernet network to meet the real-time requirements of control information in smart substations. Hence, in this paper, a deterministic network architecture for substations based on time-sensitive networks (TSN) has been developed in order to realize the domain-wide time synchronization and efficient real-time communication of the “three-layer and two-network” model in smart substations. Furthermore, a design scheme for substation automation equipment based on TSN is proposed. The proposed device realizes the timely transmission of real-time control information packets by utilizing the Earliest TxTime First (ETF) Qdisc technology of Linux and the timing sending capability of Intel 210 NIC. Furthermore, it collaborates with the time-aware shaper (TAS) traffic scheduling mechanism of TSN switches to ensure the end-to-end deterministic delay of time-sensitive traffic. As a result, it provides efficient real-time communication services with low latency and jitter for smart substation automation systems. Full article

Drone target tracking, which involves instructing drone movement to follow a moving target, encounters several challenges: (1) traditional methods need accurate state estimation of both the drone and target; (2) conventional Proportional–Derivative (PD) controllers require tedious parameter tuning and struggle with nonlinear properties; and (3) reinforcement learning methods, though promising, rely on the drone’s self-state estimation, adding complexity and computational load and reducing reliability. To address these challenges, this study proposes an innovative model-free end-to-end reinforcement learning framework, the VTD3 (Vision-Based Twin Delayed Deep Deterministic Policy Gradient), for drone target tracking tasks. This framework focuses on controlling the drone to follow a moving target while maintaining a specific distance. VTD3 is a pure vision-based tracking algorithm which integrates the YOLOv8 detector, the BoT-SORT tracking algorithm, and the Twin Delayed Deep Deterministic Policy Gradient (TD3) algorithm. It diminishes reliance on GPS and other sensors while simultaneously enhancing the tracking capability for complex target motion trajectories. In a simulated environment, we assess the tracking performance of VTD3 across four complex target motion trajectories (triangular, square, sawtooth, and square wave, including scenarios with occlusions). The experimental results indicate that our proposed VTD3 reinforcement learning algorithm substantially outperforms conventional PD controllers in drone target tracking applications. Across various target trajectories, the VTD3 algorithm demonstrates a significant reduction in average tracking errors along the X-axis and Y-axis of up to $34.35\%$ and $45.36\%$, respectively. Additionally, it achieves a notable improvement of up to $66.10\%$ in altitude control precision. In terms of motion smoothness, the VTD3 algorithm markedly enhances performance metrics, with improvements of up to $37.70\%$ in jitter and $60.64\%$ in Jerk RMS. Empirical results verify the superiority and feasibility of our proposed VTD3 framework for drone target tracking. Full article

This study investigates the optimization of traffic scheduling in autonomous vehicle networks using time-sensitive networking (TSN), a type of deterministic Ethernet. Ethernet has high bandwidth and compatibility to support various protocols, and its application range is expanding from office environments to smart factories, aerospace, and automobiles. TSN is a representative technology of deterministic Ethernet and is composed of various standards such as time synchronization, stream reservation, seamless redundancy, frame preemption, and scheduled traffic, which are sub-standards of IEEE 802.1 Ethernet established by the IEEE TSN task group. In order to ensure real-time transmission by minimizing end-to-end delay in a TSN network environment, it is necessary to schedule transmission timing in all links transmitting ST (Scheduled Traffic). This paper proposes network performance metrics and methods for applying machine learning (ML) techniques to optimize traffic scheduling. This study demonstrates that the traffic scheduling problem, which has NP-hard complexity, can be optimized using ML algorithms. The performance of each algorithm is compared and analyzed to identify the scheduling algorithm that best meets the network requirements. Reinforcement learning algorithms, specifically DQN (Deep Q Network) and A2C (Advantage Actor-Critic) were used, and normalized performance metrics (E2E delay, jitter, and guard band bandwidth usage) along with an evaluation function based on their weighted sum were proposed. The performance of each algorithm was evaluated using the topology of a real autonomous vehicle network, and their strengths and weaknesses were compared. The results confirm that artificial intelligence-based algorithms are effective for optimizing TSN traffic scheduling. This study suggests that further theoretical and practical research is needed to enhance the feasibility of applying deterministic Ethernet to autonomous vehicle networks, focusing on time synchronization and schedule optimization. Full article

Time-Sensitive Networking (TSN) and edge computing are promising networking technologies for the future of the Industrial Internet. TSN provides a reliable and deterministic low-latency communication service for edge computing. The Frame Replication and Elimination for Reliability (FRER) mechanism is important for improving the network reliability of TSN. It achieves high reliability by transmitting identical frames in parallel on two disjoint paths, while eliminating duplicated frames at the destination node. However, there are two problems with the FRER mechanism. One problem is that it does not consider the path reliability, and the other one is that it is difficult to find two completely disjoint path pairs in some cases. To solve the above problems, this paper proposes a method to find edge-disjoint path pairs considering path reliability for FRER in TSN. The method includes two parts: one is building a reliability model for paths, and the other one is computing a working path and a redundant path with the Edge-Disjoint Path Pairs Selection (EDPPS) algorithm. Theoretical and simulation results show that the proposed method effectively improves path reliability while reducing the delay jitter of frames. Compared with the traditional FRER mechanism, the proposed method reduces delay jitter by 15.6% when the network load is 0.9. Full article

Time-sensitive networks enable the high-quality mixed transmission of various types of business flows. However, the Time-Aware Scheduler mechanism fails to address the issue of interference in data flows with the same priority. This paper conducts an in-depth analysis of the store-and-forward mechanism in switches, combining it with the characteristics of critical GOOSE and SV-type flows in substations. By introducing methods such as setting offsets and allocating redundant time slots to the data flow of the transmitter in the TAS scheduling mechanism, all factors that cause conflicting interference to the data flow transmission in the TSN network are solved, and the uncertain queuing delay is eliminated. The proposed scheduling algorithm, compared to the TAS scheduling algorithm of the FIFO rule, achieves a maximum reduction of 34.35% in the transmission delay of critical business flows, while the jitter is controlled below 10 μs. Compared to the strict priority algorithm, it reduces the transmission delay by 40.26% while maintaining the standard deviation of delay within 1.59%. The maximum transmission delay and the minimum transmission delay of the data flow scheduled in this paper are between the theoretical boundary values without queuing delay, which satisfies the deterministic transmission of critical business flows under high load conditions, and provides support for future substation integrated networking and high load applications. Full article

A time jitter analysis method for an optical signal based on gated on-off optical sampling and dual-Dirac modeling is proposed and demonstrated experimentally. The optical signal under test is firstly sampled by an optical sampling pulse train generated through the gating on-off modulation of a Mach–Zehnder modulator (MZM). The sampled pulse is then broadened using optical true-time delay and electrical low-pass filtering to reduce its bandwidth to match the sample rate of a low-speed electrical analog-to-digital converter (ADC), which is used to quantify the sampled pulse. An eye diagram is obtained from the quantified data and used to plot a time jitter histogram. Finally, the dual-Dirac model is introduced to analyze the time jitter histogram to obtain the total jitter (TJ), including the deterministic jitter (DJ) and random jitter (RJ). In the experiment, a 19.05 ps TJ, including a 13.20 ps DJ and a 5.85 ps RJ, is measured for a 2.5 GHz optical signal using the proposed time jitter analysis method. The results agree well with those measured with a commercial real-time oscilloscope. Full article

Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage ring voltage-controlled oscillator (VCO) is used to transform the lower frequency reference into a high-frequency intermediate clock (600 MHz–900 MHz). Then, relying on the open-loop fractional divider, a wide frequency range of 500 kHz to 150 MHz can be generated. Due to the open-loop control characteristic, the clock generator has instantaneous frequency switching capability. In addition, phase-adjusting circuits added to the divider greatly improved the jitter performance of the output clock; its RMS jitter is 5.2 ps. This work was conducted with 0.13 μm CMOS technology. The open-loop divider occupies an area of 0.032 mm² and consumes 7.7 mW from a 1.2 V supply. Full article