Search Results (38)

The rapid advancement of artificial intelligence in automotive applications, particularly in Advanced Driver-Assistance Systems (ADAS) and smart battery management on electric vehicles, increases the demand for efficient near-sensor processing. While the problem of linear algebra in machine learning is well-addressed by existing accelerators, the computation of nonlinear activation functions is usually delegated to the host CPU, resulting in energy inefficiency and high computational costs. This paper introduces TOXOS, a RISC-V-compliant coprocessor designed to address this challenge. TOXOS implements the COordinateRotation DIgital Computer (CORDIC) algorithm to efficiently compute nonlinear functions. Taking advantage of RISC-V modularity and extendability, TOXOS seamlessly integrates with existing computing architectures. The coprocessor’s configurability enables fine-tuning of the area-performance tradeoff by adjusting the internal parallelism, the CORDIC iteration count, and the overall latency. Our implementation on a 65nm technology demonstrates a significant improvement over CPU-based solutions, showcasing a considerable speedup compared to the glibc implementation of nonlinear functions. To validate TOXOS’s real-world impact, we integrated TOXOS in an actual RISC-V microcontroller targeting the on-vehicle execution of machine learning models. This work addresses a critical gap in transcendental function computation for AI, enabling real-time decision-making for autonomous driving systems, maintaining the power efficiency crucial for electric vehicles. Full article

Ubiquitous digital array radar (UDAR) extends the integration time of moving targets by deploying a wide transmitting beam and multiple narrow receiving beams to cover the entire observed airspace. By exchanging time for energy, it effectively improves the detection ability for weak targets. Nevertheless, target motion introduces severe across-range unit (ARU), across-Doppler unit (ADU), and across-beam unit (ABU) effects, dispersing target energy across the range–Doppler-beam space. This paper proposes a beam domain angle rotation compensation and keystone-matched filtering (BARC-KTMF) algorithm to address the “three-crossing” challenge. This algorithm first corrects ABU by rotating beam–domain coordinates to align scattered energy into the final beam unit, reshaping the signal distribution pattern. Then, the KTMF method is utilized to focus target energy in the time-frequency domain. Furthermore, a special spatial windowing technique is developed to improve computational efficiency through parallel block processing. Simulation results show that the proposed approach achieves an excellent signal-to-noise ratio (SNR) gain over the typical single-beam and multi-beam long-time coherent integration (LTCI) methods under low SNR conditions. Additionally, the presented algorithm also has the capability of coarse estimation for the target incident angle. This work extends the LTCI technique to the beam domain, offering a robust framework for high-speed weak target detection. Full article

Sleep is a physiological signal which plays a vital role in maintaining human health and well-being. Polysomnographic records provide insights into the various changes occurring during sleep, and hence its study is important in diagnosing various disorders including sleep disorders. As polysomnographic records encapsulate several biological signals, an extraction of EEG signals requires efficient denoising. Thus, a reliable tool for artifact removal is essential in the field of biomedical applications. The CNN is used for its feature extraction and robustness and the least mean square filter for its noise suppression. As the techniques complement one another, a combination of both leads to a better denoised EEG signal. In this approach, CNN is used for the precise removal of artifacts and then an LMS filter is used for its effective adaptation in real-time. The hybridization of both techniques in a hardware-based environment is largely. unexplored. As a result, this study proposes an integration of convolutional neural networks and least mean square filtering for an efficient denoising of EEG signals. Both techniques are optimized to tailor the design to hardware requirements. CNN is refined using the Strassen–Winograd algorithm. The Strassen–Winograd algorithm simplifies matrix multiplication, contributing to a more hardware-optimized design. In this study LMS filtering is analyzed and optimized using several optimizations. The optimizations are two’s complement distributed arithmetic algorithm, offset binary coding-based distributed arithmetic, offset binary coding Radix 4-based distributed arithmetic, as well as a Coordinate Rotation Digital Computer. The CNN with offset binary radix 4 distributed arithmetic-based LMS filter has resulted in a decrease in area of 77% and a decrease in power by 69.1%. But, in terms of Signal to Noise Ratio, Mean Squared Error and Correlation Coefficient, the CNN with offset binary coding distributed arithmetic-based LMS filter has shown better performance. The design was synthesized and implemented in Vivado 19.1. The power and area reduction in this study makes it even more suitable for wearable devices. Full article

This article introduces an advanced theoretical approach, named the Trigonometric Kalman Filter (TKF), to enhance measurement accuracy for multi-head rotational encoders. Leveraging the processing capabilities of a Field-Programmable Gate Array (FPGA), the proposed TKF algorithm uses trigonometric functions and sophisticated signal fusion techniques to provide highly accurate real-time angle estimation with rapid response. The inclusion of the Coordinate Rotation Digital Computer (CORDIC) algorithm enables swift and efficient computation of trigonometric values, facilitating precise tracking of angular position and rotational speed. This approach represents a notable advancement in control systems, where high accuracy and minimal latency are essential for optimal performance. The paper addresses key challenges in angle measurement, particularly the signal fusion inaccuracies that often impede precision in high-demand applications. Implementing the TKF with an FPGA-based pure fixed-point method not only enhances computational efficiency but also significantly reduces latency when compared to conventional software-based solutions. This FPGA-based implementation is particularly advantageous in real-time applications where processing speed and accuracy are critical, and it demonstrates the effective integration of hardware acceleration in improving measurement fidelity. To validate the effectiveness of this approach, the TKF was rigorously tested on a precision drive control system, configured for a direct PMSM drive in an astronomical telescope mount equipped with a standard $0.5$m telescope frequently used by astronomers. This real-world application highlights the TKF’s ability to meet the stringent positioning and measurement accuracy requirements characteristic of astronomical observation, a field where minute angular adjustments are critical. The FPGA-based design enables high-frequency updates, essential for managing the minor, precise adjustments required for telescope control. The study includes a comprehensive computational analysis and experimental testing on an Altera Stratix FPGA board, presenting a detailed comparison of the TKF’s performance with other known methods, including fusion techniques such as differential methods, $\alpha$–$\beta$ filters, and related Kalman filtering applied to one sensors. The study demonstrates that the four-head fusion configuration of the TKF outperforms traditional methods in terms of measurement accuracy and responsiveness. Full article

Techniques for producing fast Huygens–Fresnel–Kirchhoff digital holograms using kernel symmetry are studied. This study demonstrates non-linear behavior in computing time, as the sampled area changes with respect to the propagated diffracted area. Given the large amount of data involved in 3D object formation, symmetries are crucial in reducing the computational time. The evaluation of diffraction patterns is implemented to avoid redundant calculations while preserving the precision of the results. This algorithm decreases the required computing time depending on the symmetry of the axes, compared to direct calculation. Interestingly, the reduction in computing time relative to the number of symmetries is not linear. Computing time curves are presented. Some redundant computations are determined by the initial conditions of the object matrix, whether even or odd, along its x and y axes. Diagonal symmetries possess intrinsic redundancy along their axes. The rotation of the image must align with the rotation of the geometric coordinates in each section to ensure accurate calculations. Full article

This paper presents a low-latency coordinate rotation digital computer (CORDIC) algorithm to accelerate the computation of arctangent functions, and it describes the corresponding iterative and pipelined architecture of this novel algorithm. As compared to the existing methods based on CORDIC, the proposed method can effectively reduce the number of iterations by dedicated pre-rotation and comparison processes. Moreover, the proposed CORDIC algorithm supports all vectors with arbitrary angles while maintaining convergence. By error analysis, the proposed algorithm can achieve the same accuracy as the conventional CORDIC algorithm during floating-point arctangent function computation and reduce the number of iterations by approximately 50%. This paper presents two new architectures—the iterative architecture, which can be more resource efficient, and the pipelined architecture, which can achieve a throughput rate of one datum per clock. Finally, the experimental comparison results indicate that the proposed method outperforms extant methods as it exhibits low latency, requires fewer resources to compute the arctangent function for floating-point inputs, and necessitates no digital signal processing (DSP) and memory for fixed-point inputs. Full article

Within the realm of digital signal processing and communication systems, FPGA-based CORDIC (Coordinate Rotation Digital Computer) processors play pivotal roles, applied in trigonometric calculations and vector operations. However, soft errors have become one of the major threats in high-reliability FPGA-based applications, potentially degrading performance and causing system failures. This paper proposes a fault classification and diagnosis method for FPGA-based CORDIC processors, leveraging Fast Fourier Transform (FFT) and Convolutional Neural Networks (CNNs). The approach involves constructing fault classification datasets, optimizing features extraction through FFT to shorten the time of diagnosis and improve the diagnostic accuracy, and employing CNNs for training and testing of faults diagnosis. Different CNN architectures are tested to explore and construct the optimal fault classifier. Experimental results encompassing simulation and implementation demonstrate the improved accuracy and efficiency in fault classification and diagnosis. The proposed method provides fault prediction with an accuracy of more than 98.6% and holds the potential to enhance the reliability and performance of FPGA-based CORDIC circuit systems, surpassing traditional fault diagnosis methods such as Sum of Square (SoS). Full article

With the rapid development of technologies like artificial intelligence, high-performance computing chips are playing an increasingly vital role. The inverse hyperbolic sine and inverse hyperbolic cosine functions are of utmost importance in fields such as image blur and robot joint control. Therefore, there is an urgent need for research into high-precision, high-performance hardware Intellectual Property (IP) for arcsinh and arccosh functions. To address this issue, this paper introduces a novel 128-bit low-latency floating-point hardware IP for arcsinh and arccosh functions, employing an enhanced Coordinate Rotation Digital Computer (CORDIC) algorithm, achieving a computation precision of 113 bits in just 32 computation cycles. This significantly enhances computational efficiency while reducing hardware implementation latency. The results indicate that, when compared to Python standard results, the calculated error of the proposed hardware IP does not exceed $8\times {10}^{-34}$. Furthermore, this paper synthesizes the completed IP using the TSMC 65 nm process, with a total IP area of 2.1056 mm${}^2$. Operating at a frequency of 300 MHz, its power is 22.4 mW. Finally, hardware implementation and resource analysis are conducted and compared on an Field Programmable Gate Array (FPGA). The results show that the improved algorithm trades a slight area increase for lower latency and higher accuracy. The designed hardware IP is expected to provide a more accurate and efficient computational tool for applications like image processing, thereby advancing technological development. Full article

With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design’s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip’s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design’s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 × 16,384 granularity, multi-channel strip-map with 65,536 × 8192 granularity, and multi-channel scan mode with 32,768 × 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data. Full article

In the field of digital signal processing, such as in navigation and radar, a significant number of high-precision arctangent function calculations are required. Lookup tables, polynomial approximation, and single/double-precision floating-point Coordinate Rotation Digital Computer (CORDIC) algorithms are insufficient to meet the demands of practical applications, where both high precision and low latency are essential. In this paper, based on the concept of trading area for speed, a four-step parallel branch iteration CORDIC algorithm is proposed. Using this improved algorithm, a 128-bit quad-precision floating-point arctangent function is designed, and the hardware circuit implementation of the arctangent algorithm is realized. The results demonstrate that the improved algorithm can achieve 128-bit floating-point arctangent calculations in just 32 cycles, with a maximum error not exceeding $2\times {10}^{-34}$ rad. It possesses exceptionally high computational accuracy and efficiency. Furthermore, the hardware area of the arithmetic unit is approximately 0.6317 mm${}^2$, and the power consumption is about 40.6483 mW under the TSMC 65 nm process at a working frequency of 500 MHz. This design can be well suited for dedicated CORDIC processor chip applications. The research presented in this paper holds significant value for high-precision and rapid arctangent function calculations in radar, navigation, meteorology, and other fields. Full article

The radial artery reflects the largest amount of physiological and pathological information about the human body. However, ultrasound signal processing involves a large number of complex functions, and traditional digital signal processing can hardly meet the requirements of real-time processing of ultrasound data. The research aims to improve computational accuracy and reduce the hardware complexity of ultrasound signal processing systems. Firstly, this paper proposes to apply the coordinate rotation digital computer (CORDIC) algorithm to the whole radial artery ultrasound signal processing, combines the signal processing characteristics of each sub-module, and designs the dynamic filtering module based on the radix-4 CORDIC algorithm, the quadrature demodulation module based on the partitioned-hybrid CORDIC algorithm, and the dynamic range transformation module based on the improved scale-free CORDIC algorithm. A digital radial artery ultrasound imaging system was then built to verify the accuracy of the three sub-modules. The simulation results show that the use of the high-performance CORDIC algorithm can improve the accuracy of data processing. This provides a new idea for the real-time processing of ultrasound signals. Finally, radial artery ultrasound data were collected from 20 volunteers using different probe scanning modes at three reference positions. The vessel diameter measurements were averaged to verify the reliability of the CORDIC algorithm for radial artery ultrasound imaging, which has practical application value for computer-aided clinical diagnosis. Full article

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA. Full article

Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB. Full article

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption algorithm, including a generalized Arnold map for the permutation. The encryption scheme demonstrated its efficiency through statistical tests, key sensitivity analysis and resistance to brute force and differential attacks. The fractional-order memristive system includes a reconfigurable coordinate rotation digital computer (CORDIC) and Grünwald–Letnikov (GL) architectures, which are essential for trigonometric and hyperbolic functions and fractional-order operator implementations, respectively. The proposed system was implemented on the Artix-7 FPGA board, achieving a throughput of 0.396 Gbit/s. Full article

This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are $821.92$ Mbits/s and $520.768$ Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications. Full article