Search Results (20)

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

We present in this paper a low-noise, low-power CMOS operational transconductance amplifier designed for the preconditioning stage of implantable neural recording microsystems. The proposed single-stage amplifier utilizes a combination of recently published techniques, including cross-coupled devices in a recycling folded-cascode topology with positive feedback, to achieve high DC voltage gain and unity-gain bandwidth while minimizing power consumption. A mixed N-type and P-type MOSFET input stage enhances input common-mode performance. Designed and implemented in a 0.18-µm CMOS process with a 1.8 V supply, post-layout simulations demonstrate an open-loop voltage gain of 97.23 dB, a 2.91 MHz unity-gain bandwidth (with a 1 pF load), and an input-referred noise of 4.75 μV_rms. The total power dissipation, including bias circuitry, is 5.43 μW, and the amplifier occupies a chip area of 0.0055 mm². Integrated into a conventional neural recording amplifier configuration, the proposed amplifier achieves a simulated input-referred noise of 5.73 µV_rms over a 1 Hz to 10 kHz bandwidth with a power consumption of 5.6 µW. This performance makes it suitable for amplifying both action potential and local field potential signals. The amplifier provides an output voltage swing of 0.976 V_pp with a total harmonic distortion of −62.68 dB at 1 kHz. Full article

The advent of CMOS power amplifiers has enabled compact and cost-effective solutions for RF applications. Among the available options, switching amplifiers are the most competitive due to their superior efficiency. In this paper, we present the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations that is compliant with the Bluetooth Low Energy (BLE) standard. The amplifier is based on a cascode configuration with charging acceleration capacitance and a combination of standard and high-voltage (HV) MOSFETs, ensuring optimal performance while maintaining device reliability. To identify the best configuration for the proposed circuit, we first provide an overview of basic class-E amplifier operations and critically review optimization techniques proposed in the scientific literature. This review is complemented by a numerical analysis of the potential advantages of using a combined standard-HV MOSFET structure. Post-layout simulations with parasitic parameter extraction demonstrated that the amplifier achieves 40.85% Power Added Efficiency and 20.52 dBm output power. Full article

GaN HEMTs based on polarization super junction (PSJ) technology offer significant improvements in efficiency and power density over conventional silicon (Si) devices due to their excellent material characteristics, which enable fast switching edges and lower specific on-resistance. However, due to the presence of an uninterrupted channel between drain and source at zero gate bias, these devices have normally-on characteristics. In this paper, the performance of a 1200 V GaN FET utilizing PSJ technology in cascode configuration is reported. The device working principle, characteristics, and switching behavior are experimentally demonstrated. The results show that cascoded GaN FETs utilizing the PSJ concept are highly promising for power device applications. Full article

This paper proposes a highly linear low-noise amplifier (LNA) using a cascode configuration. In the proposed topology, the linearity of the circuit is enhanced through the application of derivative superposition technology. The technology combines an auxiliary transistor operating in the moderate inversion region with a main transistor operating in the strong inversion region, and two degenerative inductors are connected in series at the source nodes of both transistors. The primary objective of this design is to mitigate the negative impacts of second-order and third-order nonlinearities on the third-order input intercept point (IIP3) through their interactions, thereby enhancing the linear performance of the circuit. An on-chip active bias circuit is designed to effectively address fluctuations in the IIP3 during process and temperature variations by stabilizing the transconductance of the common-source transistor, enabling the LNA to operate reliably in complex environments. During post-layout simulation in DongBu High-Tech’s 0.13 μm CMOS process, the circuit’s output third-order intercept point (OIP3) exhibits minimal fluctuations across different process corners and temperature variations. At the typical nmos and typical pmos (TT) process corner and a temperature of 30 °C, it achieves an OIP3 of 33.9 dBm with a power consumption of 42 mW sourced from a 2.8 V power supply. Furthermore, it realizes a relatively flat gain of 16 dB, a noise figure (NF) of 0.91 dB, input return loss less than −8 dB, and output return loss less than −10 dB. Full article

This paper presents a single-input multiple-output (SIMO) cascode low-noise amplifier with inductive degeneration for inter- and intra-band carrier aggregation. The proposed low-noise amplifier has two output ports for flexible operation in carrier aggregation combinations for band 30 and band 7. However, during inter- and intra-band operation, gain variation occurs depending on the output mode. To compensate for this, a switching circuit is proposed to adjust the degeneration inductor, optimizing gain performance for both modes. The switching operation can minimize the control for the dynamic range in the receiver system to support carrier aggregation. The designed low-noise amplifier was fabricated using a 65 nm CMOS process, occupying an area of 2.1 mm². In inter-band operation, the small-signal gain was measured by 18.9 dB for band 30 and 18.6 dB for band 7, with the noise figures of 1.03 dB and 1.07 dB, respectively. For intra-band operation, the small-signal gain was 17.3 dB and 17.2 dB, with the noise figures of 1.3 dB and 1.41 dB. The IIP₃ values were measured by −7.6 dBm and −6.7 dBm for inter-band, and −6.3 dBm and −6.2 dBm for intra-band. Power consumption was 8.04 mW and 7.68 mW in inter-band, and 17.04 mW and 17.64 mW in intra-band depending on the output configuration. Full article

This brief presents a continuously regulated current mirror topology capable of providing a wide range of currents with high-precision and speed control features. The circuit combines a non-linear current-mode feedback solution for fast and energy-efficient operation with an input-referred regulated-cascode configuration for precise current mirroring. The proposed implementation has an output current ranging from 100 $\mathsf{\mu }$A to 2 $\mathrm{mA}$, exhibits a fast response time of ≈100 $\mathrm{ns}$ for the full range steps, while ensuring a high power efficiency (>90%) and low current copy errors (<0.5%). Full article

The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature. Full article

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage–current (shunt–shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit’s core active elements in the main branch. The measurement results show an operational bandwidth of 2.0–29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of −5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs. Full article

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)${}^B$, 19 dB (+ 5 dB)${}^B$ and 45% (+ 5% to 10%)${}^B$, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a $732\times 605$ $\mathsf{\mu }$m${}^2$ chip’s surface. (${}^B$: indicates the improved values in the power back-off region). Full article

This paper addresses the design of a hybrid beamforming system considering the circuit parameter of six-bit millimeter-wave phase shifters based on the process design kit. The phase shifter design adopts 45 nm CMOS silicon on insulator (SOI) technology at 28-GHz. Various circuit topologies are utilized, and in particular, a design is presented based on switched LC components, connected in a cascode manner. The phase shifter configuration is connected in a cascading manner to get the 6-bit phase controls. Six different phase shifters are obtained, which are 180°, 90°, 45°, 22.5°, 11.25°, and 5.6°, with a minimum number of LC components. The circuit parameters of the designed phase shifters are then incorporated in a simulation model of hybrid beamforming for a multiuser MIMO system. The number of OFDM data symbols used in the simulation is ten for eight users, 16 QAM modulation schemes, −25 dB SNR, 120 simulation runs, and around 170 h runtime. Simulation results are obtained considering four and eight users, assuming accurate technology-based models of RFIC components of the phase shifter as well as ideal phase shifter parameters. The results indicate that the performance of the multiuser MIMO system is affected by the accuracy level of the phase shifter RF component models. The outcomes also reveal the performance tradeoff based on user data streams and the number of BS antennas. By optimizing the amount of parallel data streams per user, higher data transmission rates are achieved, while maintaining acceptable error vector magnitude (EVM) values. In addition, stochastic analysis is conducted to investigate the distribution of the RMS EVM. The outcomes show that the best fitting of RMS EVM distribution of the actual and ideal phase shifters agreed with the log-logistic and logistic distributions, respectively. The obtained (mean, variance) values of the actual phase shifters based on accurate library models are (46.997, 481.36), and for ideal components the values are (36.47, 10.44). Full article

The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor $\left(C_{ad}\right)$ with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of −112.43 and −133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V. Full article

This paper describes, based on both numerical and experimental bases, the evolution of chaotic and, in some cases, hyperchaotic attractors within mathematical models of two two-port analog functional blocks commonly used inside radio-frequency systems. The first investigated electronic circuit is known as the cascoded class C amplifier and the second network represents a resonant amplifier with Darlington’s active part. For the analysis of each mentioned block, fundamental configurations that contain coupled generalized bipolar transistors are considered; without driving force or interactions with other lumped circuits. The existence of the structurally stable strange attractors is proved via the high-resolution composition plots of the Lyapunov exponents, numerical sensitivity analysis and captured oscilloscope screenshots. Full article

This paper presents the design and implementation of a low-noise amplifier (LNA) for millimeter-wave (mm-Wave) 5G wireless applications. The LNA was based on a common-emitter configuration with cascode amplifier topology using an IHP’s 0.13 $\mathsf{\mu }$m Silicon Germanium (SiGe) heterojunction bipolar transistor (HBT) whose f_T/f_MAX/gate-delay is 360/450 GHz/2.0 ps, utilizing transmission lines for simultaneous noise and input matching. A noise figure of 3.02–3.4 dB was obtained for the entire wide bandwidth from 20 to 44 GHz. The designed LNA exhibited a gain (S_21) greater than 20 dB across the 20–44 GHz frequency range and dissipated 9.6 mW power from a 1.2 V supply. The input reflection coefficient (S_11) and output reflection coefficient (S_22) were below −10 dB, and reverse isolation (S_12) was below −55 dB for the 20–44 GHz frequency band. The input 1 dB (P1dB) compression point of −18 dBm at 34.5 GHz was obtained. The proposed LNA occupies only a 0.715 mm² area, with input and output RF (Radio Frequency) bond pads. To the authors’ knowledge, this work evidences the lowest noise figure, lowest power consumption with reasonable highest gain, and highest bandwidth attained so far at this frequency band in any silicon-based technology. Full article

This article presents a 6.89 MHz MEMS oscillator based on an ultra-low-power, low-noise, tunable gain/duty-cycle transimpedance amplifier (TIA) and a bulk Lamé-mode MEMS resonator that has a quality factor (Q) of 3.24 × 10⁶. Self-cascoding and current-starving techniques are used in the TIA design to minimize the power consumption and tune the duty-cycle of the output signal. The TIA was designed and fabricated in TSMC 65 nm CMOS process technology. Its open-loop performance has been measured separately. It achieves a tunable gain between 107.9 dBΩ and 118.1 dBΩ while dissipating only 143 nW from a 1 V supply. The duty-cycle of the output waveform can be tuned from 23.25% to 79.03%. The TIA has been interfaced and wire bonded in a series-resonant oscillator configuration with the MEMS resonator and mounted in a small cavity standard package. The closed-loop performance of the whole oscillator has been experimentally measured. It exhibits a phase noise of −128.1 dBc/Hz and −133.7 dBc/Hz at 1 kHz and 1 MHz offsets, respectively. Full article