Search Results (501)

The global expansion of interconnected edge network components requires immediate strategies for securing low-power computing nodes. Cryptographic algorithms executing over binary extension fields yield considerable computational benefits because their carry-free arithmetic significantly optimizes dynamic power consumption. However, general-purpose silicon architectures lack the dedicated hardware structures to run these finite-field operations efficiently, resulting in severe processing throughput bottlenecks. This study addresses this limitation by introducing a parallelized modular multiplier framework designed to integrate smoothly with the multicore execution environments of modern embedded platforms. Our approach deploys a progressive multiplier reduction (PMR) protocol that segments dense mathematical workloads into distributed structural thread groups. This architectural alignment allows multiplication matrices and spatial field reductions to take place concurrently, balancing localized workloads while decreasing intermediate data buffering demands. We present two distinct topological styles based on column division and row division techniques, deriving comprehensive analytical formulations to capture precise silicon area footprints, critical path delays, and total operational cycle counts. The resulting hardware metrics demonstrate that the parallel PMR design achieves a highly competitive area–delay product alongside optimized dynamic consumption characteristics. This structural paradigm delivers a scalable and robust security alternative for general edge hardware, ensuring system runtime stability while meeting tight environmental power constraints, protecting vital industrial assets, and sustaining emerging macroeconomic infrastructure. Full article

The rapid expansion of the Internet of Medical Things (IoMT) and intelligent assistive technologies has intensified the need for resource-optimized cryptographic hardware to protect sensitive biometric data. Cryptographic hardware performance relies primarily on modular arithmetic operations, especially field multiplication. Although the binary extension field provides carry-less arithmetic ideal for battery-powered devices, standard general-purpose processors lack the dedicated hardware required to execute these operations efficiently. This paper proposes a novel multicore-based modular multiplication algorithm that bridges this gap by exploiting the parallel coordination fabric and high-bandwidth interconnects of modern embedded multicore systems. Central to this work is the Progressive Product Reduction (PPR) paradigm, which optimizes hardware efficiency by integrating the multiplication and field reduction phases into a unified process, thereby minimizing intermediate data storage and computational depth. We introduce and analyze two distinct architectural strategies—Progressive Product Reduction with Column Division (PPR-CD) and Progressive Product Reduction with Row Division (PPR-RD)—and establish rigorous mathematical models to estimate hardware area, critical path delay, and exact operational latency across various core configurations. Our performance evaluation demonstrates that the PPR-RD architecture achieves superior Area-Delay Product (ADP) and energy efficiency, providing a scalable framework for securing sensitive biometric data in next-generation assistive devices. This implementation ensures robust cryptographic protection for assistive devices while maintaining energy autonomy and computational resilience essential for sustaining consumer trust, advancing global health equity, and driving financial stability in future digital economies. Full article

As the deployment of Internet of Things (IoT) ecosystems accelerates, safeguarding distributed networks against pervasive security and privacy threats has become a paramount concern. Integrating robust cryptographic protocols directly onto resource-limited edge devices offers a promising line of defense. However, severe hardware constraints historically complicate practical implementation. Because finite-field arithmetic fundamentally dictates the speed and efficiency of these cryptographic primitives, optimizing underlying multiplication techniques remains critical. To address these challenges, this paper presents an innovative, highly regular bit-serial systolic architecture tailored specifically for Dickson modular multiplication in binary extension fields. This is achieved via a streamlined systolic mapping over $GF\left(2^l\right)$ using dependency graph extraction, scheduling vectors, and projection directions. With localized pathways, the structure is highly optimized for VLSI integration. The performance and effectiveness of the proposed system are thoroughly evaluated and validated through comprehensive simulation results. Based on analytical and gate-level modeling, the design significantly enhances efficiency, lowering area by at least $162.8\%$, power by at least $214.3\%$, Area–Time Product by at least $5\%$, and Time–Power Product by at least $25.6\%$. These findings confirm that the proposed architecture substantially outperforms state-of-the-art bit-serial multipliers across these key evaluation metrics. Consequently, this solution serves as an ideal cryptographic engine for tightly constrained IoT hardware and embedded nodes, reinforcing secure and energy-aware data processing. By fostering resilient infrastructure and green digital practices, the work directly supports sustainable digital transformation and robust edge computing security. Full article

With the increasing deployment of multi-robot systems in autonomous applications, efficient task allocation is essential for coordinating multiple robots and improving system performance. To address this challenge, this paper proposes an FPGA-oriented offline–online MRTA framework that transforms online combinatorial optimization into offline decision-space compilation and hardware-efficient online strategy selection. An interval-robust dominance criterion is developed to prune strategies that cannot become optimal within a prescribed energy-cost range defined during the offline stage. Pairwise comparisons among the retained strategies are then compiled into linear decision boundaries, reducing online strategy selection to linear classification. The resulting mechanism is implemented on a Xilinx Zynq-7010 FPGA using a lightweight multiplier-free accumulation architecture. Experimental results demonstrate reduced decision latency and deterministic embedded execution. The main contribution of this study is a hardware-oriented MRTA method that replaces online combinatorial search with bounded arithmetic, comparison, and control operations suitable for FPGA implementation. Full article

Installed-capacity shares are widely used to describe power-sector transition, but per-kWh life cycle assessment (LCA) depends on delivered generation. This study develops and tests a static, annual-average generation-weighted structural diagnostic framework linking capacity-to-generation conversion, technology impact factors, scenario simulation, uncertainty analysis, optimization-boundary diagnostics, and regional proxy analysis. The lcpy Simple LCA capacity mix supplies six pedagogical S0–S5 stress-test scenarios, while UK official capacity and generation observations provide a 2020–2024 observational backcast. Relative to raw capacity shares, fixed 2024 capacity-factor weighting reduces mean generation-share error by 60.1%, and a prior-year capacity-factor model reduces it by 72.3%; these improvements are interpreted as arithmetic and structural evidence, not as evidence of dispatch-model forecasting skill. In the scenario set, generation weighting lowers GWP100 by 13.55–22.59%; the low-fossil S2 scenario gives the lowest GWP100, 0.09011 kg CO₂-eq kWh⁻¹, 50.01% below S0, and remains lowest in the tested climate-change sensitivity analyses. Multi-indicator rankings are less stable, with S2, S3, and S4 forming a low-burden group rather than a method-invariant optimum. Applying the same weighted-sum calculation to 2024 generation structures for China, the UK, and the EU gives a central-proxy China GWP100 of 0.7497 kg CO₂-eq kWh⁻¹; this is a proxy-based structural diagnostic, not a validated regionalized LCA. The results relocate the assessment focus from installed capacity to delivered generation while identifying time-varying utilization and region-specific inventories as necessary extensions. Full article

Privacy amplification (PA) is a critical process in quantum key distribution (QKD) systems, essential for eliminating information leakage to eavesdroppers and extracting unconditionally secure keys. In practical high-speed QKD systems, a large input size enables the PA scheme to approach the asymptotic limit of the secure-key rate. Concurrently, the throughput of the PA scheme must keep pace with the GHz-level clock rates of modern QKD systems to prevent it from becoming a systemic bottleneck. To globally optimize these objectives, this paper proposes a scalable and highly efficient PA scheme combining a novel $\delta$-almost-universal hash family (FM3H) with modular arithmetic hashing (MH), and proves the security of this hybrid scheme, within the information-theoretic and quantum-side framework. The proposed scheme achieves a throughput of 283 Mbps on a common mobile CPU with an input size of ${10}^{10}$ bits. NIST statistical tests and avalanche-effect measurements are reported as characterizations of the statistical properties of the output sequences. To our knowledge, this work presents the first FPGA-based implementation of a modular hashing-based PA scheme, thereby breaking the dependence of modular hashing schemes on general software platforms. In DV-QKD systems, the FPGA-based scheme achieves a throughput of $1.706$ Gbps while maintaining low resource overhead. Full article

The practicality of post-quantum lattice-based schemes is crucial for their real-world applications. Integrating these schemes requires efficient implementations through hardware, software, and algorithmic optimisation to achieve the necessary speed and resource capability. This paper aims to improve arithmetic operations in lattice-based cryptography by accelerating the Number Theoretic Transform (NTT/INTT). It optimises the transform’s main bottleneck, the twiddle-factor modular multiplication within the butterfly unit, by replacing it with constant modular multiplication derived from Barrett reduction. We introduce two constant multipliers: the Constant Barrett and a proposed Truncated-Modulus-Size Constant Barrett (TMSCB) variant, which pre-computes each twiddle constant together with its reciprocal, eliminating Barrett’s data dependency and enabling area–time trade-offs. A comprehensive evaluation of the proposed constant modular multiplication is conducted against the classical Barrett multiplication, incorporating analytical complexity analysis and experimental quantitative analysis using FPGA hardware design. The proposed optimisation technique is deployed in the hardware design of the NTT/INTT for the ML-DSA and Falcon parameter sets with optimal use of the DSP cores. Performance comparisons with state-of-the-art implementations of ML-DSA NTT show 46.73% and 29.82% execution time improvements and 17% and 35.4% area resource reductions using single- and dual-butterfly units, respectively. On the Falcon, our design achieves an execution time improvement of at least 27.6%, with area savings across several butterfly configurations. These results validate the effectiveness of the Constant Barrett optimisation technique for accelerating the NTT/INTT, paving the way for more efficient implementations in other applications. Full article

The widespread use of location-based services (LBSs) has led to the continuous collection of user location and trajectory data, increasing the risk of privacy leakage and creating a persistent tradeoff between privacy protection and data utility. To address this problem in discrete location query scenarios, this paper proposes a single-point location privacy protection method based on Q-R tree retrieval and differential privacy, termed QRDPP. QRDPP combines the adaptive spatial partitioning capability of a Q-tree with the minimum bounding rectangle (MBR)-based indexing capability of an R-tree. It applies an improved geometric privacy budget allocation strategy to leaf nodes and an arithmetic allocation strategy to non-leaf nodes, followed by Laplace perturbation of the corresponding location data and node information. For continuous trajectory query scenarios, this paper proposes a spatiotemporal generalization and differential privacy method, termed STG-DPTP, to address inadequate temporal protection, inappropriate generalization, and trajectory distortion. STG-DPTP performs hierarchical spatiotemporal clustering, separately models temporal and spatial distributions using Gaussian kernel density estimation, dynamically optimizes bandwidth parameters through Bayesian optimization, selects representative candidate subsets using the exponential mechanism, and generates protected trajectories through constrained sampling. Experiments on the GeoLife dataset evaluate the proposed methods in terms of query accuracy, computational efficiency, spatial trajectory similarity, reconstruction error, adversarial uncertainty, and temporal preservation. The results show that QRDPP improves the utility and efficiency of privacy-preserving spatial queries, while STG-DPTP better preserves the spatial distribution, trajectory structure, and temporal characteristics of the original data under the adopted differential privacy framework. Full article

A dual air-guiding variable-rate spraying system based on vision perception and control was developed to address two limitations of conventional air-assisted sprayers in high-spindle, high-density apple orchards: insufficient airflow to the upper canopy, which results in poor spray retention and inadequate pest and disease control, and continuous spraying through canopy-free gaps above the trees, which wastes spray liquid. The structural parameters of the air-guiding system were optimized using computational fluid dynamics (CFD), single-factor tests, and a central composite design, while vision-based recognition was used to automatically shut off the uppermost nozzle in canopy-free areas. The results showed that the coefficient of determination between simulated and measured air velocities was 0.982, and the mean absolute percentage error was 3.15%. The optimized deflector split ratio was 0.4; the air-outlet length, height, and width were 115, 110, and 100 mm, respectively; and the diameter of the top air outlet was 100 mm. Field tests showed that the droplet deposition density in the inner canopy was 79 droplets/cm². The deposition densities in the upper, middle, and lower canopies were 95, 94, and 92 droplets/cm², respectively, with a coefficient of variation of 0.016, demonstrating good canopy penetration and vertical deposition uniformity. When the vision-based variable-rate spraying system was enabled, the arithmetic mean reduction in off-target ground deposition across the three monitoring rows was 43.7%. These results provide a technical reference for precise and uniform pesticide application and for reducing off-target spraying in high-spindle, high-density apple orchards. Full article

Desert highways have long been subjected to aeolian sand hazards, and sand accumulation on the pavement significantly weakens the surface texture and deteriorates skid resistance, which has become one of the core contributing factors to traffic accidents on desert road sections. Current research predominantly focuses on the attenuation law of the macroscopic friction coefficient of sand-covered pavements; however, the quantitative correlation mechanism between three-dimensional micro-texture characteristics and skid resistance has not been sufficiently revealed, and there is a lack of high-precision skid resistance prediction methods under multi-condition coupling scenarios. To address the above research deficiencies, this paper takes the asphalt pavement in the Tengger Desert region as the research object. A handheld three-dimensional texture scanning system was employed to acquire the three-dimensional pavement morphology parameters under different sand coverages, and the sideway force coefficient (SFC) was synchronously measured under the corresponding conditions. Through Pearson correlation analysis and dual multiple comparison correction using the FDR-BH and Bonferroni methods, the core influencing indicators were identified. Subsequently, a skid resistance prediction model based on a BP neural network optimized by the particle swarm optimization (PSO) algorithm was constructed and horizontally compared and validated with LSTM and PSO-SVM models. The research results show the following: ① under dry conditions, the root mean square height ($S_q$), peak density ($S_{pd}$), arithmetic mean peak curvature ($S_{pc}$), valley void volume ($V_{vv}$), root mean square slope ($S_{dq}$), and developed interfacial area ratio ($S_{dr}$) are significantly linearly correlated with the SFC, among which $S_q$, $S_{pd}$, $S_{pc}$, and $V_{vv}$ are the core controlling indicators, with the absolute values of their correlation coefficients all exceeding 0.73, and ② the constructed PSO-BP prediction model achieved a coefficient of determination $R^2$ of 0.86093 on the test set, and its prediction accuracy and generalization ability are both superior to those of the LSTM and PSO-SVM models, enabling it to effectively characterize the nonlinear mapping relationship between multiple texture parameters and skid resistance. This study can provide theoretical support and a technical basis for skid resistance evaluation, sand accumulation disaster warning, and scientific maintenance decision-making for desert highways. Full article

This paper presents an optimized control strategy that enables a grid-connected photovoltaic (PV) system to operate as a static synchronous compensator (PV-STATCOM) to damp power oscillations in the transmission system, using an arithmetic optimization algorithm (AOA). The key contribution of this work is a synchronized, AOA-optimized multi-mode switching approach that includes standard PV operation, Full STATCOM, and Partial STATCOM with ramp-rate recovery, rather than relying solely on PI-gain adjustment. This is accomplished across the complete pre-fault, fault, and post-fault cycle. Under the proposed strategy, the PV system temporarily curtails its real power output when power oscillations arise following a system disturbance, thereby releasing the full inverter capacity for STATCOM operation and, hence, for oscillation damping. Once the oscillations are damped, the PV system ramps its real power back to the pre-disturbance level; at night, the inverter’s full capacity remains available for damping oscillations. The control scheme is implemented with a set of proportional–integral (PI) controllers whose parameters are tuned with the AOA, and its performance is benchmarked against tuning with the cuckoo search (CS) algorithm. Simulation results demonstrate that the AOA-tuned PV-STATCOM significantly improves damping, reduces oscillation amplitudes, maintains the point-of-common-coupling voltage within the low-voltage ride-through envelope, and keeps the system frequency within grid-code limits, thereby ensuring stable grid operation. Compared to a CS-tuned benchmark, the AOA-tuned design keeps the frequency continuously within the grid code band, settles at nominal 50 Hz, and reduces the maximum voltage overshoot from 20% to 15%. Full article

Partial shading conditions (PSCs) in photovoltaic (PV) systems generate multiple local maximum power points (LMPPs) and a single global maximum power point (GMPP) in the power–voltage (P–V) characteristics, challenging conventional maximum power point tracking (MPPT) methods. This study presents an FPGA-in-the-Loop (FIL) co-simulation of a Systematic-Sequencing Adaptive Particle Swarm Optimization (SS-APSO) algorithm for MPPT under dynamically varying shading conditions. The proposed method combines deterministic particle initialization, adaptive particle reordering, and switching among wide exploration, re-exploration and exploitation modes to enhance global search capability. The controller is implemented on a Xilinx Artix-7 FPGA using fixed-point arithmetic and a finite-state-machine architecture in VHDL and is evaluated through MATLAB/Simulink–FIL co-simulation for two PV configurations: four series-connected modules (4S) and two parallel-connected strings of two series modules (2S2P). The results demonstrate tracking efficiencies generally exceeding 98% under different shading within 0.181 s for both configurations, while in FIL co-simulation, it reaches the GMPP within 0.203. The close agreement between simulation and FIL co-simulation results demonstrates the effectiveness of the proposed SS-APSO-MPPT controller for PV systems. Full article

Modern power systems increasingly depend on energy storage devices to manage fluctuations in renewable generation and load demand. Coordinating multiple heterogeneous storage units in a grid-level system while enforcing individual state-of-charge (SoC) limits constitutes a complex, high-dimensional control problem that cannot be resolved by conventional proportional-sharing schemes. This work formulates the Distributed Optimal Energy Management (DOEM) problem for a grid comprising n parallel storage units with power-dependent efficiency and heterogeneous capacities. Optimality conditions are derived using Pontryagin’s Minimum Principle (PMP) and a smooth penalty function is introduced to handle hard SoC constraints without state-space discretisation. For the practically important class of lossless storage devices, an explicit closed-form control law is obtained, in which each unit is dispatched proportionally to its storage capacity. Numerical validation is performed on the Israeli power grid, modelling three pumped-hydro systems with a combined capacity of 8.0 GWh, using MATLAB/Simulink R2018b. Across the base net-load scenario and four additional load profiles, the cost achieved by the proposed method matches the dynamic programming (DP) benchmark within 1.1%, while the maximum state-of-charge violation is limited to 0.64% of total capacity at the default penalty setting. Computationally, the proposed update requires only 2.21 s for nine storage units compared to 59.30 s for DP, a 26.8-fold speedup, and scales with $O\left(n\right)$ arithmetic operations per time step. The results confirm a clear pathway to optimal, safe, and scalable real-time control of large-scale heterogeneous energy storage ensembles. Full article

This paper presents the hardware aspects of a Hjorth-parameter deep neural network (DNN)-based cardiac fibrillation diagnosis pipeline targeting low-power Internet of Medical Things (IoMT) devices and ASIC implementations. Building on earlier edge-to-cloud studies where Hjorth activity, mobility, and complexity were computed in software on microcontrollers and classified by a floating-point DNN, we introduce a fully synthesizable fixed-point hardware module that computes these parameters in real time, together with a quantized neural network (QNN) operating directly on the resulting fixed-point features. The Hjorth block includes derivative generation, accumulator banks, variance computation, and hardware divider and square-root units. Using the Shandong Provincial Hospital Database (SPHD) as in our previous work, we evaluate the impact of end-to-end fixed-point quantization on the AF-related arrhythmia detection performance for bit widths between 6 and 16 bits. For 10–12-bit configurations, the quantized pipeline achieves accuracy of approximately 93.7% and an area under the ROC curve (AUC) above 0.97, closely matching the floating-point baseline while significantly reducing the arithmetic complexity and memory footprint. ASIC synthesis in a 28 nm CMOS standard-cell library shows that the complete atrial detector core, integrating the Hjorth extractor and the hardware fully connected QNN, occupies on the order of $2\times {10}^4\mathsf{\mu }{\mathrm{m}}^2$ and dissipates about 3 mW, with a critical-path delay of 7.08 ns. For the optimal 10–12-bit operating points, the synthesized core achieves per-inference energy in the range of 18.6–19.0 nJ (18,600–19,000 pJ) per classification, confirming its suitability for integration into wearable and IoMT ECG monitoring nodes. These results demonstrate that co-designed fixed-point Hjorth hardware and quantized DNNs can deliver a favorable trade-off between diagnostic performance, area, power, latency, and per-inference energy compared with existing MCU-, FPGA-, and ASIC-based ECG classifiers. Full article

Resolvent Monte Carlo estimates eigenvalues of large matrices by sampling Markov chains and reading the target value off a truncated resolvent quotient, trading exact arithmetic for a stochastic error that the almost-optimal sampling scheme is designed to suppress. This paper studies when that error vanishes outright. An exact closed-form identity is derived for the variance of the moment estimators of a general, possibly signed matrix, and is used to isolate a hierarchy of zero-variance notions ranging from the most local, which constrains only the first draws, through the finite-truncation regime that a practical run can certify, to the global regime in which every moment estimator is deterministic. Determinism of the estimator is separated from correctness of the eigenvalue it reports, and the exact conditions under which each notion holds are exhibited, together with the examples that separate them. A single edgewise condition, termed the eigen-triple condition, forces the truncated quotient to equal the target eigenvalue in finite samples; the associated moment and quotient variances are second order in the maximal edge defect and vanish at the eigen-triple. A linear-time procedure certifies the condition. Full article