Search Results (306)

High parasitic capacitance from poly-insulator-poly capacitors in complementary metal oxide semiconductor (CMOS) processes presents a major bottleneck to achieving high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) in imaging systems. This study proposes a Phase-Adjustable SAR ADC that addresses this limitation through a reconfigurable architecture. The design utilizes a phase-adjustable logic unit to switch between a conventional SAR mode for high-speed operation and a noise-shaping (NS) SAR mode for high-resolution conversion, actively suppressing in-band quantization noise. An improved SAR logic unit facilitates the insertion of an adjustable phase while concurrently achieving an 86% area reduction in the core logic block. A prototype was fabricated and measured in a 0.35-µm CMOS process. In conventional mode, the ADC achieved a 7.69-bit effective number of bits at 2 MS/s. By activating the noise-shaping circuitry, performance was significantly enhanced to an 11.06-bit resolution, corresponding to a signal-to-noise-and-distortion ratio (SNDR) of 68.3 dB, at a 125 kS/s sampling rate. The results demonstrate that the proposed architecture effectively leverages the trade-off between speed and accuracy, providing a practical method for realizing high-performance ADCs despite the inherent limitations of non-ideal passive components. Full article

As a core functional device in microwave systems, attenuators play a crucial role in key aspects such as signal power regulation, amplitude attenuation, and impedance matching. Addressing the pressing technical issues currently exposed by attenuators in practical applications, such as excessive insertion loss, low attenuation accuracy, large physical dimensions, and insufficient process reliability, this paper proposes a design scheme for an RF three-bit reconfigurable stepped attenuator based on radio frequency micro-electromechanical systems (RF MEMS) switches. The attenuator employs planar integration of the T-type attenuation network, Coplanar Waveguide (CPW), Y-shaped power divider, and RF MEMS switches. While ensuring rational power distribution and stable attenuation performance over the full bandwidth, it reduces the number of switches to suppress parasitic parameters, thereby enhancing process feasibility. Test results confirm that this device demonstrates significant advancements in attenuation accuracy, achieving a precision of 1.18 dB across the 0–25 dB operational range from DC to 20 GHz, with insertion loss kept below 1.65 dB and return loss exceeding 12.15 dB. Additionally, the device boasts a compact size of merely 0.66 mm × 1.38 mm × 0.32 mm, significantly smaller than analogous products documented in existing literature. Meanwhile, its service life approaches 5 × 10⁷ cycles. Together, these two attributes validate the device’s performance reliability and miniaturization advantages. Full article

Protecting sensitive electronic interfaces is critical in industrial applications, where exposure to harsh conditions and fault events is common. This paper reviews and compares circuit techniques for the design of bidirectional protection switches, highlighting key features such as analog switching, high-voltage capability, thermal shutdown, galvanic input isolation, and adjustable current limiting. Based on this review, we propose a universal architecture that combines the most suitable building blocks identified in the literature, with a focus on options that would enable monolithic integration in high-voltage silicon-on-insulator (SOI) technology and capable of delivering up to 2 A at a maximum voltage of 200 V. The proposed architecture is intended as a design guide for realizing a universal switch, rather than a fabricated implementation. To demonstrate system-level interactions, behavioral MATLAB/Simulink (R2024b) simulations are presented using generic components, which show expected functional responses but are not tied to process-specific device models. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

Metal oxides are the most widely used material for the resistive switching layer of memristors. Nevertheless, the majority of oxide-based memristors exhibit binary switching, restricting the emulation of neuronal synaptic behaviors. In this paper, the shift from digital-to-analog switching behavior is achieved by inserting an Al₂O₃ layer atop Zr-doped HfO₂. The TiN/Al₂O₃/HZO/W/Si device exhibits long resistance state retention time and consistency. In addition, by applying a varying voltage, the device exhibits up to 20 continuous resistance states, which is highly significant for high-density storage. Upon the application of a programmable pulse signal, the device’s conductance undergoes continual alteration, reflecting long-term potentiation (LTP) and long-term depression (LTD) synaptic characteristics. The conduction mechanism of the device is studied through physical model fitting and schematic diagrams. Full article

The development of green technologies in recent years in the field of wind energy conversion into electricity implies a technology transfer from the static switching field to the energy field. This paper presents a wind turbine simulator using a hardware solution following the energy conversion of a real turbine. We implemented this solution for educational and research purposes to train students in the process of electrical conversion in wind turbines. For the simulation, we chose an E82/2300 turbine, installed by ENERCON in a nearby geographical area. The turbine has the capacity to generate 2300 kW of electricity into grids. It has a direct coupling structure of the propeller to the generator. The solution is implemented on a multi-processor architecture with analog signal processing. The structure of a wind turbine is divided into three consecutive blocks, namely TUGEN, DCDC4X, and SIN3F. Each block of the simulator is designed with electronic components. The input and output signals of these blocks have similar waveforms to real signals, and their succession is interconditioned by process parameters. The innovation of the proposed solution is provided by software engineering applied to a hardware structure. The ratio between the simulated and real values is 1:60 in order to visualize the signals on a digital oscilloscope, mainly for educational purposes. Full article

Trolox, a water-soluble analog of vitamin E, is widely used as a reference antioxidant in in vitro biochemical assays. However, its intracellular redox behavior is known to vary depending on both concentration and oxidative context. In this study, we investigated the dose-dependent antioxidant and prooxidant effects of Trolox in two cellular models, HeLa cells and 3T3 cells exposed for 1 h to increasing concentrations (2–160 µM), under both basal conditions and oxidative stress induced by hydrogen peroxide. Intracellular oxidative changes were assessed using the oxidative stress-sensitive fluorescent probe CM-H₂DCFDA. Under basal conditions, Trolox exerted slight dose-dependent antioxidant behavior in 3T3 cells on the basal production of ROS in concentrations ranging from 2 µM to 160 µM. In contrast, in HeLa cells Trolox displayed a biphasic activity: antioxidant at low doses (≤10 µM) and a switch to prooxidant behavior at higher concentrations. Under H₂O₂-induced stress, in HeLa cells Trolox retained antioxidant activity at low concentrations (≤10 µM), but this effect gradually declined at higher doses, disappearing around 80 µM and shifting to a slight prooxidant effect at 160 µM. Confocal microscopy confirmed the spectrofluorimetric results. Conversely, 3T3 cells exhibited an early shift toward prooxidant activity already at 10 µM. These findings highlight that the Trolox redox activity is determined not only by concentration but also by cell-specific intracellular environment and redox state. The study suggests caution against generalized antioxidant use of Trolox and highlights the need for specific dose–response evaluations in specific cell types and biological settings. Full article

This paper presents a low-power continuous-time delta-sigma (CT-DS) analog-to-digital converter (ADC) for use in high-sensitivity automotive-grade sub-1 GHz receivers in emerging wireless sensors network applications. The proposed ADC employs a third-order Cascade of Integrators FeedForward and Feedback (CIFF-B) loop filter operating at a sampling frequency of 150 MHz to achieve high energy efficiency and robust noise shaping. A low-noise phase-locked loop (PLL) is integrated to provide high-precision clock signals. The loop filter combines active-RC and GmC integrators with the source degeneration technique to optimize power consumption and linearity. To minimize complexity and enhance stability, a 1-bit quantizer with isolation switches and return-to-zero (RZ) digital-to-analog converters (DACs) are used in the modulator. With a 500 kHz bandwidth, the sensitivity of the receiver is −105.5 dBm. Fabricated in a 180 nm standard CMOS process, the prototype achieves a peak signal-to-noise ratio (SNR) of 76.1 dB and a signal-to-noise and distortion ratio (SNDR) of 75.3 dB, resulting in a Schreier figure of merit (FoM) of 160.7 dB based on SNDR, while consuming only 0.8 mA from a 1.8 V supply. Full article

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures. Full article

This paper investigates and characterizes a tunable inductor structure based on coupled-line configurations, referred to as a coupled-line tunable inductor (CLTI). By integrating switches along the coupled-line paths, the mutual inductance can be selectively enabled or disabled, providing a means for active inductance modulation. Spiral inductors with one-turn and two-turn cores were used in conjunction with inner-coupled-line placements to explore different coupling configurations. The test structures were implemented using printed circuit board (PCB) technology, and their performance was analyzed through electromagnetic simulations and vector network analyzer (VNA) measurements. The results confirm that switch-controlled coupled lines enable effective inductance tuning, with a measurable reduction in inductance when the coupled-line path is activated. In the switch-OFF state, only minimal performance degradation was observed due to parasitic effects. These findings provide useful insights into the practical behavior of coupled-line tunable inductors and suggest their applicability in RF circuits and adaptive analog systems, particularly where integration and compact tunability are desired. Full article

This paper proposes a cost-effective five-component discrete capacitive pre-charging circuit designed to mitigate charge redistribution effects in Analog-to-Digital Converter (ADC) inputs, particularly for low-cost embedded applications involving multiplexed high-output-resistance sources. The paper presents an analysis and experimental validation of this approach, comparing its performance against traditional methods like grounding or leaving unused multiplexer inputs floating. The proposed solution leverages external components (two capacitors and three switches) and multiplexer features to pre-charge ADC inputs to approximately half the reference voltage, which could be taken directly from the multiplexer supply rail, significantly reducing transient glitches and settling times. The experimental results demonstrate a clear improvement, achieving settling times up to 1.4 µs shorter than conventional approaches during specific multiplexer transitions. Component selection guidelines are outlined, including compensation capacitor sizing and transistor choice, addressing practical concerns such as charge injection effects. Despite certain experimental constraints noted during testing, the developed discrete pre-charging method consistently exhibited substantial performance gains. Our findings confirm that this practical, minimal-component strategy effectively addresses charge redistribution challenges, presenting an efficient solution for enhancing ADC input accuracy and response speed in resource-limited embedded sensor systems. Full article

Analog computing has re-emerged as a powerful tool for solving complex problems in various domains due to its energy efficiency and inherent parallelism. This paper summarizes recent advancements in analog computing, exploring discrete time and continuous time methods for solving combinatorial optimization problems, solving partial differential equations and systems of linear equations, accelerating machine learning (ML) inference, multi-beam beamforming, signal processing, quantum simulation, and statistical inference. We highlight CMOS implementations that leverage switched-capacitor, switched-current, and radio-frequency circuits, as well as non-CMOS implementations that leverage non-volatile memory, wave physics, and stochastic processes. These advancements demonstrate high-speed, energy-efficient computations for computational electromagnetics, finite-difference time-domain (FDTD) solvers, artificial intelligence (AI) inference engines, wireless systems, and related applications. Theoretical foundations, experimental validations, and potential future applications in high-performance computing and signal processing are also discussed. Full article

This paper presents a microcontroller-based technique for accurately measuring resistive sensors over a wide dynamic range using an adaptive constant current source. Unlike conventional voltage dividers or fixed-current methods—often limited by reduced resolution and saturation when sensor resistance varies across several decades—the proposed system dynamically adjusts the excitation current to maintain optimal Analog-to-Digital Converter (ADC) input conditions. The measurement circuit employs a fixed reference resistor and an inverting amplifier configuration, where the excitation current is generated by one or more pulse-width modulated (PWM) signals filtered through low-pass RC networks. A microcontroller selects the appropriate PWM channel to ensure that the output voltage remains within the ADC’s linear range. To support multiple sensors, an analog switch enables sequential measurements using the same dual-PWM current source. The full experimental implementation uses four op-amps to support modularity, buffering, and dual-range operation. Experimental results show accurate measurement of resistances from 1 kΩ to 100 kΩ, with maximum relative errors of 0.15% in the 1–10 kΩ range and 0.33% in the 10–100 kΩ range. The method provides a low-cost, scalable, and digitally controlled solution suitable for embedded resistive sensing applications without the need for high-resolution ADCs or programmable gain amplifiers. Full article

This paper presents a novel design for precise vertical landing of drones based on the detection of three phase shifts in the range of ±180°. The design has three inputs to which the signal transmitted from an oscillator located at the landing point arrives with different delays. The circuit increases the aerial tracking volume relative to that achieved by detectors with theoretical unambiguous detection ranges of ±90°. The phase shift measurement circuit uses an analog phase detector (mixer), detecting a maximum range of ±90°and a double multiplication of the input signals, in phase and phase-shifted, without the need to fulfill the quadrature condition. The calibration procedure, phase detector curve modeling, and calculation of the input signal phase shift are significantly simplified by the use of an automatic gain control on each branch, dwhich keeps input amplitudes to the analog phase detectors constant. A simple program to determine phase shifts and guidance instructions is proposed, which could be integrated into the same flight control platform, thus avoiding the need to add additional processing components. A prototype has been manufactured in C band to explain the details of the procedure design. The circuit uses commercial circuits and microstrip technology, avoiding the crossing of lines by means of switches, which allows the design topology to be extrapolated to much higher frequencies. Calibration and measurements at 5.3 GHz show a dynamic range greater than 50 dB and a non-ambiguous detection range of ±180°. These specifications would allow one to track the drone during the landing maneuver in an inverted cone formed by a surface with an 11 m radius at 10 m high and the landing point, when 4 cm between RF inputs is considered. The errors of the phase shifts used in the landing maneuver are less than ±3°, which translates into 1.7% losses over the detector theoretical range in the worst case. The circuit has a frequency bandwidth of 4.8 GHz to 5.6 GHz, considering a 3 dB variation in the input power when the AGC is limiting the output signal to 0 dBm at the circuit reference point of each branch. In addition, the evolution of phases in the landing maneuver is shown by means of a small simulation program in which the drone trajectory is inside and outside the tracking range of ±180°. Full article

Memristors with resistive switching capabilities are vital for information storage and brain-inspired computing, making them a key focus in current research. This study demonstrates non-volatile analog resistive switching behavior in Al/TiO_x/TiN/Si(n⁺⁺)/Al memristive devices. Analog resistive switching offers gradual, controllable conductance changes, which are essential for mimicking brain-like synaptic behavior, unlike digital/abrupt switching. The amorphous titanium oxide (TiO_x) active layer was deposited using the pulsed-DC reactive magnetron sputtering technique. The impact of increasing the oxide thickness on the electrical performance of the memristors was investigated. Electrical characterizations revealed stable, forming-free analog resistive switching, achieving endurance beyond 300 DC cycles. The charge conduction mechanisms underlying the current–voltage (I–V) characteristics are analyzed in detail, revealing the presence of ohmic behavior, Schottky emission, and space-charge-limited conduction (SCLC). Experimental results indicate that increasing the TiO_x film thickness from 31 to 44 nm leads to a notable change in the current conduction mechanism. The results confirm that the memristors have good stability (>1500 s) and are capable of exhibiting excellent long-term potentiation (LTP) and long-term depression (LTD) properties. The analog switching driven by oxygen vacancy-induced barrier modulation in the TiO_x/TiN interface is explained in detail, supported by a proposed model. The remarkable switching characteristics exhibited by the TiO_x-based memristive devices make them highly suitable for artificial synapse applications in neuromorphic computing systems. Full article