Search Results (71)

A transparent, end-to-end pathway from learning-level training to deployable fixed-point hardware is presented and framed as gradients to gates. A didactic XOR convolutional network is first employed so that backpropagation, post-training quantization in INT8, and fixed-point arithmetic can be made concrete and verified with exact checks. The same methodology was applied to a compact LeNet-5 case study. On the software side, the training-to-export flow was formalized, and a bit-accurate Python reference was constructed for the quantized network. On the hardware side, a synthesizable INT8 datapath was implemented in Verilog, including multiply–accumulate units, sigmoid activation stages, and per-layer requantization with rounding and saturation. Test benches are provided so that the exported weights and activations can be ingested, and layer-wise matches can be reported. A co-simulation harness was used to coordinate framework inference, quantization, file conversion, HDL simulation, and regression checks, which enabled deterministic comparisons of the activations, partial sums and outputs. The complete loop was mapped to Artix-7 on the CMOD A7 development board, and the resource usage, maximum clock frequency, inference latency, and throughput were determined. The approach aligns with an educational HDL-to-Caffe pipeline by using reusable parameterized Verilog primitives for convolution, pooling, activation, and fully connected layers, training in Colab with AccDNN, Caffe, quantization, and an automated bit-for-bit verification regime before FPGA synthesis. Methodological contributions are provided, including a minimal and auditable XOR CNN that exposes scales, shifts, and saturation; a practical quantization recipe with INT32 accumulation and unit tests that guarantee agreement within one least significant bit between RTL and the INT8 reference; and a scalable mapping to LeNet-5 using a row-stationary and line-buffered dataflow on an Artix-7 FPGA. Empirical evidence shows feasibility at 100 MHz with representative utilization, millisecond-scale latency and zero mismatches across large test sets, which validates the quantization configuration and the verification strategy. Full article

Semiconductor optical amplifiers (SOAs) are central to the development of ultrafast, low-power all-optical signal processing systems. Their strong nonlinear response, compact size, and compatibility with photonic integration platforms make them key enablers for implementing all-optical logic functions beyond the limitations of electronic switching. This review offers a comprehensive analysis of the principal SOA technologies used in all-optical logic gate implementations, including conventional bulk and quantum well SOAs, quantum dot SOAs (QD-SOAs), photonic crystal SOAs (PhC-SOAs), reflective SOAs (RSOAs), and carrier reservoir SOAs (CR-SOAs). For each architecture, we examine the carrier dynamics, gain recovery mechanisms, saturation behavior, and fabrication considerations, together with their associated nonlinear effects such as cross-gain modulation, cross-phase modulation, and four-wave mixing. We further evaluate reported implementations of key logic operations—AND, NAND, OR, NOR, XOR, and XNOR—highlighting performance trade-offs in terms of speed, extinction ratio, operational power, integration complexity, and scalability. The review concludes with current challenges and emerging research directions aimed at realizing fully integrated, high-speed, and energy-efficient all-optical logic systems based on next-generation SOA technologies. Full article

This study examined the correlation between the number of delay flip-flops (D-FFs) connected after each ring oscillator (RO) and the bit distribution of random number sequences in an RO-based random number generator (RNG). In our previous research, unstable input signals to the XOR gate contributed to differences in bit distribution. Based on these results, we simulated how combining signals with biased distributions through XOR gates affects the overall bit distribution. Beyond this, we also conducted simulations where the inputs to the XOR gate included not just {0, 1} signals, but also three-state signals incorporating metastable states. We then proposed using multi-D-FFs as synchronization circuits for RO signals and performed analyses on RO-based RNG implementations by estimating metastable output conditions and conducting NIST Special Publication 800-22 tests regarding bit distributions. These results confirm that inserting two or more D-FFs after RO signals improves the bit distribution of RO-based RNG implementations. Full article

The performance of true random number generators (TRNGs) fundamentally depends on the quality of their entropy sources (ESs). However, many FPGA-friendly designs still rely on a single mechanism and struggle to achieve both high throughput and low resource cost. To address this challenge, we propose the exclusive OR (XOR) Self-Feedback Ring Oscillator (XORSFRO), an XORNOT-style TRNG that integrates two cross-connected XOR gates with a short inverter delay chain and clocked sampling. A unified timing model is developed to describe how arrival-time skew and gate inertial delay lead to cancellation, narrow-pulse generation, and inversion events, thereby enabling effective entropy extraction. Experimental results on Xilinx Spartan-6 and Artix-7 FPGAs demonstrate that XORSFRO maintains stable operation across standard process–voltage–temperature (PVT) variations, while achieving higher throughput and lower hardware overhead compared with recent FPGA-based TRNGs. The generated bitstreams pass both the NIST SP 800-22 and NIST SP 800-90B test suites without post-processing. Full article

This paper presents fine-grained Field Programmable Gate Arrays (FPGA) architectures for the Advanced Encryption Standard (AES) MixColumns and InvMixColumns transformations, targeting improved performance and resource utilization. The proposed method reformulates these operations as boolean functions directly mapped onto FPGA Lookup-Table (LuT) primitives, replacing conventional xor-based arithmetic with memory-level computation. A custom MATLAB-R2019a-based pre-synthesis optimization algorithm performs algebraic simplification and shared subexpression extraction at the polynomial level of Galois Field $GF(2^8)$, reducing redundant logic memory. This architecture, LuT-level optimization minimizes the delay of the complex InvMixColumns stage and narrows the delay gap between encryption (1.305 ns) and decryption (1.854 ns), resulting in a more balanced and power-efficient AES pipeline. Hardware implementation on a Xilinx Virtex-5 FPGA confirms the efficiency of the design, demonstrating competitive performance compared to state-of-the-art FPGA realizations. Its fast performance and minimal hardware requirements make it well suited for real-time secure communication systems and embedded platforms with limited resources that need reliable bidirectional data processing. Full article

With the increasing demand for ultrafast optical signal processing, silicon-on-silica (SoS) waveguides with ring resonators have emerged as a promising platform for integrated all-optical logic gates (AOLGs). In this work, we design and simulate a SoS-based waveguide structure, operating at the telecommunication wavelength of 1550 nm, consisting of a circular ring resonator coupled to straight bus waveguides using Lumerical FDTD solutions. The design achieves a high Q-factor of 11,071, indicating low optical loss and strong light confinement. The evanescent coupling between the ring and waveguides, along with optimized waveguide dimensions, enables efficient interference, realizing a complete suite of AOLGs (XOR, AND, OR, NOT, NOR, NAND, and XNOR). Numerical simulations demonstrate robust performance across all gates, with high contrast ratios between 11.40 dB and 13.72 dB and an ultra-compact footprint of 1.42 × 1.08 µm². The results confirm the device’s capability to manipulate optical signals at data rates up to 55 Gb/s, highlighting its potential for scalable, high-speed, and energy-efficient optical computing. These findings provide a solid foundation for the future experimental implementation and integration of SoS-based photonic logic circuits in next-generation optical communication systems. Full article

The paper introduces the concept of a True Random Number Generator (TRNG) based on an unstable circuit that uses only two types of logic devices: XOR gates and logic inverters forming delay lines. The core circuit ensures randomness in both the voltage (logical state) and time domains (duration of autonomous operation), while utilizing very few resources. Due to its low complexity, the proposed TRNG can be easily implemented in reconfigurable devices without sophisticated components such as Digital Clock Managers (DCM), Phase Locked Loops (PLL), or dedicated IP cores. The authors present a theoretical analysis of the TRNG using a Simulink macromodel, demonstrating chaotic behavior, and describe its implementation on a Complex Programmable Logic Device (CPLD) and additional verification on an FPGA. The randomness quality of the TRNG was validated using the standard National Institute of Standards and Technology (NIST) SP 800-22 battery of tests. Full article

This study explores the integration of reduced graphene oxide (rGO) into an optoelectronic XOR logic gate to enhance BB84 protocol encryption in quantum communication systems. The research leverages the nonlinear optical properties of rGO, specifically its nonlinear refraction characteristics, in combination with a Michelson interferometer to implement an optoelectronic XOR gate. rGO samples were deposited using the Langmuir–Blodgett technique and characterized in morphology and structure. The optical setup utilized a frequency-modulated laser signal for the interferometer and a pulsed laser system that generates the quantum information carrier. This integration of quantum encryption with nonlinear optical materials offers enhanced security against classical attacks while providing adaptability for various applications from secure communications to quantum AI. Full article

We propose a high-speed all-optical logic gate design based on silicon racetrack and ring resonators patterned on a silica substrate. The architecture features racetrack resonators at both the input and output, with a central ring resonator enabling the required phase-sensitive interference for logic processing. Logic operations are achieved through the interplay of constructive and destructive interference induced by phase-shifted input beams. Using the finite-difference time-domain (FDTD) method in Lumerical software, we simulate and demonstrate seven fundamental Boolean logic functions, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, at an operating wavelength of 1.33 µm. The system supports a data rate of 47.94 Gb/s, suitable for ultrafast optical computing. The performance is quantitatively evaluated using the contrast ratio (CR) as the reference metric, with more than acceptable values of 13.09 dB (XOR), 13.84 dB (AND), 13.14 dB (OR), 13.80 dB (NOT), 14.53 dB (NOR), 13.80 dB (NAND), and 14.67 dB (XNOR), confirming strong logic level discrimination. Comparative analysis with existing optical gate designs underscores the advantages of our compact silicon-on-silica structure in terms of speed, CR performance, and integration potential. This study validates the effectiveness of racetrack–ring configurations for next-generation all-optical logic circuits. Full article

Encryption and decryption are essential components in signal processing and optical communication systems, providing data confidentiality, integrity, and secure high-speed transmission. We present a novel design and simulation of an all-optical encryption and decryption system operating at 120 Gb/s using carrier reservoir semiconductor optical amplifiers (CR-SOAs) embedded in Mach–Zehnder interferometers (MZIs). The architecture relies on two consecutive exclusive-OR (XOR) logic gates, implemented through phase-sensitive interference in the CR-SOA-MZI structure. The first XOR gate performs encryption by combining the input data signal with a secure optical key, while the second gate decrypts the encoded signal using the same key. The fast gain recovery and efficient carrier dynamics of CR-SOAs enable a high-speed, low-latency operation suitable for modern photonic networks. The system is modeled and simulated using Mathematica Wolfram, and the output quality factors of the encrypted and decrypted signals are found to be 28.57 and 14.48, respectively, confirming excellent signal integrity and logic performance. The influence of key operating parameters, including the impact of amplified spontaneous emission noise, on system behavior is also examined. This work highlights the potential of CR-SOA-MZI-based designs for scalable, ultrafast, and energy-efficient all-optical security applications. Full article

Quantum-dot cellular automata (QCA) offer a high-performance, low-power alternative to traditional VLSI technology for nanocomputing. However, the existing metal-dot QCA-based parity generators and checker circuits suffer from increased energy dissipation, larger area consumption, and complex multilayered layouts, limiting their practical feasibility. This work designs a 3-bit parity generator and 4-bit checker to address these challenges using an optimized modified majority voter-based Ex-OR gate in QCA. A single-layered layout was simulated in QCADesigner 2.0.3, avoiding crossovers to reduce fabrication complexity. Energy analysis using QCADesigner-E reveals 34.4 meV energy consumption, achieving 31% energy efficiency and 75% area efficiency in the context of QCA costs compared to recent designs. The proposed circuit highlights the unique potential of QCA as a scalable, energy-efficient solution for high-density next-generation computing systems. Full article

This paper provides a comprehensive survey of 58 lightweight block ciphers (LWBCs) introduced between 2018 and 2025, designed specifically for securing resource-constrained environments such as the Internet of Things (IoTs). The ciphers are systematically categorized into five structural classes: substitution-permutation network (SPN), Feistel network (FN), generalized Feistel network (GFN), addition-rotation-XOR (ARX), and hybrid architectures. For each cipher, key characteristics—block size, key length, structural design, number of rounds, implementation cost in gate equivalents (GEs), and known limitations—are analyzed in detail. The study offers an in-depth comparative assessment of performance, security, and implementation efficiency, providing a clear understanding of design trade-offs and cryptographic innovations. By consolidating and evaluating recent advancements in lightweight cryptography, this survey fills a crucial gap in the literature. It equips researchers, engineers, and system designers with the insights needed to make informed decisions when selecting or developing efficient cryptographic solutions tailored for modern IoTs systems. Its comprehensive scope and practical relevance make it an essential reference for advancing secure, lightweight cryptographic implementations in an increasingly connected world. Full article

Microring resonators, known for their compact size, wavelength selectivity, and high-quality factor, enable efficient light manipulation, making them ideal for photonic logic applications. This paper presents the design and simulation of seven fundamental all-optical logic gates—XOR, AND, OR, NOT, NOR, NAND, and XNOR—using a seven-microring silicon-on-silica waveguide. Operating at the standard telecommunication wavelength of 1.55 µm, the proposed design exploits constructive and destructive interferences caused by phase changes in the input optical beams to perform logic operations. Numerical simulations, conducted using Lumerical FDTD Solutions, validate the performance of the logic gates, with the contrast ratio (CR) as the primary evaluation metric. The proposed design achieves CR values of 14.04 dB for XOR, 15.14 dB for AND, 15.85 dB for OR, 13.42 dB for NOT, 12.02 dB for NOR, 12.75 dB for NAND, and 14.10 dB for XNOR, significantly higher than those reported in previous works. This results in a data rate of 199.8 Gb/s, facilitated by a compact waveguide size of 1.30 × 1.35 μm². These results highlight the potential of silicon photonics and microring resonators in enabling high-performance, energy-efficient, and densely integrated optical computing and communication systems. Full article

Substitution boxes (S-Boxes) function as essential nonlinear elements in contemporary cryptographic systems, offering robust protection against cryptanalytic attacks. This study presents a novel technique for generating compact 8-bit S-Boxes based on multiplication in the Galois Field $GF\left(2^4\right)$. The goal of this method is to create S-Boxes with low hardware implementation cost while ensuring cryptographic properties. Experimental results indicate that the suggested S-Boxes achieve a nonlinearity value of 112, matching the AES S-Box. They also maintain other cryptographic properties, such as the Bit Independence Criterion (BIC), the Strict Avalanche Criterion (SAC), Differential Approximation Probability, and Linear Approximation Probability, within acceptable security thresholds. Notably, compared to existing studies, the proposed S-Box architecture demonstrates enhanced hardware efficiency, significantly reducing resource utilization in implementations. Specifically, the implementation cost of the S-Box consists of 31 XOR gates, 32 two-input AND gates, 6 two-input OR gates, and 2 MUX21s. Moreover, this work provides a thorough assessment of the S-Box, covering cryptographic properties, side channel attacks, and implementation aspects. Furthermore, the study estimates the quantum resource requirements for implementing the S-Box, including an analysis of CNOT, Toffoli, and NOT gate counts. Full article

The three-level simplified neutral point clamped (3L-SNPC) inverter has received increasing attention in recent years due to its potential applications in electrical drives and smart grids with renewable energy integration. However, most existing research has primarily focused on control development, with limited studies investigating modulation strategies or analyzing inverter losses under varying operating conditions. These aspects are critical for practical industrial applications. To address this gap, this paper proposes a novel carrier-based space vector pulse width modulation (CB-SVPWM) strategy for the 3L-SNPC inverter, aimed at simplifying PWM implementation and reducing cost. The proposed modulation strategy is experimentally evaluated by comparing inverter losses and total harmonic distortion with those of the conventional three-level neutral point clamped (3L-NPC) inverter under an equivalent carrier-based modulation scheme. A comprehensive comparative analysis is conducted across the full modulation range to demonstrate the effectiveness of the proposed approach, achieving a 13.2% reduction in total power loss, a 33.6% improvement in execution time, and maintaining a comparable weighted total harmonic distortion (WTHD) with a deviation within 0.04% of the conventional 3L-NPC inverter. Full article