Search Results (39)

High-Bandwidth Memory (HBM) enables the bandwidth required by modern AI and high-performance computing, yet its three dimensional stack traps heat and amplifies thermo mechanical stress. We first review how conventional solutions such as heat spreaders, microchannels, high density Through-Silicon Vias (TSVs), and Mass Reflow Molded Underfill (MR MUF) underfills lower but do not eliminate the internal thermal resistance that rises sharply beyond 12layer stacks. We then synthesize recent hybrid bonding studies, showing that an optimized Cu pad density, interface characteristic, and mechanical treatments can cut junction-to-junction thermal resistance by between 22.8% and 47%, raise vertical thermal conductivity by up to three times, and shrink the stack height by more than 15%. A meta-analysis identifies design thresholds such as at least 20% Cu coverage that balances heat flow, interfacial stress, and reliability. The review next traces the chain from Coefficient of Thermal Expansion (CTE) mismatch to Cu protrusion, delamination, and warpage and classifies mitigation strategies into (i) material selection including SiCN dielectrics, nano twinned Cu, and polymer composites, (ii) process technologies such as sub-200 °C plasma-activated bonding and Chemical Mechanical Polishing (CMP) anneal co-optimization, and (iii) the structural design, including staggered stack and filleted corners. Integrating these levers suppresses stress hotspots and extends fatigue life in more than 16layer stacks. Finally, we outline a research roadmap combining a multiscale simulation with high layer prototyping to co-optimize thermal, mechanical, and electrical metrics for next-generation 20-layer HBM. Full article

In this paper, a novel through-silicon via (TSV) fabrication strategy based on through-hole structures is proposed for low-cost and low-complexity manufacturing. Compared to conventional TSV fabrication processes, this method significantly simplifies the process flow by employing double-sided liner deposition, double-sided barrier layer/seed layer formation, and double-sided Cu electroplating. This method enhances the TSV stability by eliminating Cu contamination issues during chemical–mechanical polishing (CMP), which are a common challenge in traditional blind via fabrication processes. Additionally, the liner and barrier layer/seed layer achieve a high step coverage exceeding 80%, ensuring excellent conformality and structural integrity. For electroplating, a multi-stage bi-directional electroplating technique is introduced to enable void-free Cu filling in TSVs. The fabricated TSVs exhibit an ultra-low leakage current of 135 fA at 20 V, demonstrating their potential for advancing 3D integration technologies in heterogeneous integration. Full article

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs. Full article

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps’ reliability, through-silicon vias’ (TSVs) and redistribution layers’ (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing. Full article

As semiconductor packaging technologies face limitations, through-silicon via (TSV) technology has emerged as a key solution to extending Moore’s law by achieving high-density, high-performance microelectronics. TSV technology enables enhanced wiring density, signal speed, and power efficiency, and offers significant advantages over traditional wire-bonding techniques. However, achieving fine-pitch and high-density interconnects remains a challenge. Solder flip-chip microbumps have demonstrated their potential to improve interconnect reliability and performance. However, the environmental impact of lead-based solders necessitates a shift to lead-free alternatives. This review highlights the transition from Sn-Pb solders to lead-free options, such as Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Zn, and Bi- or In-based alloys, driven by regulatory and environmental considerations. Although lead-free solders address environmental concerns, their higher melting points pose challenges such as thermal stress and chip warping, which affect device reliability. To overcome these challenges, the development of low-melting-point solder alloys has gained momentum. This study examines advancements in low-temperature solder technologies and evaluates their potential for enhancing device reliability by mitigating thermal stress and ensuring long-term stability. Full article

This study introduces a manufacturing process based on industrial MEMS technology, enabling the production of diverse sensor designs customized for a wide range of absolute pressure measurements. Using monocrystalline silicon as the structural material minimizes thermal stresses and eliminates temperature-dependent semiconductor effects, as silicon functions solely as a mechanical material. Integrating a eutectic bonding process in the sensor fabrication allows for a reliable operation at temperatures up to 350 °C. The capacitive sensor electrodes are enclosed within a silicon-based Faraday cage, ensuring effective shielding against external electrostatic interference. An innovative Through-Silicon Via (TSV) design, sealed using gold–gold (Au-Au) diffusion and gold–silicon (Au-Si) eutectic bonding, further enhances the mechanical and thermal stability of the sensors, even under high-temperature conditions. The unfilled TSV structure mitigates mechanical stress from thermal expansion. The sensors exhibited excellent performance, achieving a linearity of 99.994%, a thermal drift of −0.0164% FS (full scale)/K at full load and 350 °C, and a high sensitivity of 34 fF/kPa. These results highlight the potential of these sensors for high-performance applications across various demanding environments. Full article

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method. Full article

A meta-surface-based arbitrary bandwidth filter realization method for terahertz (THz) future communications is presented. The approach involves integrating a meta-surface-based bandstop filter into an ultra-wideband (UWB) bandpass filter and adjusting the operating frequency range of the meta-surface bandstop filter to realize the design of arbitrary bandwidth filters. It effectively addresses the complexity of designing traditional arbitrary bandwidth filters and the challenges in achieving impedance matching. To underscore its practicality, the paper employs silicon substrate integrated gap waveguide (SSIGW) and this method to craft a THz filter. To begin, design equations for electromagnetic band gap (EBG) structures were developed in accordance with the requirements of through-silicon via (TSV) and applied to the design of the SSIGW. Subsequently, this article employs equivalent transmission line models and equivalent circuits to conduct theoretical analyses for both the UWB passband and the meta-surface stopband portions. The proposed THz filter boasts a center frequency of 0.151 THz, a relative bandwidth of 6.9%, insertion loss below 0.68 dB, and stopbands exceeding 20 GHz in both upper and lower ranges. The in-band group delay is 0.119 ± 0.048 ns. Compared to reported THz filters, the SSIGW filter boasts advantages such as low loss and minimal delay, making it even more suitable for future wireless communication. Full article

A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with good scalability, a small area, and high performance using vertical through-silicon vias (TSV). However, the failure rate of TSV, which is higher than that of horizontal links, causes unpredictable topology variations and requires adaptive routing algorithms to select the available paths dynamically. Most works have aimed at the congestion control for TSV partially 3D NoCs to bypass the TSV reliability issue, while others have focused on the fault tolerance in TSV fully connected 3D NoCs and ignored the performance degradation. In order to adequately improve reliability and performance in TSV fully connected 3D NoC architectures, we propose a TSV-aware Reinforcement Learning Assisted Routing Algorithm (RLARA) for fault-tolerant 3D NoCs. The proposed method can take advantage of both the high throughput of fully connected TSVs and the cost-effective fault tolerance of partially connected TSVs using periodically updated TSV-aware Q table of reinforcement learning. RLARA makes the distributed routing decision with the lowest TSV utilization to avoid the overheating of the TSVs and mitigate the reliability problem. Furthermore, the K-means clustering algorithm is further adopted to compress the routing table of RLARA by exploiting the routing information similarity. To alleviate the inherent deadlock issue of adaptive routing algorithms, the link Q-value from reinforcement learning is combined with the router status based in buffer utilization to predict the congestion and enable RLARA to perform best even under a high traffic load. The experimental results of the ablation study on simulator Garnet 2.0 verify the effectiveness of our proposed RLARA under different fault models, which can perform better than the latest 3D NoC routing algorithms, with up to a 9.04% lower average delay and 8.58% higher successful delivered rate. Full article

The main challenges in 3D metrology involve measuring TSVs etched with very high aspect ratios, where the via depth to diameter ratio approaches 10:1–20:1. In this paper, we introduce an innovative approach to enhance our in-house spectroscopic reflectometer module by integrating aperture technology, resulting in a substantial amplification of interference signals. Our system offers the flexibility to conduct measurements on an average number of TSVs, individual TSVs, or specific periodic arrays of TSVs. Additionally, we demonstrate the utility of the spectroscopic reflectometer as a non-destructive, high-speed metrology solution for in-line monitoring of TSV etch uniformity. Through a series of experimental trials in a reactive ion etch (RIE) process, we show that leveraging feedback data from the reflectometer leads to marked improvements in etch depth uniformity. Full article

This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs. Full article

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore’s Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed. Full article

Following Moore’s law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 $\mathsf{\mu }$m long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks. Full article

Radio frequency (RF) systems utilizing through-silicon vias (TSVs) have been widely used in the aerospace and nuclear industry, which means that studying the total ionizing dose (TID) effect on TSV structures has become necessary. To investigate the TID effect on TSV structures, a 1D TSV capacitance model was established in COMSOL Multiphysics (COMSOL), and the impact of irradiation was simulated. Then, three types of TSV components were designed, and an irradiation experiment based on them was conducted, to validate the simulation results. After irradiation, the S₂₁ degraded for 0.2 dB, 0.6 dB, and 0.8 dB, at the irradiation dose of 30 krad (Si), 90 krad (Si), 150 krad (Si), respectively. The variation trend was consistent with the simulation in the high-frequency structure simulator (HFSS), and the effect of irradiation on the TSV component was nonlinear. With the increase in the irradiation dose, the S₂₁ of TSV components deteriorated, while the variation of S₂₁ decreased. The simulation and irradiation experiment validated a relatively accurate method for assessing the RF systems’ performance under an irradiation environment, and the TID effect on structures similar to TSVs in RF systems, such as through-silicon capacitors. Full article

In our work, we studied thin nickel films deposited by electroless plating for use as a barrier and seed layer in the through-silicon vias (TSV) technology. El-Ni coatings were deposited on a copper substrate from the original electrolyte and with the use of various concentrations of organic additives in the composition of the electrolyte. The surface morphology, crystal state, and phase composition of the deposited coatings were studied by SEM, AFM, and XRD methods. The El-Ni coating deposited without the use of an organic additive has an irregular topography with rare phenocrysts of globular formations of hemispherical shape and a root mean square roughness value of 13.62 nm. The phosphorus concentration in the coating is 9.78 wt.%. According to the results of the X-ray diffraction studies of El-Ni, the coating deposited without the use of an organic additive has a nanocrystalline structure with an average nickel crystallite size of 2.76 nm. The influence of the organic additive is seen in the smoothening of the samples surface. The root mean square roughness values of the El-Ni sample coatings vary within 2.09–2.70 nm. According to microanalysis data the phosphorus concentration in the developed coatings is ~4.7–6.2 wt.%. The study of the crystalline state of the deposited coatings by X-ray diffraction made it possible to detect two arrays of nanocrystallites in their structure, with average sizes of 4.8–10.3 nm and 1.3–2.6 nm. Full article