Search Results (60)

Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) almost all use Multi-Version Concurrency Control (MVCC) protocol to ensure data consistency. MVCC allows multiple transactions to execute concurrently without lock conflicts, reducing the wait time between read and write operations, and thereby significantly increasing the throughput of NVM OLTP engines. However, it requires garbage collection (GC) to clean up the obsolete tuple versions to prevent storage overflow, which consumes additional system resources. Furthermore, existing GC approaches in NVM OLTP engines are inefficient because they are based on methods designed for dynamic random access memory (DRAM) OLTP engines, without considering the significant differences in read/write bandwidth and cache line size between NVM and DRAM. These approaches either involve excessive random NVM access (traversing tuple versions) or lead to too many additional NVM write operations, both of which degrade the performance and durability of NVM. In this paper, we propose TB-Collect, a high-performance GC approach specifically designed for NVM OLTP engines. On the one hand, TB-Collect separates tuple headers and contents, storing data in an append-only manner, which greatly reduces NVM writes. On the other hand, TB-Collect performs GC at the block level, eliminating the need to traverse tuple versions and improving the utilization of reclaimed space. We have implemented TB-Collect on DBx1000 and MySQL. Experimental results show that TB-Collect achieves 1.15 to 1.58 times the throughput of existing methods when running TPCC and YCSB workloads. Full article

Modern computer applications have become highly data-intensive, giving rise to an increase in data traffic between the processor and memory units. Computing-in-Memory (CiM) has shown great promise as a solution to this aptly named von Neumann bottleneck problem by enabling computation within the memory unit and thus reducing data traffic. Many simulation tools in the literature have been proposed to enable the design space exploration (DSE) of these novel computer architectures as researchers are in need of these tools to test their designs prior to fabrication. This paper presents a collection of classical nonvolatile memory (NVM) and CiM simulation tools to showcase their capabilities, as presented in their respective analyses. We provide an in-depth overview of DSE, emerging NVM device technologies, and popular CiM architectures. We organize the simulation tools by design-level scopes with respect to their focus on the devices, circuits, architectures, systems/algorithms, and applications they support. We conclude this work by identifying the gaps within the simulation space. Full article

With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and restrict the rapid development of CiM digital circuits. To address this problem, this paper proposes a Vin–Vout CiM unit circuit with the built-in state of FeFET as a bridge. The proposed unit circuit unifies the form of logic inputs and describes the basic structure of FeFET to realize logic functions under the application of gate-source voltage. Based on the proposed unit circuit, basic logic gates are designed and used to realize CiM Full Adder (FA). The simulation results verify the feasibility of FeFET as the core of logic operations and prove the scalability of FeFET-based unit circuit, which is expected to develop more efficient CiM circuits. Full article

Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) have not fully leveraged hardware characteristics, resulting in an imbalance between throughput and recovery performance. In this paper, we conclude with the reason why existing designs fail to achieve both: placing indexes on NVM results in numerous random writes and write amplification for index updates, leading to a decrease in system performance. Placing indexes on dynamic random access memory (DRAM) results in much time consumption for rebuilding indexes during recovery. To address this issue, we propose FIR, an NVM OLTP Engine with the fast rebuilding of the DRAM indexes, achieving instant system recovery while maintaining high throughput. Firstly, we design an index checkpoint strategy. During recovery, the indexes are quickly rebuilt by the bottom-up algorithm with index checkpoints. Then, to achieve instant recovery of the entire engine after rebuilding indexes, we optimize the existing log-free design by leveraging time-ordered storage, which significantly reduces the number of NVM writes. We also implement garbage collection based on data redistribution, enhancing system availability. The experimental results demonstrate that FIR achieves 98% of the performance of state-of-the-art OLTP Engine when running TPCC and YCSB. And the recovery speed of FIR is 43.6×–54.5× faster, achieving near-instantaneous recovery. Full article

The rapid advancement of artificial intelligence (AI) technology, combined with the widespread proliferation of Internet of Things (IoT) devices, has significantly expanded the scope of AI applications, from data centers to edge devices. Running AI applications on edge devices requires a careful balance between data processing performance and energy efficiency. This challenge becomes even more critical when the computational load of applications dynamically changes over time, making it difficult to maintain optimal performance and energy efficiency simultaneously. To address these challenges, we propose a novel processing-in-memory (PIM) technology that dynamically optimizes performance and power consumption in response to real-time workload variations in AI applications. Our proposed solution consists of a new PIM architecture and an operational algorithm designed to maximize its effectiveness. The PIM architecture follows a well-established structure known for effectively handling data-centric tasks in AI applications. However, unlike conventional designs, it features a heterogeneous configuration of high-performance PIM (HP-PIM) modules and low-power PIM (LP-PIM) modules. This enables the system to dynamically adjust data processing based on varying computational load, optimizing energy efficiency according to the application’s workload demands. In addition, we present a data placement optimization algorithm to fully leverage the potential of the heterogeneous PIM architecture. This algorithm predicts changes in application workloads and optimally allocates data to the HP-PIM and LP-PIM modules, improving energy efficiency. To validate and evaluate the proposed technology, we implemented the PIM architecture and developed an embedded processor that integrates this architecture. We performed FPGA prototyping of the processor, and functional verification was successfully completed. Experimental results from running applications with varying workload demands on the prototype PIM processor demonstrate that the proposed technology achieves up to 29.54% energy savings. Full article

Quality of service (QoS) has evolved to ensure performance across various computing environments, focusing on data bandwidth, response time, throughput, and stability. Traditional QoS schemes primarily target DRAM-based homogeneous memory systems, exposing limitations when applied to diverse memory configurations. Moreover, the emergence of nonvolatile memories (NVMs) has made achieving QoS even more challenging due to their differing characteristics. While QoS schemes have been proposed for DRAM-based memory systems or hybrid memory systems combining DRAM and a single NVM type, there is a lack of research on QoS techniques for memory systems that incorporate multiple types of NVM simultaneously. Ensuring QoS in these heterogeneous memory environments is challenging due to significant differences in memory characteristics. In this paper, we propose a novel technique, dynamic affinity-based resource pairing (DARP), designed to enhance QoS in multicore heterogeneous memory systems. The proposed approach dynamically monitors the memory access patterns of applications and leverages the specific read/write characteristics of NVM devices. Detailed information from monitoring is used to optimally allocate memory data to the most suitable memory devices, ensuring stable memory response times and mitigating bottlenecks. Extensive experiments validate the efficiency and scalability of DARP across various workloads and heterogeneous memory configurations, including memory systems with multiple types of NVM. The results show that our technique significantly outperforms state-of-the-art QoS methods in terms of memory response time consistency and overall QoS in heterogeneous memory environments. DARP achieved a memory response time variability of 74.4% in six different memory configurations compared to the baseline on average, demonstrating its high scalability and effectiveness in enhancing QoS across various heterogeneous memory systems. Full article

The rapid advancement of technology, alongside state-of-the-art techniques is at an all-time high. However, this unprecedented growth of technological prowess also brings forth potential threats, as oftentimes the security encompassing these technologies is imperfect. Particularly within the automobile industry, the recent strides in technology have brought about increased complexity. A notable flaw lies in the CAN-FD protocol, which lacks robust security measures, making it vulnerable to data theft, injection, replay, and flood data attacks. With the rising complexity of in-vehicular networks and the widespread adoption of CAN-FD, the imperative to safeguard the protocol has never been more crucial. This paper aims to provide a comprehensive review of the existing in-vehicle communication protocol, CAN-FD. It explores existing security approaches designed to fortify CAN-FD, demonstrating multiple multi-layer solutions that leverage modern techniques including Physical Unclonable Function (PUF), Elliptical Curve Cryptography (ECC), Ethereum Blockchain, and Smart contracts. The paper highlights existing multi-layer security measures that offer minimal overhead, optimal performance, and robust security. Moreover, it identifies areas where these security measures fall short and discusses ongoing research along with suggestions for implementing software and hardware-level modifications. These proposed changes aim to streamline complexity, reduce overhead while ensuring forward compatibility. In essence, the methods outlined in this study are poised to excel in real-world applications, offering robust protection for the evolving landscape of in-vehicular communication systems. Full article

In the era of widespread edge computing, energy conservation modes like complete power shutdown are crucial for battery-powered devices, but they risk data loss in volatile memory. Energy autonomous systems, relying on ambient energy, face operational challenges due to power losses. Recent advancements in emerging nonvolatile memories (NVMs) like FRAM, RRAM, MRAM, and PCM offer mature solutions to sustain work progress with minimal energy overhead during outages. This paper thoroughly reviews utilizing emerging NVMs in microcontroller units (MCUs), comparing their key attributes to describe unique benefits and potential applications. Furthermore, we discuss the intricate details of NVM circuit design and NVM-driven compute-in-memory (CIM) architectures. In summary, integrating emerging NVMs into MCUs showcases promising prospects for next-generation applications such as Internet of Things and neural networks. Full article

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and −18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (T_ILD) decreases from 100 to 10 nm, the change in the V_TH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin T_ILD of 50 nm or less need to be designed considering electrical coupling. Full article

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO₂/Al₂O₃-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO₂ is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO₂/Al₂O₃-based stacks. Full article

This study compares the performance of two types of capacitive devices, indium tin oxide-aluminum oxide-zirconia aluminum oxide-silicon oxide-silicon (IAZAOS) and indium tin oxide-aluminum oxide-hafnium aluminum oxide-silicon oxide-silicon (IAHAOS), as silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory (NVM) total dose of ultraviolet radiation (UV TD) sensors. Results show that IAZAOS with zirconia aluminum oxide as the charge-trapping layer outperforms IAHAOS with hafnium aluminum oxide for a UV TD sensor. After exposure to UV TD irradiation of 100 mW·s/cm², the threshold voltage (V_T) change of IAZAOS is almost 1.25 times that of IAHAOS. The study also found that annealing can significantly improve the response performance of IAZAOS UV TD sensors. Furthermore, IAZAOS devices with partially smaller nanocrystals in the charge-trapping layer greatly enhance the response of SONOS-type UV TD sensors. The study also compared the constant voltage stress-induced leakage current (CVSILC) and found that the CVSILC for annealed IAZAOS devices is 1000 times smaller than that of IAHAOS devices. Moreover, the IAZAOS-I2Z2 exhibits a superior performance regarding irradiation/refresh cycle endurance as compared to the IAHAOS-I2H1 device. These findings suggest that IAZAOS capacitive devices have superior performance and potential for use in SONOS-type UV TD sensors. Full article

In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. In this paper, we propose a fully digital non-volatile CIM (DNV-CIM) macro with compressed coding look-up table (LUT) multiplier (CCLUTM) using the 40 nm technology, which is highly compatible with the standard commodity NOR Flash memory. We also provide a continuous accumulation scheme for machine learning applications. When applied to a modified ResNet18 network trained under the CIFAR-10 dataset, the simulations indicate that the proposed CCLUTM-based DNV-CIM can achieve a peak energy efficiency of 75.18 TOPS/W with 4-bit multiplication and accumulation (MAC) operations. Full article

HfO₂-based resistive random-access memory (RRAM) with a Ti buffer layer has been extensively studied as an emerging nonvolatile memory (eNVM) candidate because of its excellent resistive switching (RS) properties and CMOS process compatibility. However, a detailed understanding of the nature of Ti thickness-dependent RS and systematic thermal degradation research about the effect of post-metallization annealing (PMA) time on oxygen vacancy distribution and RS performance still needs to be included. Herein, the impact of Ti buffer layer thickness on the RS performance of the Al/Ti/HfO₂/TiN devices is first addressed. Consequently, we have proposed a simple strategy to regulate the leakage current, forming voltage, memory window, and uniformity by varying the thickness of the Ti layer. Moreover, it is found that the device with 15 nm Ti shows the minimum cycle-to-cycle variability (CCV) and device-to-device variability (DDV), good retention (10⁵ s at 85 °C), and superior endurance (10⁴). In addition, thermal degradation of the Al/Ti(15 nm)/HfO₂/TiN devices under different PMA times at 400 °C is carried out. It is found that the leakage current increases and the forming voltage and memory window decrease with the increase in PMA time due to the thermally activated oxidation of the Ti. However, when the PMA time increases to 30 min, the Ti can no longer capture oxygen from HfO₂ due to the formation of self-limited TiO_x. Therefore, the device shows superior thermal stability with a PMA time of 90 min at 400 °C and no degradation of the memory window, uniformity, endurance, or retention. This work demonstrates that the Ti/HfO₂-based RRAM shows superior back-end-of-line compatibility with high thermal stability up to 400 °C for over an hour. Full article

The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash memory systems, the large voltage required to erase the charge of nonvolatile memory cells, and the limitations of scaled-down systems. Ferroelectric materials are one exciting means of breaking away from this structure, as Hf-based ferroelectric materials have a low operating voltage, excellent data retention qualities, and show fast switching speed, and can be used as non-volatile memory (NVM) if polarization characteristics are utilized. Moreover, adjusting their conductance enables diverse computing architectures, such as neuromorphic computing with analog characteristics or ‘logic-in-memory’ computing with digital characteristics, through high integration. Several types of ferroelectric memories, including two-terminal-based FTJs, three-terminal-based FeFETs using electric field effect, and FeRAMs using ferroelectric materials as capacitors, are currently being studied. In this review paper, we include these devices, as well as a Fe-diode with high on/off ratio properties, which has a similar structure to the FTJs but operate with the Schottky barrier modulation. After reviewing the operating principles and features of each structure, we conclude with a summary of recent applications that have incorporated them. Full article

BN-based resistive random-access memory (RRAM) has emerged as a potential candidate for non-volatile memory (NVM) in aerospace applications, offering high thermal conductivity, excellent mechanical, and chemical stability, low power consumption, high density, and reliability. However, the presence of defects and trap states in BN-based RRAM can limit its performance and reliability in aerospace applications. As a result, higher set voltages of 1.4 and 1.23 V were obtained for non-annealed and nitrogen-annealed BN-based RRAM, respectively, but lower set voltages of 1.06 V were obtained for hydrogen-annealed BN-based RRAM. In addition, the hydrogen-annealed BN-based RRAM showed an on/off ratio of 100, which is 10 times higher than the non-annealed BN-based RRAM. We observed that the LRS changed to the HRS state before 10,000 s for both the non-annealed and nitrogen-annealed BN-based RRAMs. In contrast, the hydrogen-annealed BN-based RRAM showed excellent retention characteristics, with data retained up to 10,000 s. Full article