Search Results (49)

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage. Full article

This paper presents a 17–38 GHz wideband low-noise amplifier (LNA) designed in a 150-nm GaAs pHEMT process. The proposed amplifier adopts a cascode topology with an interstage inductor between the common-source (CS) and common-gate (CG) stages, and a series inductor at the source node of the CS stage for source degeneration. By incorporating these inductors in the amplification stage, simultaneous noise and input matching is facilitated, while achieving flat gain characteristics over a broad frequency range and ensuring stability. In addition, the amplification stage with inductors achieves input matching using only a shunt component in the DC bias path, without any series matching elements. This approach allows the amplifier to achieve simultaneous noise and input matching (SNIM), ensuring low-noise performance over a wide bandwidth. The simulation results show a flat gain of 20–23 dB and a low noise figure of 1.1–2.1 dB over the 17–38 GHz band. Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

The explosive demand for high-performance secondary power sources in artificial intelligence (AI) has brought significant opportunities for low-voltage GaN devices. This paper focuses on research on high-efficiency and high-reliability low-voltage p-GaN gate HEMTs with a gate–drain distance, L_GD, of 1 to 3 μm in our pilot line, manufactured on 6-inch Si using a CMOS-compatible process, with extraordinary wafer-level uniformity. Specifically, these fabricated p-GaN gate HEMTs with an L_GD of 1.5 μm demonstrate a blocking voltage of over 180 V and a high V_TH of 1.6 V and exhibit a low R_ON of 2.8 Ω·mm. It is found that device structure optimization can significantly enhance device reliability. That is, through the dedicated optimization of source field plate structure and interlayer dielectric (ILD) thickness, the dynamic ON-resistance, R_ON, degradation of devices with an L_GD of 1.5 µm was successfully suppressed from 60% to 20%, and the V_TH shift was significantly reduced from 1.1 to 0.5 V. Further, the devices also passed preliminary gate bias stress and high-voltage OFF-state stress tests, providing guidance for preparing high-performance, low-voltage p-GaN gate HEMTs in the future. Full article

In this study, a single-pole double-throw (SPDT) switch for Sub-6 GHz application is designed. In particular, a shunt inductor is connected to the antenna port of the switch for ESD (electrostatic discharge) protection in RF (radio frequency) front end module. The shunt inductor not only serves as an ESD protection device, but also serves as a component of a parallel resonance circuit to suppress insertion loss of the switch. In addition, in order to secure the power handling capability, transistors turned off in the transmit (Tx) mode are implemented as quadruple-gate transistors. An SPDT switch is fabricated using GaAs pHEMT provided in the 500 nm GaAs BiFET process to verify the feasibility of the proposed switch structure. The operating frequency is set from 3 GHz to 5 GHz. The insertion loss and isolation measured in the Tx mode are lower than 0.35 dB and higher than 31.6 dB, respectively. The insertion loss and isolation measured in the Rx mode are lower than 0.32 dB and higher than 33.9 dB, respectively. The chip size including test pads is 0.890 × 0.875 mm². Full article

This study introduces an enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a self-aligned p-GaN gate structure, fabricated using a gate-first process. The key innovation of this work lies in simplifying the fabrication process by utilizing gate metallization for both electrical contact and etching mask functions, enabling precise self-alignment. A highly selective Cl₂/N₂/O₂ inductively coupled plasma (ICP) etching process was optimized to etch the p-GaN layer in the access regions, with a selectivity ratio of 33:1 and minimal damage to the AlGaN barrier. Additionally, a novel, non-annealed ohmic contact formation technique was developed, leveraging ICP etching to create nitrogen vacancies that facilitate contact formation without requiring thermal annealing. This technique streamlines the process by combining ohmic contact formation and mesa isolation into a single lithographic step. Incorporating a SiNx gate dielectric layer led to a 4.5 V threshold voltage shift in the fabricated devices. The resulting devices exhibited improved electrical performance, including a wide gate voltage swing (>10 V), a high on/off current ratio (~10⁷), and clear pinch-off characteristics. These results demonstrate the effectiveness of the proposed fabrication approach, offering significant improvements in process efficiency and manufacturability. Full article

A three-stage low-noise amplifier (LNA) operating over the 6–18 GHz frequency range is designed and implemented, featuring a flat noise figure (NF) and enhanced output 1 dB compression point (OP_1dB). To improve linearity and minimize distortion, a power high-electron-mobility transistor (HEMT) is employed in the final stage. Additionally, resistive feedback and self-biasing techniques are integrated to extend the amplifier’s bandwidth. The proposed LNA exhibits a high and flat power gain of 25 ± 1 dB, with an input return loss of more than 10 dB. The measured NF remains stable at 2.6 ± 0.3 dB over the 6–18 GHz range. Furthermore, the OP_1dB exceeds 19.5 dBm across the entire 3 dB gain bandwidth (BW). The circuit is fabricated using a 0.15 μm GaAs pHEMT process, occupying a compact chip area of 1.2 × 1.8 mm². Full article

This paper presents two cryogenic low-noise amplifiers (LNAs) based on the WIN’s 0.18 $\mathrm{\mu }$m gate length gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process designed for radio telescope receivers. Discrete transistors with gate peripheries spanning 50–600 $\mathrm{\mu }$m were DC-characterized at 290 K and 15 K, respectively. The LNAs underwent on-chip noise characterization under 15 K using a Y-factor measurement setup, which integrated a calibrated noise source and a noise figure analyzer. This approach directly quantified the noise temperature—critical metrics for radio telescope receiver front-ends. The top-performing LNA variant identified through on-chip characterization was packaged and evaluated in a cryogenic test-bed. This LNA, spanning a bandwidth of 0.3–15 GHz, demonstrated a gain of 26 dB and a minimum noise temperature of 6 K when operated at an ambient temperature of 15 K. In contrast, a second LNA architecture, tested solely on-chip, demonstrated a gain of 30 dB and a minimum noise temperature of 15 K across the 0.3–7 GHz range. Full article

In this study, we present a comprehensive comparative analysis of the surge current capability in the third quadrant for four commercial 650 V p-GaN gate HEMTs. Temperature-dependent experiments reveal varying degrees of negative correlation between surge current capability and device junction temperature across the four devices. Gate leakage testing and the decapsulation of failed devices identified two distinct failure modes. Through failure analysis techniques and TCAD simulations, the characteristics of these failure modes were thoroughly revealed. For Failure Mode I, the combined impact of electrical and thermal stress during the surge current process leads to extensive damage in the upper interconnect metal layer. For Failure Mode II, degradation of the metal to p-GaN Schottky contact under a strong electric field causes a rapid increase in the gate current, and the high gate current, coupled with the strong electric field, results in severe electromigration of the gate metal. Among the four tested devices, those exhibiting higher surge energy are more prone to gate damage, making them more susceptible to Failure Mode II. Full article

This paper demonstrates that potential oscillations in various frequency bands of monolithic microwave integrated circuits (MMICs) can be effectively suppressed using well-designed dual RC traps in the bias networks. The proposed approach is applied to the design and development of a highly stable W-band low-noise amplifier (LNA) MMIC for high-precision millimeter-wave applications. The amplifier is fabricated using the 0.1 µm GaAs pHEMT process from Win Semiconductors. The cascaded four-stage design consists of two low-noise-optimized stages, followed by two high-gain-tuned stages. Stability is enhanced through the integration of dual RC traps in the bias networks, which is rigorously evaluated using stability factors (K and μ) and network determinant function (NDF) encirclement analysis. In low-noise mode, the developed low-noise amplifier MMIC achieves a noise figure of 5.6−6.2 dB and a linear gain of 17.8−19.8 dB over the 90−98 GHz frequency range, while only consuming a DC power of 96 mW. In high-gain mode, it has a noise figure of 6.2−6.9 dB and a linear gain of 19.8−21.7 dB. Full article

This work reports the concept of a shunt negative feedback technique for implementing a millimeter-wave wideband low-noise amplifier. The proposed shunt negative feedback network consists of a resistor–capacitor–inductor configuration. The proposed feedback network can achieve simultaneous noise and input matching (SNIM) over a wide frequency range by adjusting the values of the resistor–capacitor–inductor configuration based on numerical analysis. By adopting the SNIM-based gain core as the first stage of the amplifier, the simulation results of the three-stage low-noise amplifier in a 150-nm GaAs pHEMT process achieve a gain of 15.6–18.6 dB and a noise figure of 1.05–2.8 dB in the frequency range of 13–33 GHz, respectively, while dissipating 99 mW. Full article

This paper presents a W-band power amplifier monolithic microwave integrated circuit (MMIC) that is designed for high-precision millimeter-wave systems and fabricated using a 0.1 µm GaAs pHEMT process. The amplifier’s stability was evaluated using the network determinant function, ensuring robust performance under both linear and nonlinear conditions. Simultaneous matching for gain and output power was achieved with minimal passive elements. The developed power amplifier MMIC exhibits a linear gain exceeding 20 dB and an input return loss greater than 6 dB across the 88–98 GHz range. It delivers an output power of 23.8–24.1 dBm with a power gain of 17.3–17.9 dB in the 88–97 GHz range and achieves a maximum power-added efficiency (PAE) of 24% at 94 GHz. Full article

In this study, we propose a simple measurement technique to quantitatively measure the time taken by threshold voltage of normally-off p-GaN AlGaN/GaN HEMTs to recover from a nominal operational gate stress-induced instability. The proposed technique eliminates the requirement to perform a full transfer characteristic sweep post-stress, thereby eliminating the measurement-induced instability effect, often colluding precise recovery time measurement. The rate of recovery and extracted recovery times hold significance in empirically correlating the location of traps in the p-GaN or AlGaN barrier region causing V_TH instability. The gate of the HEMT is stressed at nominal operational drive voltages 1.5 V, 2 V, and 4 V for various time intervals from 500 μs to 100 s, and the time taken for the drain current to recover to prestress levels measured at near-threshold voltage (~1.1 V_TH) is measured as the threshold voltage recovery time. With increasing gate stress voltages, 2DEG gets trapped at relatively deeper trap energy levels at the AlGaN/GaN interface requiring more emission time during the process of recovery, mandating larger recovery times. At higher stress voltage of 4 V, the Schottky gate leakage current is high enough enabling injected holes to cross the AlGaN barrier and counter-compensate for the deeply trapped 2DEG, requiring relatively the same recovery times as lower stress voltages where the gate leakage is negligibly small. With increasing stress time, the amount of 2DEG trapped increases, requiring more recovery time to de-trap and beyond a certain time, saturation of the trap density occurs causing the recovery time to plateau. Full article

This paper presents an ultra-wideband, low insertion loss, and high accuracy 6-bit digital step attenuator (DSA). To improve the accuracy of amplitude and phase shift of the attenuator, two innovative compensation structures are proposed in this paper: a series inductive compensation structure (SICS) designed to compensate for high frequency attenuation values and a small bit compensation structure (SBCS) intended for large attenuation bits. Additionally, we propose insertion loss reduction techniques (ILRTs) to reduce insertion loss. The fabricated 6-bit DSA core area is only 0.51 mm², and it exhibits an attenuation range of 31.5 dB in 0.5 dB steps. Measurements reveal that the root-mean-square (RMS) attenuation and phase errors for the 64 attenuation states are within 0.18 dB and 7°, respectively. The insertion loss is better than 2.54 dB; the return loss is better than −17 dB; and the input 1 dB compression point (IP1 dB) is 29 dBm at IF 12 GHz. To the best of our knowledge, this chip presents the highest attenuation accuracy, the lowest insertion loss, the best IP1dB, and a good matching performance in the range of 2–22 GHz using the 0.25 μm GaAs p-HEMT process. Full article

A 28 GHz digitally controlled 6-bit phase shifter with a precision calibration technique in GaN high-electron mobility transistor (HEMT) technology is presented for Ka-band phased-array systems and applications. It comprises six stages, in which stages 1 and 2 for 5.625° and 11.25° are designed in the form of a switched-line circuit, and stages 3, 4, and 5 for 22.5°, 45°, and 90° are designed in the form of a switched-filter circuit. The final stage 6 for 180° is designed in a single-to-differential balun followed by a single-pole double-throw (SPDT) switch for achieving an efficient phase inversion. A novel continuous tuning calibration technique is proposed to improve the phase accuracy. It controls the gate bias voltage of off-state HEMTs at the stage 6 SPDT switch for fine calibration of the output phase. Fabricated in a 0.15 μm GaN HEMT process using a die size of 1.75 mm², the circuit produces 64 phase states at 28 GHz with a 5.625° step. The experimental results show that the Root-Mean-Square (RMS) phase error is significantly improved from 8.56° before calibration to 1.08° after calibration. It is also found that the calibration does not induce significant changes for other performances such as the insertion loss, RMS amplitude error, and input-referred P_1dB. This work successfully demonstrates that the GaN technology can be applied to millimeter-wave high-power phased-array transceiver systems. Full article