Search Results (76)

With the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alternative to conventional DRAM and SDRAM, offering advantages such as faster access speeds, reduced power consumption, and enhanced endurance. However, MRAM is subject to challenges including process variations and thermal fluctuations, which can induce random bit errors and result in imbalanced probabilities of 0 and 1 bits. To address these issues, we propose a novel sparse coding scheme characterized by a minimum Hamming distance of three. During the encoding process, three check bits are appended to the user data and processed using a generator matrix. If the resulting codeword fails to satisfy the sparsity constraint, it is inverted to comply with the coding requirement. This method is based on the error characteristics inherent in MRAM to facilitate effective error correction. Furthermore, we introduce a dynamic threshold detection technique that updates bit probability estimates in real time during data transmission. Simulation results demonstrate substantial improvements in both error resilience and decoding accuracy, particularly as MRAM density increases. Full article

Dynamic random-access memory (DRAM) is a vital component in modern computing systems. Enhancing memory performance requires maximizing capacitor capacitance within DRAM cells, which is achieved using high-k dielectric materials deposited as thin, uniform films via atomic layer deposition (ALD). Precise film deposition that minimizes electronic defects caused by charged vacancies is essential for reducing leakage current and ensuring high dielectric strength. In this study, we fabricated metal–insulator–metal (MIM) capacitors in high-aspect-ratio trench structures using remote plasma ALD (RP-ALD) and direct plasma ALD (DP-ALD). The trenches, etched into silicon, featured a 7:1 aspect ratio, 76 nm pitch, and 38 nm critical dimension. We evaluated the electrical characteristics of HfO₂-based capacitors with TiN top and bottom electrodes, focusing on leakage current density and equivalent oxide thickness. Capacitance–voltage analysis and X-ray photoelectron spectroscopy (XPS) revealed that RP-ALD effectively suppressed plasma-induced damage, reducing defect density and leakage current. While DP-ALD offered excellent film properties, it suffered from degraded lateral uniformity due to direct plasma exposure. Given its superior lateral uniformity, lower leakage, and defect suppression, RP-ALD shows strong potential for improving DRAM capacitor performance and serves as a promising alternative to the currently adopted thermal ALD process. Full article

In mobile dynamic random access memory (DRAM) receivers, the data strobe complement (DQS_c) and data strobe true (DQS_t) signals must be maintained at high and low voltage levels in the write data strobe off (WDQS_OFF) mode. Therefore, we developed a voltage regulation circuit to optimize the differential voltage signals of DQS_c and DQS_t, ensuring a high voltage level above 0.9 V and a low voltage level below 0.3 V. Experimental results showed that the circuit stably maintained DQS_c above 0.9 V and DQS_t below 0.3 V before the write preamble time (tWPRE) and in WDQS_OFF mode. This configuration effectively prevents unintended activation in the mobile DRAM DQS input receiver. Full article

Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) almost all use Multi-Version Concurrency Control (MVCC) protocol to ensure data consistency. MVCC allows multiple transactions to execute concurrently without lock conflicts, reducing the wait time between read and write operations, and thereby significantly increasing the throughput of NVM OLTP engines. However, it requires garbage collection (GC) to clean up the obsolete tuple versions to prevent storage overflow, which consumes additional system resources. Furthermore, existing GC approaches in NVM OLTP engines are inefficient because they are based on methods designed for dynamic random access memory (DRAM) OLTP engines, without considering the significant differences in read/write bandwidth and cache line size between NVM and DRAM. These approaches either involve excessive random NVM access (traversing tuple versions) or lead to too many additional NVM write operations, both of which degrade the performance and durability of NVM. In this paper, we propose TB-Collect, a high-performance GC approach specifically designed for NVM OLTP engines. On the one hand, TB-Collect separates tuple headers and contents, storing data in an append-only manner, which greatly reduces NVM writes. On the other hand, TB-Collect performs GC at the block level, eliminating the need to traverse tuple versions and improving the utilization of reclaimed space. We have implemented TB-Collect on DBx1000 and MySQL. Experimental results show that TB-Collect achieves 1.15 to 1.58 times the throughput of existing methods when running TPCC and YCSB workloads. Full article

As data centers expand, immersion cooling systems are gaining attention for thermal management of memory devices. To enable widespread adoption, it is essential to evaluate the impact of coolants on the reliability of memory packages. In this study, high-voltage direct current (DC) stress tests were conducted on commercial dynamic random access memory (DRAM) packages in both single-phase coolant and air environments to analyze heat generation and electrical characteristics. A DC voltage ranging from 2.5 to 3.1 V, which is higher than the regular operating voltage of 1.2 V, was applied. Temperature changes were measured using an infrared camera in the air, and a contact-based thermometer in the coolant. The leakage current was also evaluated through I-V curve analysis. Heat generation and changes in leakage currents were not significant in either environment until the applied voltage stress exceeded approximately twice the standard voltage (2.5–2.8 V). However, the package’s degradation accelerated when the applied voltages exceeded 3.0 V, demonstrating a nonlinear increase in temperature and leakage current. Full article

Information-Centric Networking (ICN) typically utilizes DRAM (Dynamic Random Access Memory) to build in-network cache components due to its high data transfer rate and low latency. However, DRAM faces significant limitations in terms of cost and capacity, making it challenging to meet the growing demands for cache scalability required by increasing Internet traffic. Combining high-speed but expensive memory (e.g., DRAM) with large-capacity, low-cost storage (e.g., SSD) to construct a hierarchical cache architecture has emerged as an effective solution to this problem. However, how to perform efficient cache management in such architectures to realize the expected cache performance remains challenging. This paper proposes a cache management scheme for hierarchical cache architectures in ICN, which introduces a differentiated replica replacement policy to accommodate the varying request access patterns at different cache layers, thereby enhancing overall cache performance. Additionally, a probabilistic insertion-based SSD cache admission filtering mechanism is designed to control the SSD write load, addressing the issue of balancing SSD lifespan and space utilization. Extensive simulation results demonstrate that the proposed scheme exhibits superior cache performance and lower SSD write load under various workloads and replica placement strategies, highlighting its broad applicability to different application scenarios. Additionally, it maintains stable performance improvements across different cache capacity settings, further reflecting its good scalability. Full article

Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) have not fully leveraged hardware characteristics, resulting in an imbalance between throughput and recovery performance. In this paper, we conclude with the reason why existing designs fail to achieve both: placing indexes on NVM results in numerous random writes and write amplification for index updates, leading to a decrease in system performance. Placing indexes on dynamic random access memory (DRAM) results in much time consumption for rebuilding indexes during recovery. To address this issue, we propose FIR, an NVM OLTP Engine with the fast rebuilding of the DRAM indexes, achieving instant system recovery while maintaining high throughput. Firstly, we design an index checkpoint strategy. During recovery, the indexes are quickly rebuilt by the bottom-up algorithm with index checkpoints. Then, to achieve instant recovery of the entire engine after rebuilding indexes, we optimize the existing log-free design by leveraging time-ordered storage, which significantly reduces the number of NVM writes. We also implement garbage collection based on data redistribution, enhancing system availability. The experimental results demonstrate that FIR achieves 98% of the performance of state-of-the-art OLTP Engine when running TPCC and YCSB. And the recovery speed of FIR is 43.6×–54.5× faster, achieving near-instantaneous recovery. Full article

Dynamic random-access memory (DRAM) is crucial for high-performance computing due to its speed and storage capacity. As the demand for high-capacity memory increases, DRAM has adopted a scaled-down approach for the next generation. However, the reduced distance between cells leads to electrical interference, known as the 1-row Hammer effect, which degrades DRAM performance and poses security risks. Therefore, the 1-row Hammer effect is a critical issue in current DRAM technology. In this study, we investigate the principles and impact of the 1-row Hammer phenomenon on DRAM. The 1-row Hammer effect can cause two types of failures: D0 and D1. We focus on D0 failures, which occur when stored data transition from 0 to 1 due to repeated accesses. This phenomenon involves the capture and diffusion of electrons, influenced by interfacial traps and device structures. To investigate the D0 failure, we simulated the 1-row Hammer effect using a mixed-mode approach to examine its effects on interfacial traps and device structure changes. This study aims to improve our understanding of row Hammer and suggests a mitigation strategy using buried oxide. The proposed structure mitigates the D0 failure by approximately 25%, effectively improving the security and reliability of DRAM. Full article

As the scope of artificial intelligence (AI) expands and the structure becomes more complex, the amount of data for inference and training has increased. In traditional computer architectures, the memory bandwidth limitations have intensified bottlenecks in AI systems, and processing-in-memory (PIM) architectures have been proposed to overcome this issue. PIM is an architecture that performs computations within memory, thereby reducing data movement between the CPU and memory. However, since PIM is difficult to optimize as a general-purpose architecture, it is essential to adopt an architecture suitable for the target application. While various simulators and emulators have been introduced for the design space exploration (DSE) of different PIM architectures, simulators are limited in debugging hardware operations, and emulators face challenges in flexibly modifying the system configuration, as emulators implement the entire architecture in hardware. Therefore, this paper introduces PIMCoSim, a comprehensive hardware–software co-simulator for the DSE of DRAM-PIM systems. This co-simulator partially emulates simplified hardware-implemented processing elements (PEs) and integrates software models for memory operations, facilitating the DSE of PIM systems. To validate PIMCoSim, we analyzed results for different computational workloads by varying PIM structures and operational policies, demonstrating the efficiency of DRAM-PIM systems. The co-simulation approach in PIMCoSim aims to contribute to analyzing DRAM-PIM configurations and adopting optimized structures. Full article

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string. Full article

As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cycles, causing performance degradation. Specifically, in the 6F² DRAM structure, activating a word line (WL) lowers the energy barrier of adjacent WLs, leading to the Pass Gate Effect (PGE). This study investigates the use of buried oxide beneath the WL to mitigate the PGE through simulation. Using SILVACO TCAD, we analyzed the impact of varying the size and position of the buried oxide on the PGE. The results showed that increasing the oxide size or reducing the distance to the WL effectively reduced the PGE. However, the presence of interface traps, which increase with the addition of buried oxide, was found to exacerbate the PGE, indicating that minimizing interface traps is crucial when incorporating buried oxide. Full article

Dynamic random access memory (DRAM) serves as a critical component in medical equipment. Given the exacting standards demanded by medical equipment products, manufacturers face pressure to improve their product quality. The electrical characteristics of these products are based on the resistance value of the DRAM components. Hence, the purpose of this study is to optimize the resistance value of DRAM components in medical equipment. We proposed a novel FMEA-TSTM-NNGA framework that integrates failure mode and effect analysis (FMEA), the two-stage Taguchi method (TSTM), neural networks (NN), and genetic algorithms (GA) to optimize the manufacturing process. Moreover, the proposed FMEA-TSTM-NNGA framework achieved a substantial reduction in experimental trials, cutting the required number by a factor of 85.3 when compared to the grid search method. Our framework successfully identified optimal manufacturing condition settings for the resistance values of DRAM components: Depo time = 27 s, Depo O2 flow = 151 sccm, ARC-LTO etch time = 43 s, ARC-LTO etch pressure = 97 mTorr, Ox-SiCO etch time = 91 s, Ox-SiCO gas ratio = 22%, and Polish time = 84 s. The results helped the case company improve the resistance value of DRAM components from 191.1 × 10⁻³ Ohm to 176.84 × 10⁻³ Ohm, which is closer to the target value of 176.5 × 10⁻³ Ohm. The proposed FMEA-TSTM-NNGA framework is designed to operate efficiently on resource-constrained, facilitating real-time adjustments to production attributes. This capability enables DRAM manufacturers to swiftly optimize product quality. Full article

Many dynamic random-access memory (DRAM) manufacturing companies encounter significant resistance value deviations during the PVD sputtering process for manufacturing Ti thin films. These resistance values are influenced by the thickness of the thin films. Current mitigation strategies focus on adjusting film thickness to reduce resistance deviations, but this approach affects product structure profile and performance. Additionally, varying Ti thin film thicknesses across different product structures increase manufacturing complexity. This study aims to minimize resistance value deviations across multiple film thicknesses with minimal resource utilization. To achieve this goal, we propose the TSDTM-ANN-GA framework, which integrates the two-stage dynamic Taguchi method (TSDTM), artificial neural networks (ANN), and genetic algorithms (GA). The proposed framework requires significantly fewer experimental resources than traditional full factorial design and grid search method, making it suitable for resource-constrained and low-power computing environments. Our TSDTM-ANN-GA framework successfully identified an optimal production condition configuration for five different Ti thin film thicknesses: Degas temperature = 245 °C, Ar flow = 55 sccm, DC power = 5911 W, and DC power ramp rate = 4009 W/s. The results indicate that the deviation between the resistance values and their design values for the five Ti thin film thicknesses decreased by 86.8%, 94.1%, 95.9%, 98.2%, and 98.8%, respectively. The proposed method effectively reduced resistance deviations for the five Ti thin film thicknesses and simplified manufacturing management, allowing the required design values to be achieved under the same manufacturing conditions. This framework can efficiently operate on resource-limited and low-power computers, achieving the goal of real-time dynamic production parameter adjustments and enabling DRAM manufacturing companies to improve product quality promptly. Full article

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method. Full article

Using DNA as the next-generation medium for data storage offers unparalleled advantages in terms of data density, storage duration, and power consumption as compared to existing data storage technologies. To meet the high-speed data writing requirements in DNA data storage, this paper proposes a novel design for an ultra-high-density and high-throughput DNA synthesis platform. The presented design mainly leverages two functional modules: a dynamic random-access memory (DRAM)-like integrated circuit (IC) responsible for electrode addressing and voltage supply, and the static droplet array (SDA)-based microfluidic structure to eliminate any reaction species diffusion concern in electrochemical DNA synthesis. Through theoretical analysis and simulation studies, we validate the effective addressing of 10 million electrodes and stable, adjustable voltage supply by the integrated circuit. We also demonstrate a reaction unit size down to 3.16 × 3.16 μm², equivalent to 10 million/cm², that can rapidly and stably generate static droplets at each site, effectively constraining proton diffusion. Finally, we conducted a synthesis cycle experiment by incorporating fluorescent beacons on a microfabricated electrode array to examine the feasibility of our design. Full article