Search Results (2,103)

The deployment of object detection models on resource-constrained edge devices remains a substantial challenge, primarily because conventional static networks expend the same worst-case computational cost on every input, regardless of intrinsic difficulty. This paper proposes an input-adaptive dynamic neural network architecture for object detection in embedded environments. The present study investigates two orthogonal axes of input-adaptive inference for embedded object detection: The system demonstrates depth adaptivity through the implementation of Early Exit, and width adaptivity via group-wise Adaptive Routing. The proposed framework is constructed on a frozen Ultralytics YOLO26s backbone and incorporates two YOLO-style early-exit heads positioned at approximately 33% and 66% of the backbone depth. Furthermore, the framework incorporates two Straight-Through Gumbel-Softmax routers, which are appended after Layers 4 and 8 with group-wise hard gating. Both axes additionally accept an explicit external control signal that allows the host system to override the input-conditional policy at inference time. The dual-mode design facilitates the functionality of the trained checkpoint as either an input-adaptive policy, in which the depth and width are determined per sample from the input distribution, or an externally controlled policy. The experimental findings demonstrate two strongly asymmetric input-adaptive policies on a frozen YOLO26s backbone. The early-exit profile reduces the compute per sample from 12.739 to 10.532 GFLOPs—a 17.32% reduction according to our in-house Conv2d/Linear MAC-based GFLOPs estimator—while preserving baseline accuracy (mAP50 = 0.1545 vs. baseline = 0.1528; ΔmAP50 = +0.0017, within evaluation noise; mAP50–95 = −0.0033). Evaluating the router-only profile in the same validator pipeline with a sparsity penalty of γ = 0.05 results in a 12.3% decrease in logical GFLOPs (from 12.739 to 11.172), while maintaining an accuracy level that is at or above the PEFT baseline (mAP50 = 0.2324 and mAP50–95 = 0.1040). In our small-domain PEFT setup, training the dynamic-policy modules yields per-checkpoint mAP shifts in this magnitude. Therefore, we interpret the width-axis accuracy result as preservation of the baseline rather than an improvement. Our contribution on the width axis is reducing computing power while maintaining baseline accuracy. Importantly, the router profile’s logical GFLOP savings are not currently reflected in wall-clock latency under our dense-kernel PyTorch implementation. Achieving practical speedup requires sparse-kernel deployment, such as structured-sparse kernels, TensorRT, TVM, or Triton paths. We will address this in future deployment-level work. Our results indicate that the depth axis can yield genuine end-to-end speedup today, while the width axis offers deployment-pending compute reduction. Full article

Federated Learning (FL) enables privacy-preserving model training in edge and IoT environments. However, in adversarial settings, FL suffers from two key challenges: robustness degradation due to data heterogeneity and poisoning attacks, and runtime instability on resource-constrained devices. Existing work mainly focuses on robustness while overlooking system-level stability. To address this, we propose FedCASKD, a robustness- and stability-aware FL framework. It employs a score-based soft aggregation mechanism to suppress unreliable client updates without requiring a trusted dataset, and introduces a selection-aware bidirectional knowledge distillation protocol to mitigate model drift under Non-IID data. The novelty lies in integrating aggregation and distillation into a unified feedback framework that enhances robustness and stability. Experiments on AGNews and SogouNews show that FedCASKD outperforms baselines under label-flipping attacks and heterogeneous settings. Memory and Out-of-Memory (OOM) tests further demonstrate its superior runtime stability in edge environments. Full article

Fiber Bragg Grating (FBG) sensors are widely used for strain and temperature monitoring due to their high sensitivity, compact size, electromagnetic immunity, and multiplexing capability. While conventional FBG interrogators remain bulky and costly, Photonic Integrated Circuit (PIC) platforms provide a promising route toward compact, scalable, and low-power FBG interrogation. However, the choice of architecture strongly determines the achievable resolution, bandwidth, multiplexing capacity, and robustness. This review compares on-chip demodulation architectures, evaluating their performance in resolution, bandwidth, and interrogation speed. We show that the optimal architecture depends strongly on the application: AWG-based schemes excel in compact, multi-FBG readout; ring-resonator systems are highly effective for tunable filtering; and interferometric phase-domain schemes offer the highest sensitivity for dynamic strain sensing. Despite these architectural advances, practical deployment remains constrained by system-level bottlenecks. These challenges primarily include source/detector integration, fiber–chip coupling, packaging robustness, and thermal drift. Overcoming these barriers requires a shift in future development from isolated photonic-device optimization toward comprehensive, system-level co-design. Full article

Cardiac arrhythmias are a leading cause of cardiovascular mortality worldwide, necessitating accurate automated detection systems for continuous monitoring and clinical decision support. This study addresses the critical challenge of severe class imbalance in ECG beat classification, where normal beats comprise 82.8% of samples while life-threatening ventricular arrhythmias represent only 6.5%. We propose a lightweight one-dimensional convolutional neural network (1D-CNN) trained with a two-pronged class-balancing strategy: random oversampling of minority classes to 35% of the majority class size, combined with class-weighted cross-entropy loss. Recent work has achieved accuracies approaching 99–100% on the MIT-BIH database through increasingly complex architectures, including transfer learning, attention mechanisms, and multi-channel fusion. However, these approaches often require millions of parameters, limiting deployability on resource-constrained wearables. Despite the recent trend toward complexity, our simple four-block CNN with only 398,469 parameters achieves 99.18% overall test accuracy and a 96.38% macro-averaged F1-score on the MIT-BIH Arrhythmia Database—competitive with state-of-the-art methods while using 90–96% fewer parameters. Critically, the model attains 98.32% recall on ventricular beats, demonstrating high sensitivity for detecting life-threatening arrhythmias. Ablation studies confirm that both oversampling and weighted loss are essential: removing either component causes catastrophic performance degradation. Our results challenge the assumption that architectural complexity is necessary for ECG classification and demonstrate that proper class imbalance handling enables simple models to achieve state-of-the-art performances with superior computational efficiency suitable for deployment in wearable cardiac monitoring devices. Full article

To improve operational safety in confined spaces, this study proposes an intelligent safety monitoring framework that utilizes multimodal data from wearable devices. The framework comprises two core components: a human activity recognition (HAR) module and a bio-inspired adaptive multimodal decision fusion (BA-MDF) module. The HAR module processes accelerometer and gyroscope data through an enhanced FFT–LSTM architecture that integrates time- and frequency-domain features for real-time activity classification. The BA-MDF module, inspired by biological multisensory integration mechanisms—particularly the inverse effectiveness principle observed in the superior colliculus—evaluates contextual risk by adaptively fusing HAR outputs, heart rate variability, and geospatial constraints without additional computational overhead. Experimental testing demonstrated 92.4% overall HAR accuracy and 94.3% identification accuracy for emergency scenarios under a simulated sensor degradation environment. These results validate the framework’s effectiveness in mitigating risks from anomalous events in visually constrained environments. Full article

Quantization reduces the precision of neural network parameters to accelerate inference and lower power consumption, but it often causes noticeable accuracy degradation. We propose a differentiable quantization framework that replaces the non-differentiable rounding operation with a continuous surrogate function. During QAT, gradients are backpropagated through the proposed surrogate rather than being estimated by the STE, enabling gradient-based optimization of model weights, quantization parameters, and layer-wise bit-width configurations. Experiments on CIFAR-10 show that our method achieves higher accuracy than several representative quantization approximation methods under different bit-width settings. On embedded platforms, it improves post-quantization accuracy by up to 3.66 percentage points over industrial quantization frameworks such as TensorRT and Huawei AMCT on detection and segmentation tasks, and outperforms representative bit-width allocation methods by up to 7.49 percentage points. These results demonstrate the effectiveness of the proposed method for improving the accuracy of quantized neural networks on resource-constrained devices. Full article

Real-time binaural beat synthesis in dynamic acoustic environments is challenged by carrier non-stationarity, interaural phase discontinuities, and processing delay in conventional digital signal processing pipelines. This study proposes a predictive dual-stage neural framework for phase-coherent auditory synthesis under non-stationary acoustic conditions. The framework decouples real-time carrier estimation from phase-coherent signal generation through two specialized modules. An intelligent acoustic sensing module (AI-1) estimates time-varying carrier information across harmonic, fluctuating, and broadband acoustic profiles using a causal neural front-end with an adaptive confidence-driven strategy. A predictive phase-coherent generator (AI-2) then forecasts short-horizon carrier trajectories and drives a discrete-time phase accumulator to maintain continuous phase evolution during binaural beat embedding. Objective evaluation under multiple acoustic profiles and noise conditions shows that the proposed framework maintains strong phase continuity, with a Phase Coherence Factor greater than 0.91, and low artifact levels, with a Signal-to-Artifact Ratio greater than 39.8 dB, under the evaluated conditions. Additional comparisons with conventional DSP baselines, stronger classical F0 estimators, a lightweight neural F0 tracker, and component-wise ablation variants further demonstrate that the performance improvement arises from the combination of adaptive carrier estimation and predictive phase-coherent actuation, rather than from carrier estimation alone. Hardware profiling shows a combined INT8 inference time of 2.4 ms per frame on a resource-constrained Raspberry Pi Zero 2W-class edge device. Importantly, this inference time and the sub-millisecond phase-accumulator resolution should not be interpreted as sub-millisecond end-to-end physical audio latency. The complete system still includes buffering, framing, neural inference, and output processing delay; the proposed method instead reduces effective phase-boundary misalignment through short-horizon predictive compensation. These results support the proposed framework as a lightweight engineering solution for real-time phase-continuous auditory synthesis in dynamic listening environments. The reported PCF and SAR values should be interpreted as signal-level indicators of phase continuity and artifact suppression, rather than as evidence of listener comfort, perceptual preference, or neurophysiological efficacy. Full article

Accurate estimation of internal battery temperature is critical for the safety and state-of-health assessment of lithium-ion batteries, yet it remains challenging due to the trade-off between model accuracy and computational feasibility on resource-constrained edge hardware. This work targets stationary large-scale battery energy storage stations (BESS), where ambient temperatures are actively regulated within a narrow range (typically 15–35 °C), and is developed and validated on large-format prismatic LFP cells. We propose ThermaPhysLite, a lightweight physics-informed neural network (PINN) framework with three innovations: (i) a lightweight PINN architecture tailored for edge devices; (ii) integration of a simplified electro–thermal model—a lumped-parameter thermal circuit coupled with the Bernardi heat generation equation—into a multi-scale temporal convolutional network (MS-TCN) through the PINN paradigm; and (iii) real-time online deployment on the ESP32-S3 embedded platform. Ground-truth internal temperatures were obtained via side-drilled thermocouple embedding in disassembled cells. Offline validation under three operating conditions demonstrates RMSE values of 0.15–0.20 °C. Following INT8 quantization (compressed to 84.29 KB), online deployment yields RMSE values of 0.17–0.24 °C with single-cell inference latency of 120 ms, demonstrating practical viability for BMS in large-scale energy storage systems. Full article

Silicon micromachining serves as the foundational enabling technology for high-precision MEMS inertial sensors. However, the relentless pursuit of enhanced sensitivity and multi-functionality in emerging applications encounters a fundamental bottleneck when confined to two-dimensional scaling. The evolution toward complex three-dimensional (3D) stacking architectures is an inevitable trajectory for devices including MEMS inertial sensors, yet performance is constrained by the limitations of conventional processes in fabricating and integrating intricate 3D hollow structures. Specifically, uniformity in large-area deep silicon etching, structural integrity of convex corners in wet etching, and residual stress induced by multi-layer wafer bonding have emerged as critical, shared challenges. To address these issues, this paper proposes a triple-layer wafer-level stacking scheme that synergistically combines wet/dry hybrid etching with low-temperature adhesive bonding. This stacking scheme incorporates an innovative linear compensation model for wet-etched convex corners, enabling high-precision fabrication of complex corner structures under deep etching conditions. Furthermore, a collaborative strategy involving temporary bonding and plasma flow-field optimization improves the uniformity and integrity of dry etching for large perforated structures. A low-temperature triple-layer wafer-level stacking process is developed, encompassing precise adhesive dispensing, optical alignment, and a stepped low-temperature curing profile, thereby achieving highly symmetric 3D integration with controlled adhesive distribution. The efficacy of this stacking scheme is validated through the fabrication of a symmetrically stacked triple-layer MOEMS accelerometer sensing element. Test results demonstrate a noise floor as low as 0.40 µg/√Hz and a bias instability of 1.81 µg over 10 min. Compared with a double-layer counterpart, improved performance is obtained. The wafer-level stacking scheme established in this work not only provides a viable pathway for pushing the manufacturing limits of high-precision inertial devices but also offers a generic methodology for tackling complex hollow structure formation and low-temperature integration, holding referential value for broader applications in high-precision 3D microsystems. Full article

Falls are a major contributor to morbidity and mortality among older adults, and timely fall detection can help reduce the severity of fall-related outcomes. Wearable inertial measurement unit (IMU) sensors offer a promising solution for fall detection; however, many existing approaches rely on multiple sensing locations and computationally intensive models, which can limit their practicality for resource-constrained wearable devices. This study proposes a knowledge distillation framework for efficient wrist-based fall detection using the publicly available University of Málaga fall detection dataset (UMAFall), a benchmark dataset for human activity recognition and fall detection. Although UMAFall was not collected from older adults, it provides a useful public benchmark for evaluating IMU-based fall detection methods. Knowledge distillation was implemented using a teacher–student framework, in which a high-capacity teacher model trained with IMU data from four body locations (waist, wrist, ankle, and chest) provided soft targets for guiding a compact wrist-only CNN student model. In a held-out test evaluation using Subjects 2 and 5, the teacher model achieved 97.6% accuracy and an F1 score of 96.7%, with approximately 1.3 million trainable parameters. The independently trained wrist-based CNN achieved 90.2% accuracy and an F1 score of 87.1%. After applying knowledge distillation, the student model improved to 95.1% accuracy and an F1 score of 93.3% while maintaining the same lightweight architecture. A supplementary leave-one-subject-out analysis showed slightly higher and more stable AUC for KD-CNN than the independently trained CNN (0.96 ± 0.03 vs. 0.94 ± 0.07). These findings suggest that knowledge distillation can improve wrist-only fall detection in this feasibility evaluation, but further validation using older adults and real-world smartwatch data is needed. Full article

Ischemic stroke remains a leading cause of global mortality and long-term neurological disability, where the “Time is Brain” paradigm dictates that rapid and accurate lesion assessment is fundamental for effective clinical intervention. While the nnU-Net v2 framework has established a new state of the art in medical image segmentation, its high computational demands and reliance on data-center-grade GPUs hinder its translation into real-time, point-of-care clinical workflows. This study presents a technical feasibility analysis of a Cloud-to-Edge optimization pipeline designed to transfer a 3D nnU-Net v2 model from a high-performance cloud environment to a resource-constrained embedded device. Experimental results showed that edge deployment was associated with a reduction in overlap-based segmentation metrics compared with the cloud reference, with Dice decreasing from approximately 0.78 to 0.67. However, TensorRT FP32 and FP16 inference produced nearly identical mean segmentation metrics, suggesting that reduced-precision inference did not introduce additional measurable degradation under the evaluated conditions. The optimized FP16 configuration achieved a processing time of 10.2 s per 3D volume, representing a 33% reduction compared with embedded FP32 inference, while operating within a low-power envelope of approximately 10–13 W. These findings support the preliminary technical feasibility of executing advanced 3D volumetric segmentation models on low-power edge hardware. Nevertheless, the evaluation was limited to an internal 25-case test subset and did not include external validation, prospective clinical assessment, or reader studies. Therefore, the proposed system should be interpreted as a preliminary deployment framework rather than a clinically validated tool for autonomous stroke imaging. Full article

The Internet of Things increasingly relies on EDHOC (Ephemeral Diffie–Hellman Over COSE, RFC 9528) and OSCORE (Object Security for Constrained RESTful Environments, RFC 8613) for lightweight authenticated key exchange and application-layer security. On resource-constrained devices, however, the computational cost of these protocols remains prohibitive in software: a complete EDHOC handshake requires hundreds of milliseconds to several seconds on typical embedded processors. Prior evaluations of EDHOC and OSCORE focus almost exclusively on ARM Cortex-M platforms; to the best of our knowledge, no dedicated evaluation or hardware acceleration study exists for RISC-V. This paper presents the first performance characterization of EDHOC and OSCORE on a RISC-V platform. It introduces a hardware accelerator integrated as a memory-mapped peripheral within a Rocket RV32IMAC SoC. The accelerator offloads the complete EDHOC Method 3 handshake, encompassing X25519 scalar multiplication, HMAC-SHA-256 key derivation, AES-CCM-16-64-128 authenticated encryption, and all protocol state management and message construction within a single hardware boundary; OSCORE per-packet AEAD is accelerated through a dedicated post-handshake interface using the same core. By moving the entire handshake execution to dedicated hardware, the accelerator eliminates the residual overhead that remains in software, regardless of whether individual cryptographic primitives are offloaded. Implemented on a Xilinx Arty A7-100T FPGA, the design consumes 10,597 Slice LUTs, 10,421 Slice Registers, and 15 DSP slices. The accelerator completes the EDHOC handshake in 6.64 ms and 4.52 ms for the Initiator and Responder, respectively, achieving 58× and 85× speedups over the optimized Monocypher software baseline on the same platform, and delivers 37× to 56× speedups for OSCORE per-packet AEAD acceleration across payload sizes from 10 to 1000 bytes. The host firmware footprint is reduced from over 25 KB to 3.6 KB for EDHOC-only and to 5.2 KB for the combined EDHOC and OSCORE stack. Full article

Network traffic classification is a cornerstone of network management and security. Addressing the challenges of feature extraction in encrypted traffic and the deployment limitations of traditional deep learning models on resource-constrained edge devices due to their large parameter sizes, this paper proposes a lightweight network for encrypted traffic classification, termed CEMA-Net (Convolutional Positional Encoding and Efficient Multi-scale Attention Network). Specifically, the proposed model integrates an Efficient Multi-scale Attention (EMA) mechanism with a Convolutional Positional Encoding (CPE) strategy to jointly capture global dependencies and local contextual information. To enable efficient adaptation to traffic data, an Efficient Multi-scale Attention Adapter (EMAAdapter) is designed, which reconstructs one-dimensional traffic sequences into a pseudo-2D representation and extracts horizontal, vertical, and local features in parallel. This design facilitates effective modeling of complex cross-scale dependencies in encrypted traffic with minimal computational overhead. Experimental results on three public datasets demonstrate that the proposed method, with only 0.66 M parameters, achieves superior classification performance compared with mainstream vision-based models such as ResNet-101, while significantly reducing computational cost. These results highlight the effectiveness of combining convolutional positional encoding with multi-scale attention mechanisms and provide an efficient solution for encrypted traffic classification in resource-constrained environments. Full article

In ubiquitous Wi-Fi sensing, human motion interval segmentation is crucial for applications ranging from basic intrusion detection to advanced activity understanding. Existing methods often treat the Channel State Information (CSI) primarily as time series, overlooking its rich information in the spatial and frequency domains. To address this, we propose a training-free motion segmentation method that exploits the spatiotemporal features of CSI. We first analyze the discriminative spatial distributions of the CSI Ratio on the complex plane and construct a spatiotemporally dual-constrained local density estimator to characterize motion-induced perturbations. To overcome subcarrier selection challenges, we introduce a packet-level asymmetric truncation-based fusion algorithm, which yields a feature representation with a pronounced bimodal histogram. This enables the automatic determination of the optimal segmentation threshold based on the distribution characteristics of the truncated density image. Experiments in typical indoor environments demonstrate that the proposed method achieves high accuracy in both motion event detection and interval localization. Full article

Implementing cryptographic primitives on resource-constrained IoT devices involves tight latency, code-size, and energy budgets. This work proposes a general LLVM backend instruction-selection strategy that recognizes single-bit update idioms—typically expressed as LOAD–-(AND/OR)–-STORE sequences in SHA-256 and similar bit-oriented code—and lowers them to the most efficient target-specific bit-manipulation primitive when legality and cost conditions are met. As a concrete instantiation, we implement the strategy for the Renesas RL78/G23 ISA by rewriting eligible patterns into SET1/CLR1 instructions when the constant mask targets exactly one bit. We evaluate the resulting backend on an RL78/G23 platform using cycle counts and code size (bytes) across SHA-256-driven workloads motivated by firmware integrity checking, Merkle-tree hashing, HMAC-based authentication, password-based key derivation (PBKDF2), and chunk-level update validation. The observed cycle reductions are also converted to absolute time across the device’s supported on-chip oscillator frequencies to quantify latency impact under different clocking modes. The experimental validation in this work is limited to the RL78/G23 backend implementation. The underlying instruction-selection idea may be adaptable to other RL78-family devices or to other embedded architectures that provide equivalent single-bit set/clear or bitfield operations; however, such adaptations require target-specific legality checks, cost modeling, and separate experimental validation. Full article