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Article

Accelerating EDHOC and OSCORE for Resource-Constrained RISC-V Systems

1
Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan
2
Faculty of Electronics and Telecommunications, The University of Science, Vietnam National University Ho Chi Minh City (HCMUS), Ho Chi Minh City 72711, Vietnam
*
Authors to whom correspondence should be addressed.
Electronics 2026, 15(11), 2256; https://doi.org/10.3390/electronics15112256
Submission received: 31 March 2026 / Revised: 9 May 2026 / Accepted: 19 May 2026 / Published: 22 May 2026

Abstract

The Internet of Things increasingly relies on EDHOC (Ephemeral Diffie–Hellman Over COSE, RFC 9528) and OSCORE (Object Security for Constrained RESTful Environments, RFC 8613) for lightweight authenticated key exchange and application-layer security. On resource-constrained devices, however, the computational cost of these protocols remains prohibitive in software: a complete EDHOC handshake requires hundreds of milliseconds to several seconds on typical embedded processors. Prior evaluations of EDHOC and OSCORE focus almost exclusively on ARM Cortex-M platforms; to the best of our knowledge, no dedicated evaluation or hardware acceleration study exists for RISC-V. This paper presents the first performance characterization of EDHOC and OSCORE on a RISC-V platform. It introduces a hardware accelerator integrated as a memory-mapped peripheral within a Rocket RV32IMAC SoC. The accelerator offloads the complete EDHOC Method 3 handshake, encompassing X25519 scalar multiplication, HMAC-SHA-256 key derivation, AES-CCM-16-64-128 authenticated encryption, and all protocol state management and message construction within a single hardware boundary; OSCORE per-packet AEAD is accelerated through a dedicated post-handshake interface using the same core. By moving the entire handshake execution to dedicated hardware, the accelerator eliminates the residual overhead that remains in software, regardless of whether individual cryptographic primitives are offloaded. Implemented on a Xilinx Arty A7-100T FPGA, the design consumes 10,597 Slice LUTs, 10,421 Slice Registers, and 15 DSP slices. The accelerator completes the EDHOC handshake in 6.64 ms and 4.52 ms for the Initiator and Responder, respectively, achieving 58× and 85× speedups over the optimized Monocypher software baseline on the same platform, and delivers 37× to 56× speedups for OSCORE per-packet AEAD acceleration across payload sizes from 10 to 1000 bytes. The host firmware footprint is reduced from over 25 KB to 3.6 KB for EDHOC-only and to 5.2 KB for the combined EDHOC and OSCORE stack.
Keywords: EDHOC; OSCORE; RISC-V; hardware accelerator; IoT security; FPGA EDHOC; OSCORE; RISC-V; hardware accelerator; IoT security; FPGA

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MDPI and ACS Style

Nguyen, K.-D.; Le, D.-H.; Pham, C.-K. Accelerating EDHOC and OSCORE for Resource-Constrained RISC-V Systems. Electronics 2026, 15, 2256. https://doi.org/10.3390/electronics15112256

AMA Style

Nguyen K-D, Le D-H, Pham C-K. Accelerating EDHOC and OSCORE for Resource-Constrained RISC-V Systems. Electronics. 2026; 15(11):2256. https://doi.org/10.3390/electronics15112256

Chicago/Turabian Style

Nguyen, Khai-Duy, Duc-Hung Le, and Cong-Kha Pham. 2026. "Accelerating EDHOC and OSCORE for Resource-Constrained RISC-V Systems" Electronics 15, no. 11: 2256. https://doi.org/10.3390/electronics15112256

APA Style

Nguyen, K.-D., Le, D.-H., & Pham, C.-K. (2026). Accelerating EDHOC and OSCORE for Resource-Constrained RISC-V Systems. Electronics, 15(11), 2256. https://doi.org/10.3390/electronics15112256

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