Search Results (17)

With the growing demand for secure image communication, effective encryption solutions are critical for safeguarding visual data from unauthorized access. The substitution box (S-box) in AES (Advanced Encryption Standard) is critical for ensuring nonlinearity and security. However, the static S-box used in AES is vulnerable to algebraic attacks, side-channel attacks, and so on. This study offers a novel Lorenz key and Chua key-based Reversible Substitution Box (LCK-SB) for image encryption, which takes advantage of the chaotic behavior of the Lorenz and Chua key systems to improve security due to nonlinear jumps and mixed chaotic behavior while maintaining optimal quantum cost, area, and power. The suggested method uses a hybrid Lorenz and Chua key generator to create a highly nonlinear and reversible S-box, which ensures strong confusion and diffusion features. The performance of the LCK-SB approach is examined on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms, and the findings show that quantum cost, delay, and power are decreased by 97%, 74.6%, and 35%, respectively. Furthermore, the formal security analysis shows that the suggested technique efficiently resists threats. The theoretical analysis and experimental assessment show that the suggested system is more secure for picture encryption, making it suitable for real-time and high-security applications. Full article

With advances in space, nuclear, and defense industries, the susceptibility of semiconductor integrated circuits (ICs) to radiation has increased. Radiation-induced degradation and malfunctioning of IC performance can lead to system failure, leading to significant damage. To address this limitation, this study employed mixed-stage modeling and simulation (M&S) techniques to evaluate the reliability of complementary metal-oxide semiconductor application-specific ICs (ASICs) in radiation environments. Radiation-hardened IC chips were designed and fabricated using layout modification techniques based on M&S. The ASIC, which includes the D-latch and Operational Amplifier (Op-Amp) circuits, was validated for resistance up to a total ionizing dose of 20 kGy(Si). The proposed radiation-hardened ICs demonstrated stable performance even in radiation-exposed environments, ensuring reliable operation under such conditions. The findings provide insights into overcoming radiation-induced degradation and malfunction in semiconductor integrated circuits, which is particularly relevant for advancing space, nuclear, and defense industries. Full article

Exploring the genetic landscape of native cattle is an exciting avenue for elucidating nuanced patterns of genetic variation and adaptive dynamics. Xiangnan cattle, a native Chinese cattle breed mainly produced in Hunan Province, are well adapted to the high temperature and humidity of the local environment and exhibit strong disease resistance. Herein, we employed whole-genome sequences of 16 Xiangnan cattle complemented by published genome data from 81 cattle. Our findings revealed that Xiangnan cattle are pure East Asian indicine cattle with high genetic diversity and low inbreeding. By annotating the selection signals obtained by the CLR, θπ, F_ST, and XP-EHH methods, genes associated with immunity (ITGB3, CD55, OTUD1, and PRLH) and heat tolerance (COX4I2, DNAJC18, DNAJC1, EIF2AK4, and ASIC2) were identified. In addition, the considerable introgression from banteng and gaur also contributed to the rapid adaptation of Xiangnan cattle to the environment of Southern China. These results will provide a basis for the further conservation and exploitation of Xiangnan cattle genetic resources. Full article

Bioimpedance imaging aims to generate a 3D map of the resistivity and permittivity of biological tissue from multiple impedance channels measured with electrodes applied to the skin. When the electrodes are distributed around the body (for example, by delineating a cross section of the chest or a limb), bioimpedance imaging is called electrical impedance tomography (EIT) and results in functional 2D images. Conventional EIT systems rely on individually cabling each electrode to master electronics in a star configuration. This approach works well for rack-mounted equipment; however, the bulkiness of the cabling is unsuitable for a wearable system. Previously presented cooperative sensors solve this cabling problem using active (dry) electrodes connected via a two-wire parallel bus. The bus can be implemented with two unshielded wires or even two conductive textile layers, thus replacing the cumbersome wiring of the conventional star arrangement. Prior research demonstrated cooperative sensors for measuring bioimpedances, successfully realizing a measurement reference signal, sensor synchronization, and data transfer though still relying on individual batteries to power the sensors. Subsequent research using cooperative sensors for biopotential measurements proposed a method to remove batteries from the sensors and have the central unit supply power over the two-wire bus. Building from our previous research, this paper presents the application of this method to the measurement of bioimpedances. Two different approaches are discussed, one using discrete, commercially available components, and the other with an application-specific integrated circuit (ASIC). The initial experimental results reveal that both approaches are feasible, but the ASIC approach offers advantages for medical safety, as well as lower power consumption and a smaller size. Full article

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. Full article

Proprioceptors are low-threshold mechanoreceptors involved in perceiving body position and strain bearing. However, the physiological response of proprioceptors to fatigue- and muscle-acidosis-related disturbances remains unknown. Here, we employed whole-cell patch-clamp recordings to probe the effect of mild acidosis on the mechanosensitivity of the proprioceptive neurons of dorsal root ganglia (DRG) in mice. We cultured neurite-bearing parvalbumin-positive (Pv+) DRG neurons on a laminin-coated elastic substrate and examined mechanically activated currents induced through substrate deformation-driven neurite stretch (SDNS). The SDNS-induced inward currents (I_SDNS) were indentation depth-dependent and significantly inhibited by mild acidification (pH 7.2~6.8). The acid-inhibiting effect occurred in neurons with an I_SDNS sensitive to APETx2 (an ASIC3-selective antagonist) inhibition, but not in those with an I_SNDS resistant to APETx2. Detailed subgroup analyses revealed I_SDNS was expressed in 59% (25/42) of Parvalbumin-positive (Pv+) DRG neurons, 90% of which were inhibited by APETx2. In contrast, an acid (pH 6.8)-induced current (I_Acid) was expressed in 76% (32/42) of Pv+ DRG neurons, 59% (21/32) of which were inhibited by APETx2. Together, ASIC3-containing channels are highly heterogenous and differentially contribute to the I_SNDS and I_Acid among Pv+ proprioceptors. In conclusion, our findings highlight the importance of ASIC3-containing ion channels in the physiological response of proprioceptors to acidic environments. Full article

To improve the wear resistance of the TMR blade and investigate the effect of nano-La₂O₃ and Mo on the wear resistance of laser cladding coating. 65Mn blade as the substrate, La₂O₃, Mo and Mo-La₂O₃ composite powders were added into Ni60a/SiC composite powder. Using scanning electron microscopy, X-ray diffraction, X-ray photoelectron spectroscopy and the CFT-I surface synthesizer, the phase composition, element distribution and friction and wear properties of the coating were analyzed to obtain the best composition of the composite coating. The results showed that the wear resistance of Mo-La₂O₃-Ni60a/SiC composite coating was the best. The coating was analyzed by X-ray diffraction and X-ray photoelectron spectroscopy. The coating contained hard phases such as CrB, CrC and Cr₇C₃, and the element distribution was uniform. It can be seen from the scanning electron microscope that the addition of nano-Mo and La₂O₃ improves the toughness and compactness of Ni60a/SiC composite coating, and the microstructure is refined. The friction coefficient of Mo-La₂O₃-Ni60a/SiC composite coating is 0.5, and the wear depth is 12.35 μm, 23% and 89% lower than that of 65Mn substrate, respectively. The surface roughness of the Mo-La₂O₃-Ni60a/SiC coating after wear is 2.06 μm, and the wear amount is 0.001 g. The wear mechanism of the coating is mainly adhesive wear, abrasive wear, and oxidation wear. The wear surface of the Mo-La₂O₃-Ni60a/SiC composite coating is mainly composed of micro furrows, accompanied by the generation of new wear-resistant layers. Full article

To enable a-SiC_x:H-based memristors to be integrated into brain-inspired chips, and to efficiently deal with the massive and diverse data, high switching uniformity of the a-SiC_0.11:H memristor is urgently needed. In this study, we introduced a TiSbTe layer into an a-SiC_0.11:H memristor, and successfully observed the ultra-high uniformity of the TiSbTe/a-SiC_0.11:H memristor device. Compared with the a-SiC_0.11:H memristor, the cycle-to-cycle coefficient of variation in the high resistance state and the low resistance state of TiSbTe/a-SiC_0.11:H memristors was reduced by 92.5% and 66.4%, respectively. Moreover, the device-to-device coefficient of variation in the high resistance state and the low resistance state of TiSbTe/a-SiC_0.11:H memristors decreased by 93.6% and 86.3%, respectively. A high-resolution transmission electron microscope revealed that a permanent TiSbTe nanocrystalline conductive nanofilament was formed in the TiSbTe layer during the DC sweeping process. The localized electric field of the TiSbTe nanocrystalline was beneficial for confining the position of the conductive filaments in the a-SiC_0.11:H film, which contributed to improving the uniformity of the device. The temperature-dependent I-V characteristic further confirmed that the bridge and rupture of the Si dangling bond nanopathway was responsible for the resistive switching of the TiSbTe/a-SiC_0.11:H device. The ultra-high uniformity of the TiSbTe/a-SiC_0.11:H device ensured the successful implementation of biosynaptic functions such as spike-duration-dependent plasticity, long-term potentiation, long-term depression, and spike-timing-dependent plasticity. Furthermore, visual learning capability could be simulated through changing the conductance of the TiSbTe/a-SiC_0.11:H device. Our discovery of the ultra-high uniformity of TiSbTe/a-SiC_0.11:H memristor devices provides an avenue for their integration into the next generation of AI chips. Full article

Elliptic curve cryptography (ECC) is one of the commonly used standard methods for encrypting and signing messages which is especially applicable to resource-constrained devices such as sensor nodes that are networked in the Internet of Things. The same holds true for wearable sensors. In these fields of application, confidentiality and data integrity are of utmost importance as human lives depend on them. In this paper, we discuss the resistance of our fast dual-field ECDSA accelerator against side-channel analysis attacks. We present our implementation of a design supporting four different NIST elliptic curves to allow the reader to understand the discussion of the resistance aspects. For two different target platforms—ASIC and FPGA—we show that the application of atomic patterns, which is considered to ensure resistance against simple side-channel analysis attacks in the literature, is not sufficient to prevent either simple SCA or horizontal address-bit DPA attacks. We also evaluated an approach which is based on the activity of the field multiplier to increase the inherent resistance of the design against attacks performed. Full article

The rapid evolution of Internet of Things (IoT) applications, such as e-health and the smart ecosystem, has resulted in the emergence of numerous security flaws. Therefore, security protocols must be implemented among IoT network nodes to resist the majority of the emerging threats. As a result, IoT devices must adopt cryptographic algorithms such as public-key encryption and decryption. The cryptographic algorithms are computationally more complicated to be efficiently implemented on IoT devices due to their limited computing resources. The core operation of most cryptographic algorithms is the finite field multiplication operation, and concise implementation of this operation will have a significant impact on the cryptographic algorithm’s entire implementation. As a result, this paper mainly concentrates on developing a compact and efficient word-based serial-in/serial-out finite field multiplier suitable for usage in IoT devices with limited resources. The proposed multiplier structure is simple to implement in VLSI technology due to its modularity and regularity. The suggested structure is derived from a formal and systematic technique for mapping regular iterative algorithms onto processor arrays. The proposed methodology allows for control of the processor array workload and the workload of each processing element. Managing processor word size allows for control of system latency, area, and consumed energy. The ASIC experimental results indicate that the proposed processor structure reduces area and energy consumption by factors reaching up to 97.7% and 99.2%, respectively. Full article

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm${}^2$. The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Full article

Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, designs with tunable cutoff frequency of the input high‑pass filter may suffer from excessive nonlinearity, since the gate-source voltages of the transistors forming the pseudoresistors vary following the signal being amplified. Consequently, the nonlinear distortion in such circuits may be high for signal frequencies close to the cutoff frequency of the input filter. Here we propose a simple modification of the architecture of a tunable AC-coupled amplifier, in which the bias voltages V_gs of the transistors forming the pseudoresistor are kept constant independently of the signal levels, what results in significantly improved linearity. Based on numerical simulations of the proposed circuit designed in 180 nm technology we analyze the Total Harmonic Distortion levels as a function of signal frequency and amplitude. We also investigate the impact of basic amplifier parameters—gain, cutoff frequency of the AC coupling circuit, and silicon area—on the distortion and noise performance. The post-layout simulations of the complete test ASIC show that the distortion is very significantly reduced at frequencies near the cutoff frequency, when compared to the commonly used circuits. The THD values are below 1.17% for signal frequencies 1 Hz–10 kHz and signal amplitudes up to 10 mV peak-to-peak. The preamplifier area is only 0.0046 mm² and the noise is 8.3 µV_rms in the 1 Hz–10 kHz range. To our knowledge this is the first report on a CMOS neural amplifier with systematic characterization of THD across complete range of frequencies and amplitudes of neuronal signals recorded by extracellular electrodes. Full article

Application-Specific Integrated Circuit (ASIC)-resistant Proof-of-Work (PoW) is widely adopted in modern cryptocurrency. The operation of ASIC-resistant PoW on ASIC is designed to be inefficient due to its special features. In this paper, we firstly introduce a novel ASIC-resistant PoW for low-end microcontrollers. We utilized the measured power trace during the cryptographic function on certain input values. Afterward, the post-processing routine was performed on the power trace to remove the noise. The refined power trace is always constant information depending on input values. By performing the hash function with the power trace, the final output was obtained. This framework only works on microcontrollers and the power trace depends on certain input values, which is not predictable and computed by ASIC. Full article

Bitcoin is the first cryptocurrency to participate in a network and receive compensation for online remittance and mining without any intervention from a third party, such as financial institutions. Bitcoin mining is done through proof of work (PoW). Given its characteristics, the higher hash rate results in a higher probability of mining, leading to the emergence of a mining pool, called a mining organization. Unlike central processing units or graphics processing units, high-cost application-specific integrated circuit miners have emerged with performance efficiency. The problem is that the obtained hash rate exposes Bitcoin’s mining monopoly and causes the risk of a double-payment attack. To solve this problem, we propose the error-correction code PoW (ECCPoW), combining the low-density parity-check decoder and hash function. The ECCPoW contributes to the phenomenon of symmetry in the proof of work (PoW) blockchain. This paper proposes the implementation of ECCPoW, replacing the PoW in Bitcoin. Finally, we compare the mining centralization, security, and scalability of ECCPoW and Bitcoin. Full article

Microelectrode arrays that consistently and reliably record and stimulate neural activity under conditions of chronic implantation have so far eluded the neural interface community due to failures attributed to both biotic and abiotic mechanisms. Arrays with transverse dimensions of 10 µm or below are thought to minimize the inflammatory response; however, the reduction of implant thickness also decreases buckling thresholds for materials with low Young’s modulus. While these issues have been overcome using stiffer, thicker materials as transport shuttles during implantation, the acute damage from the use of shuttles may generate many other biotic complications. Amorphous silicon carbide (a-SiC) provides excellent electrical insulation and a large Young’s modulus, allowing the fabrication of ultrasmall arrays with increased resistance to buckling. Prototype a-SiC intracortical implants were fabricated containing 8 - 16 single shanks which had critical thicknesses of either 4 µm or 6 µm. The 6 µm thick a-SiC shanks could penetrate rat cortex without an insertion aid. Single unit recordings from SIROF-coated arrays implanted without any structural support are presented. This work demonstrates that a-SiC can provide an excellent mechanical platform for devices that penetrate cortical tissue while maintaining a critical thickness less than 10 µm. Full article