Search Results (98)

Resource-constrained edge processors deployed on unmanned aerial vehicles and wearable platforms require compact, drift-robust gas classification models for a range of environmental and security monitoring applications, including CBRN-motivated scenarios. Existing approaches rely on server-grade architectures incompatible with edge-board-scale deployment, or on classifiers that chemically degrade severely under long-term sensor drift. Each UCI gas class was mapped to a CBRN behavioral category based on physicochemical analogy (molecular functional group, vapor pressure, and metal-oxide semiconductor (MOS) cross-sensitivity pattern), following established precedent. Analyzed were Ammonia (NH₃), Acetaldehyde (CH₃CHO), Acetone ((CH₃)₂CO), Ethylene (C₂H₄), Ethanol (C₂H₅OH), Toluene (C₆H₅CH₃). We propose herein an end-to-end pipeline integrating a novel 1-D convolutional neural network with depth-wise separable convolutions (LiteSensor-Net), INT8 post-training quantization, structured magnitude pruning, and a knowledge-distillation domain-adaptation module (KD–DM) for sensor drift compensation. Using the UCI Gas Sensor Array Drift Dataset (13,910 measurements; 16 metal-oxide sensors; six analyte gases; a 36-month work span). LiteSensor-Net achieved accuracy = 92.63 ± 2.02%, macro-F1 = 0.898, model size = 5.99 kB INT8 pruned, inference latency = 6.3 ms, RAM footprint = 31.7 kB, and energy per inference = 0.04 mJ (all metrics on Raspberry Pi 4B, ARM Cortex-A72). Under chronological forward-chaining evaluation, KD–DM–20 achieved 47.91 ± 18.79% mean accuracy over Batches 2–10, representing a +9.25 pp improvement over uncompensated NC (38.66%). A six-metric benchmark framework—accuracy, macro-F1, model size, inference latency, RAM footprint, and energy per inference—is introduced to standardize edge-AI gas classifier evaluation. The proposed pipeline provides an open-source, deployable foundation for edge-class gas classification systems, with CBRN detection as a motivating application. Full operational validation on certified chemical simulants remains as future work. Full article

The Internet of Things increasingly relies on EDHOC (Ephemeral Diffie–Hellman Over COSE, RFC 9528) and OSCORE (Object Security for Constrained RESTful Environments, RFC 8613) for lightweight authenticated key exchange and application-layer security. On resource-constrained devices, however, the computational cost of these protocols remains prohibitive in software: a complete EDHOC handshake requires hundreds of milliseconds to several seconds on typical embedded processors. Prior evaluations of EDHOC and OSCORE focus almost exclusively on ARM Cortex-M platforms; to the best of our knowledge, no dedicated evaluation or hardware acceleration study exists for RISC-V. This paper presents the first performance characterization of EDHOC and OSCORE on a RISC-V platform. It introduces a hardware accelerator integrated as a memory-mapped peripheral within a Rocket RV32IMAC SoC. The accelerator offloads the complete EDHOC Method 3 handshake, encompassing X25519 scalar multiplication, HMAC-SHA-256 key derivation, AES-CCM-16-64-128 authenticated encryption, and all protocol state management and message construction within a single hardware boundary; OSCORE per-packet AEAD is accelerated through a dedicated post-handshake interface using the same core. By moving the entire handshake execution to dedicated hardware, the accelerator eliminates the residual overhead that remains in software, regardless of whether individual cryptographic primitives are offloaded. Implemented on a Xilinx Arty A7-100T FPGA, the design consumes 10,597 Slice LUTs, 10,421 Slice Registers, and 15 DSP slices. The accelerator completes the EDHOC handshake in 6.64 ms and 4.52 ms for the Initiator and Responder, respectively, achieving 58× and 85× speedups over the optimized Monocypher software baseline on the same platform, and delivers 37× to 56× speedups for OSCORE per-packet AEAD acceleration across payload sizes from 10 to 1000 bytes. The host firmware footprint is reduced from over 25 KB to 3.6 KB for EDHOC-only and to 5.2 KB for the combined EDHOC and OSCORE stack. Full article

Many System-on-Chip (SoC) studies rely solely on simulation and tool-based results, encountering unexpected failures during post-silicon validation. In particular, silicon-level demonstrations of Hardware/Software (HW/SW) functional equivalence, which confirms that an FPGA-validated design operates identically on an ASIC with the same firmware, remain extremely rare. This work proposes a reproducible FPGA-to-silicon verification methodology that establishes HW/SW functional equivalence at the silicon level by applying an identical firmware source code, device driver, and memory map to both platforms. The methodology is validated on an Arm Cortex-M0-based SoC platform fabricated in Samsung 28 nm Low Power Plus (LPP) CMOS technology with a dual Inter-Integrated Circuit (I2C) interface. The fabricated chip integrates two 64KB on-chip memories within a core area of 653 $\mathsf{\mu }$m × 769 $\mathsf{\mu }$m, operates at 125 MHz, and consumes 17.5 mW at the optimal operating point of 1.0 V. The primary contributions are: (1) a reproducible FPGA-to-silicon HW/SW functional equivalence verification methodology based on shared firmware source code, device driver, and memory map across both platforms, (2) silicon-measurement-based performance characterization with verified experimental data, (3) a reproducible design methodology documenting the complete flow from FPGA verification through ASIC fabrication, including static timing closure, place-and-route, and physical verification, and (4) an extensible SoC platform architecture enabling researchers to integrate and validate their own Intellectual Property (IP) via Advanced High-performance Bus (AHB) and I2C interfaces. Full article

The rapid proliferation of Internet of Things (IoT) devices in cloud-based e-learning platforms has posed significant security risks, particularly in protecting learner information, authentication of devices, and safe communication in the highly heterogeneous learning settings. Current cryptographic solutions are largely based on classical public-key infrastructure (PKI) protocols such as RSA and ECC, which will become vulnerable with the advent of large-scale quantum computers capable of executing Shor’s algorithm. In addition, traditional perimeter-based security models are inadequate for handling the dynamics, scattered, and resource-limited characteristics of IoT-enabled educational systems. As a solution to these problems, this paper introduces ZeroTrustEdu, a scalable zero-trust cryptographic solution that combines lightweight post-quantum key management with adaptive trust scoring of cloud-connected IoT e-learning infrastructure. The proposed framework makes three fundamental contributions namely: (1) a hierarchical zero-trust security model with no implicit trust, operating across device, edge, and cloud layers; (2) a lightweight key distribution protocol based on the Module-Lattice Key Encapsulation Mechanism (ML-KEM) compliant with NIST FIPS 203 standards and (3) an adaptive behavioral trust scoring engine that dynamically adjusts device and user trust levels based on real-time interaction analytics. The architecture is evaluated using extensive NS-3 network simulations with up to 100,000 concurrent IoT nodes with formal security analysis under Chosen Plaintext Attack (CPA) and Chosen Ciphertext Attack (CCA) threat models. Comparative evaluation against RSA-2048, ECC-P256, and AES-256 baselines demonstrates that, ZeroTrustEdu delivers a 62% ± 3% (95% CI, 10 independent runs) reduction in ML-KEM encapsulation latency (12.8 ms for key encapsulation/decapsulation, contributing to a complete device authentication latency of 47.3 ms including ML-DSA signature operations), 45% reduced communication overheads, and 38% reduction in energy consumption on ARM Cortex-M4 constrained devices compared to RSA-2048 and achieves provable post-quantum security reducible to the hardness of the Module Learning With Errors (MLWE) problem. These findings demonstrate that the proposed architecture provides a viable, scalable, and quantum-resilient security solution for next-generation IoT-enabled e-learning environments. The cryptographic security of ZeroTrustEdu is guaranteed at the primitive level through NIST-standardized ML-KEM (FIPS 203) and ML-DSA (FIPS 204), with IND-CCA2 and EUF-CMA security formally proven in the respective standards; full protocol-level formal verification using automated theorem provers (ProVerif, Tamarin) is identified as valuable future work to rule out protocol-composition vulnerabilities beyond primitive-level guarantees. Full article

Post-quantum cryptographic implementations in Internet-of-Things (IoT) devices are significantly threatened by physical side-channel attacks, where practical attack risks are increased by physical accessibility and resource limitations. In particular, recent work has shown that belief propagation-based attacks can recover secret keys from lattice-based digital signatures using only a single side-channel trace of the Number Theoretic Transform (NTT). This work introduces the Quantum-Randomized Number Theoretic Transform (QR-NTT), an implementation-level defense mechanism that integrates quantum-derived entropy directly into the execution flow of lattice-based signature algorithms. Rather than treating randomness as a static input, QR-NTT uses quantum entropy to introduce controlled variability in execution ordering, arithmetic factor usage, and memory access behavior while preserving mathematical correctness and constant-time execution. The proposed framework is designed for embedded platforms and remains compatible with existing post-quantum cryptographic standards and IoT communication protocols. A complete implementation on an ARM Cortex-M4 platform, coupled with commercial quantum random number generator (QRNG) hardware, demonstrates that QR-NTT significantly degrades the effectiveness of template matching and belief propagation attacks. Experimental evaluation shows a reduction in single-trace attack success rates from over 90% to below 3% and an increase of approximately two orders of magnitude in the number of traces required for successful key recovery. These security gains are achieved with moderate overheads of 18.3% in execution time and 1.8 KB of additional memory while remaining well within practical IoT constraints. The results indicate that quantum-derived entropy can be leveraged as a practical implementation-level defense against physical attacks, complementing algorithmic post-quantum security. QR-NTT demonstrates a viable path toward strengthening the real-world resilience of post-quantum IoT systems without sacrificing deployability. Full article

Body area networks (BANs) require secure intra-body communication, yet sensor nodes are too resource-constrained for conventional public-key cryptography, and pre-shared key schemes conflict with plug-and-play clinical workflows. This paper introduces PhysioKey, a TinyML-based key agreement framework that derives symmetric session keys from physiological signals without pre-shared secrets or trusted third parties. A lightweight 1D-CNN (6320 parameters, INT8-quantized, 31.2 KB flash) extracts embeddings from ECG and PPG windows on ARM Cortex-M4 class devices, which are reconciled through fuzzy commitment with BCH error-correcting codes. Patient-level 5-fold cross-validation on PTB-XL (500 patients, dual-ECG) achieves EER of $7.8\%\pm 0.8\%$ with ROC AUC $0.978\pm 0.004$; on BIDMC (53 patients, ECG + PPG), a dual-encoder architecture reduces cross-modal EER to $30.6\%\pm 1.2\%$. Since standalone PhysioKey yields only 7–24 effective key bits, the recommended deployment mode is a hybrid PhysioKey + ECDH protocol providing 128-bit security while PhysioKey adds physical on-body authentication; standalone operation suits energy-constrained scenarios with its $27\times$ advantage over ECDH. HKDF-SHA-256 post-processing yields session keys passing all six NIST SP 800-22 tests (≥96% at the 1024-bit level). Full article

This paper presents an ARMv8/NEON-oriented implementation of NCC-Sign targeting the NTT-friendly trinomial parameter sets (NCC-Sign-1/3/5), whose dominant cost arises from mixed-radix NTT computations with $n=2^a·3^b$. We design lane-local SIMD kernels—including a four-lane Montgomery multiply–reduce, a centered modular reduction pass, a fused stage-0 butterfly, and streamlined radix-2/radix-3 pipelines—and extend them with three further optimizations: (i) radix-2 multi-stage butterfly merging to halve intermediate load/store traffic, (ii) a stride-3 vectorization technique exploiting NEON structure load/store instructions (vld3q/vst3q) to fully vectorize small-len radix-3 stages that would otherwise fall back to scalar execution, and (iii) NEON-parallel pointwise Montgomery multiplication. Using cycle-accurate PMU measurements under identical toolchains for baseline and optimized builds on Apple M1 Pro, we observe geometric-mean speedups of 1.40× for key generation, 2.24× for signing, and 2.01× for verification across NCC-Sign-1/3/5, with per-kernel gains of up to 5–6× for NTT/INTT and 7.5× for pointwise multiplication. To contextualize these results, we provide a direct comparison with the NEON-optimized ML-DSA (Dilithium) implementation of Becker et al. on the same platform, a cross-platform evaluation on Arm Cortex-A72 (Raspberry Pi 4), a Montgomery-versus-Barrett microbenchmark supporting our design choice, and an empirical constant-time assessment via dudect confirming that no timing leakage is detected in any NEON kernel under 30 million measurements. Full article

Wireless power transfer (WPT) systems have garnered significant market attention owing to their broad applicability in portable electronic devices, electric vehicles, unmanned aerial vehicles, biomedical implants, and related fields. In these systems, operating frequency and efficiency are critical factors affecting both transmission efficiency and transmission distance, making high-frequency operation an important trend for improving overall WPT performance. However, elevating the switching frequency also introduces notable challenges, including increased switching losses in power devices, limited load adaptability, and poor anti-misalignment capability, which in practice often lead to degraded system efficiency and unsatisfactory waveform quality. Accordingly, this paper proposes a high-frequency inverter power supply system capable of operating at a maximum output voltage frequency of 25 KHz. Under conditions of a 10 KHz output frequency and a 20 KΩ load, the system achieves a peak efficiency of 94.01%. A prototype was implemented through the integration of a software algorithm based on ARM Cortex-M3 core control with a hardware architecture consisting of a driving circuit, a full-bridge inverter, and a switchable filtering module. This work offers practical design insights for the development of future high-frequency, high-voltage inverter systems, while also providing valuable experimental data to support further research in this area. Full article

This work presents the development and validation of a modular low-power wind turbine emulator (WTE) specifically designed for academic research and distributed generation applications. The primary objective is to provide a flexible and cost-effective test bench capable of replicating the aerodynamic and mechanical performance of a bladed rotor without the need for wind tunnels or specific field conditions. The emulator integrates a 4.5 kW three-phase induction machine as the motor and a 1 kW permanent magnet synchronous generator (PMSG). The system is managed by an ARM Cortex M7 microcontroller, which gives instructions to a Siemens Sinamics Variable Frequency Drive (VFD) that is used for torque vector control, offering superior dynamic response to wind speed variations. The aerodynamic characteristics were previously derived using blade element momentum (BEM) theory and validated using MATLAB/Simulink simulations. Unlike traditional steady-state emulators, this study addresses dynamic behavior through an autonomous control algorithm that reduces mechanical stress and compensates for inertia differences. Experimental tests conducted in a grid-connected scenario using a commercial on-grid inverter showed high correlation between the emulator’s output and the field data of a real EOLOCAL AG1000 turbine. The results confirm the system’s reliability as a platform for evaluating power conversion systems and for future expansions, such as blade pitch control emulation. Full article

Casing collar locator (CCL) measurements are widely used as reliable depth markers for positioning downhole instruments in cased-hole operations, enabling accurate depth control for operations such as perforation. However, autonomous collar recognition in downhole environments remains challenging because CCL signals are often corrupted by toolstring- or casing-induced magnetic interference, while stringent size and power budgets limit the use of computationally intensive algorithms and specific operations require real-time, in situ processing. To address these constraints, we propose Collar Recognition Nets (CRNs), a family of domain-specific lightweight 1-D convolutional neural networks for collar signature recognition from streaming CCL waveforms. With depthwise separable convolutions and input pooling, CRNs optimize efficiency without sacrificing accuracy. Our most compact model achieves an F1-score of 0.972 on field data with only 1985 parameters and 8208 MACs, and deployed on an ARM Cortex-M7-based embedded system using the TensorFlow Lite for Microcontrollers (TFLM) library, the model demonstrates a throughput of 1000 inferences per second and 343.2 μs latency, confirming the feasibility of robust, autonomous, and real-time collar recognition under stringent downhole constraints. Full article

Arrhythmia is a life-threatening cardiovascular disease if not detected early. While deep learning models have demonstrated strong performance in ECG-based arrhythmia classification, deploying these models on resource-constrained wearable devices remains challenging. In this paper, we present a quantization-compatible neural architecture search (NAS) framework that discovers ultra-compact minority-aware convolutional neural networks (CNN). We formulate NAS as a multi-objective optimization problem, jointly maximizing balanced accuracy and minority-classes recall while minimizing model size and computational complexity. Furthermore, we constrain our search space to INT8-compatible operations. We evaluated our framework on the MIT-BIH Arrhythmia Database. We discovered NanoCNN models for binary and multi-class classification tasks. The models trained without augmentation achieved 98.7% and 98.21% overall accuracies outperforming the state-of-the-art. The discovered models required 38.3 K and 51.5 K multiply-accumulate operations (MAC) per inference, enabling their deployment on ARM Cortex-M4 microcontrollers. With augmentation and other minority-aware interventions, our model attained 91.6% balanced accuracy. Our results validated the effectiveness of the adopted search and training techniques for arrhythmia screening and diagnosis. Full article

Rapid Internet of Things (IoT) expansion creates security risks due to resource limits and evolving botnets. While Graph Neural Networks (GNNs) offer accuracy, their computational demands hinder real-time edge deployment. This study presents IoTGuard, based on a ‘Hetero-MLP’ architecture. The model replaces costly message passing with 8-dimensional categorical embeddings to capture protocol semantics. To avoid topology overfitting, L3 identifiers were excluded, relying on 13 L4 attributes selected via Pearson correlation. Evaluations on the NF-BoT-IoT-v2 dataset (37.7 M samples) demonstrate a 12.17 KB (INT8) footprint via post-training quantization. This represents a 1.9× size reduction, enabling independent operation on ARM Cortex-M7 platforms (Arm Ltd., Cambridge, UK) at 37,093 requests per second. The framework achieves a DDoS F1-score of 0.9943 with a false-positive rate of 0.0054. Comparative analysis confirms that while Random Forest is accurate, Hetero-MLP reduces parameters by 25.4× versus standard GAT models. The proposed approach balances detection depth with edge constraints, offering scalable critical infrastructure protection. Full article

Growing evidence has revealed that gut dysbiosis is associated with the development of anxio-depressive disorders through mechanisms that involve neuroimmune signaling, neurotransmitter changes, and neuroplasticity in the brain. This study investigated the effects of gingerol-enriched ginger (GEG) on specifically anxiety-related neuroinflammation-, neuroimmunity-, neuroplasticity-, neurotransmission-, and neurotoxicity-associated genes in different brain regions, as well as on alterations linked to colonic microflora-driven dysbiosis, in the spinal nerve ligation (SNL) rat model of neuropathic pain (NP). Twenty-seven male rats were assigned to 3 groups: sham, SNL, and SNL-treated with GEG at 200 mg/kg body weight (SNL+200GEG) via oral gavage for 5 weeks. Anxiety-like behavior was assessed on the elevated plus maze (EPM). mRNA expression was assessed by qRT-PCR using respective primers. Correlation between behavioral parameters and colonic microbiome composition was analyzed using the Spearman rank correlation. The SNL+200GEG group demonstrated decreased anxiety-like behavior in the SNL model. Compared to the SNL group, the SNL+200GEG group had increased mRNA expression of NRF2 (amygdala: left), LXRα (amygdala: both sides), and CX3CR1 (amygdala: both sides, hippocampus: right). GEG modulated neuroplasticity as shown by increased gene expression of PGK1 (amygdala: right, hippocampus: both sides), MEK1 (frontal cortex: both sides), LDHA (frontal cortex: both sides), GPM6A (frontal cortex: both sides, amygdala: right, hippocampus: right, and hypothalamus), and GLUT1 (amygdala: right) as well by decreased gene expression of HIF1α (in all brain regions except for the hypothalamus). GEG modulated neurotransmission via clearance of excessive glutamate release as suggested by increased gene expression of SLC1A3 (frontal cortex: both sides, hippocampus: right) and via augmenting mGluR5 signaling as shown by increased gene expression of GRM5 (hippocampus: both sides, hypothalamus) as well as downregulation of KMO, HAAO, GRIN2B, and GRIN2C influencing downstream serotonergic neurotransmission and NMDA receptor-mediated glutamatergic pathways in different brain regions. GEG further alleviated neurotoxicity through downregulated gene expression of SIRT1, KMO, IDO1, and HAAO in different brain regions. Moreover, the increased relative abundance of Bilophila spp., accompanied by decreased time spent in the EPM open arms, suggests that increased Bilophila abundance increases anxiety-like behavior. GEG supplementation mitigated anxiety-like behavior in male rats with NP, at least in part, by reducing SNL-induced inflammatory sequelae-related mRNA gene expression in different brain regions. In addition, there is a positive correlation between the abundance of Bilophila wadsworthia and the degree of anxiety-like behavior. Full article

Real-time path planning for autonomous Unmanned Aerial Vehicles (UAVs) under strict hardware limitations remains a central challenge in embedded robotics. This study presents a refined Rapidly-Exploring Random Tree (RRT) algorithm implemented within an onboard embedded system based on a 32-bit STM32 microcontroller, demonstrating that real-time autonomous navigation can be achieved under low-power computation constraints. The proposed framework integrates a three-stage process—path pruning, Bézier curve smoothing, and iterative optimization—designed to minimize computational overhead while maintaining flight stability. By leveraging the STM32’s limited 72 MHz ARM Cortex-M3 core and 20 KB SRAM, the system performs all planning stages directly on the microcontroller without external computation. Experimental flight tests verify that the UAV can autonomously generate and follow smooth, collision-free trajectories across static obstacle fields with high tracking accuracy. The results confirm the feasibility of executing a full RRT-based planner on an STM32-class embedded platform, establishing a practical pathway for resource-efficient, onboard UAV autonomy. Full article

Atrial fibrillation (AF) is the most common type of heart rhythm disorder worldwide. Early recognition of brief episodes of atrial fibrillation can provide important diagnostic information and lead to prompt treatment. AF is mainly characterized by an irregular heartbeat. Today, many personal devices such as smartphones, smartwatches, smart rings, or small wearable medical devices can detect heart rhythm. Sensors can acquire different types of heart-related signals and extract the sequence of inter-beat intervals, i.e., the instantaneous heart rate. Various algorithms, some of which are very complex and require significant computational resources, are used to recognize AF based on inter-beat intervals (RR). This study aims to verify the possibility of using neural networks algorithms directly on a microcontroller connected to sensors for AF detection. Sequences of 25, 50, and 100 RR were extracted from a public database of electrocardiographic signals with annotated episodes of atrial fibrillation. A custom 1D convolutional neural network (1D-CNN) was designed and then validated via a 5-fold subject-wise split cross-validation scheme. In each fold, the model was tested on a set of 3 randomly selected subjects, which had not previously been used for training, to ensure a subject-independent evaluation of model performance. Across all folds, all models achieved high and stable performance, with test accuracies of 0.963 ± 0.031, 0.976 ± 0.022, and 0.980 ± 0.023, respectively, for models using 25 RR, 50 RR, and 100 RR sequences. Precision, recall, F1-score, and AUC-ROC exhibited similarly high performance, confirming robust generalization across unseen subjects. Performance systematically improved with longer RR windows, indicating that richer temporal context enhances discrimination of AF rhythm irregularities. A complete Edge AI prototype integrating a low-power ECG analog front-end, an ARM Cortex M7 microcontroller and an IoT transmitting module was utilized for realistic tests. Inferencing time, peak RAM usage, flash usage and current absorption were measured. The results obtained show the possibility of using neural network algorithms directly on microcontrollers for real-time AF recognition with very low power consumption. The prototype is also capable of sending the suspicious ECG trace to the cloud for final validation by a physician. The proposed methodology can be used for personal screening not only with ECG signals but with any other signal that reproduces the sequence of heartbeats (e.g., photoplethysmographic, pulse oximetric, pressure, accelerometric, etc.). Full article