Study on Transmission Efficiency in 25 KHz Wireless Power Transfer Systems

Abstract

Wireless power transfer (WPT) systems have garnered significant market attention owing to their broad applicability in portable electronic devices, electric vehicles, unmanned aerial vehicles, biomedical implants, and related fields. In these systems, operating frequency and efficiency are critical factors affecting both transmission efficiency and transmission distance, making high-frequency operation an important trend for improving overall WPT performance. However, elevating the switching frequency also introduces notable challenges, including increased switching losses in power devices, limited load adaptability, and poor anti-misalignment capability, which in practice often lead to degraded system efficiency and unsatisfactory waveform quality. Accordingly, this paper proposes a high-frequency inverter power supply system capable of operating at a maximum output voltage frequency of 25 KHz. Under conditions of a 10 KHz output frequency and a 20 KΩ load, the system achieves a peak efficiency of 94.01%. A prototype was implemented through the integration of a software algorithm based on ARM Cortex-M3 core control with a hardware architecture consisting of a driving circuit, a full-bridge inverter, and a switchable filtering module. This work offers practical design insights for the development of future high-frequency, high-voltage inverter systems, while also providing valuable experimental data to support further research in this area.

1. Introduction

In recent years, as electronic devices show a trend toward miniaturization and higher integration levels, there has been a growing demand for higher operating frequencies in wireless power transfer (WPT) systems [1]. High-frequency operation significantly reduces the required values of compensation inductors and capacitors, thereby enabling higher power density and extending effective transmission distance. These advantages have facilitated the application of WPT in fields such as electric vehicles [2], portable electronics [3], biomedical implants, and modern industrial arc welding power supplies [4,5]. The inherent suitability of high-frequency operation for compact, lightweight, and highly integrated inductive and capacitive components further drives the development of high-frequency WPT systems, underscoring the importance of continued exploration in this direction.

However, the elevation of operating frequency introduces significant challenges to WPT systems: (1) switching losses in power devices increase markedly [1]; (2) parasitic parameters (e.g., parasitic capacitance and inductance) become non-negligible and adversely affect system efficiency [3]; (3) driving circuit design becomes more complex under high-frequency conditions, making soft switching difficult to achieve, while system load adaptability and misalignment tolerance degrade [6,7,8]; and (4) higher frequencies can lead to increased electromagnetic interference [4]. Moreover, under strongly coupled conditions, high-frequency harmonics can cause the direction of power flow between the two coils to reverse, resulting in reduced power transfer efficiency and potentially inducing system instability or bifurcation phenomena.

To address the aforementioned challenges, extensive research has been conducted by domestic and international teams. In terms of inverter topologies, resonant power amplifiers such as Class-D, Class-E, and Class-EF, as well as H-bridge and its derived topologies (e.g., multilevel, multiphase, and parallel inverters), have been widely studied and applied [8,9,10,11,12]. As reported in Ref. [3], all four proposed topologies are capable of transmitting 0.48 W of power over a 15 mm distance with an efficiency of 70%. Compared to existing studies, these topologies demonstrate higher power density and improved transmission efficiency. To enhance the overall operational power of inverter power supplies, multi-input inverter structures are employed. For instance, a Boost-type multi-input front stage with multiple windings simultaneously supplying power ensures input-stage power, while a single-polarity dual-frequency sinusoidal pulse-width modulation control is adopted at the subsequent stage to achieve inverter design [13,14,15,16,17]. In control strategies, by abandoning non-universal fixed impedance matching constraints and introducing multi-harmonic analysis to reveal the mechanism of harmonic power reverse flow under strong coupling, a globally optimized triple-phase-shift control strategy suitable for asymmetric parameters and a wide coupling range has been proposed [7]. This strategy improves the efficiency and power regulation accuracy of wireless power transfer systems. In terms of compensation network design, the LCC–LCC/S hybrid topology based on coupled-inductor self-switching enables constant-current or constant-voltage output without additional components through secondary-side switch control. It also allows autonomous mode switching under abnormal operating conditions, thereby enhancing system safety and simplifying the control structure. This approach offers considerable engineering applicability and achieves a maximum system transmission efficiency of 89.6% [6]. Furthermore, soft switching techniques (e.g., zero-voltage switching, ZVS; zero-current switching, ZCS) and dynamic frequency tracking algorithms have garnered increasing attention for minimizing switching losses and maintaining high efficiency under variable load and coupling conditions [4]. For stable transmission in wireless power transfer (WPT) systems, the selection and application of devices in inverter power supplies also represent a critical research focus [18,19,20,21,22,23,24,25,26]. These studies lay a significant foundation for the design of high-frequency WPT systems.

Despite the existing research outlined above, current WPT systems still face significant challenges in practical engineering applications, including limited output frequency, suboptimal transmission efficiency, and sensitivity to external parameter variations [27,28,29,30]. In high-frequency operation, overall efficiency tends to degrade due to pronounced switching losses and harmonic effects, making it difficult to simultaneously achieve high efficiency, high power, and high stability. Most high-frequency WPT systems reported thus far are primarily validated through software simulation, with relatively few studies focusing on the optimized design and integrated innovation of efficient and reliable mid- to high-frequency WPT systems. A systematic and complete design framework remains largely undeveloped, which to some extent constrains the practical deployment of such systems in fields such as industrial high-power charging and dynamic wireless power supply.

In response, this paper presents the development of a high-efficiency wireless power transfer system with a maximum operating frequency of 25 KHz. The system employs an STM32 timer (STMicroelectronics, Paris, France) to generate sinusoidal pulse-width modulation (SPWM) pulses. Leveraging its integrated pulse-width modulation (PWM) output module, SPWM signals are produced and fed into an IR2110S driver circuit (Infineon Technologies, Neubiberg, Germany), which subsequently generates pulses to drive a full-bridge inverter circuit. The ultimate objective is to realize a 25 KHz WPT system characterized by structural simplicity, reliable control, and high efficiency, thereby offering a feasible technical solution for medium-power wireless charging applications.

2. System Design

2.1. Hardware Design

By synthesizing the aforementioned methodologies and their respective enhancements, a wireless power transfer (WPT)(Guiyang University, Guiyang, China) system hardware design capable of operating at an inverter switching frequency up to 25 KHz has been successfully realized, as shown in Figure 1.

The hardware architecture of the inverter power supply system primarily consists of four functional modules. To achieve an output voltage frequency exceeding 50 Hz, the frequency and modulation parameters of the sinusoidal pulse-width modulation (SPWM) signal are not fixed. Therefore, a microcontroller unit (MCU) based on an ARM core is preferred for its flexibility in signal generation and control.

The SPWM signal generated by the MCU has an amplitude of only 3.3 V, which is insufficient to drive the subsequent H-bridge inverter stage. Consequently, a dedicated signal driving module is essential. This driving circuit can be realized using either discrete components or integrated circuits (ICs), with the final selection depending on the power rating and switching signal requirements of the inverter bridge. In this design, to enhance both driving capability and operational stability, a hybrid configuration combining discrete-component circuits and integrated circuits is employed. The circuit topology of the integrated driving section is shown in Figure 2.

As shown in Figure 2, D7 and C5 act as the bootstrap diode and bootstrap capacitor of the IR2110S, respectively, while C17 serves as a filter capacitor. The SD pin functions as an enable terminal, with a low-level input enabling the outputs and a high-level input disabling them. When a high-level PWM signal is applied to the HIN pin, the corresponding HO pin outputs a high level, turning on the associated power switch. Conversely, a low-level PWM signal at HIN results in a low-level output at HO, turning off the switch. The same operational logic applies to the LIN pin. In this design, SPWM signals are fed into HIN and LIN, and the IR2110S outputs two amplified SPWM signals through its HO and LO terminals.For details of the IR2110S driver circuit, please refer to Appendix A.

In the design of the inverter H-bridge, a full-bridge inverter topology is employed, driven by four complementary SPWM signals. Through the alternating switching of the four IGBTs, an initial inverted AC output is ultimately generated across the total load R connected at AC-Out. To achieve higher output power, multiple inverter H-bridges can be configured in parallel. The single-phase inverter H-bridge circuit implemented in this work is illustrated in Figure 3.

As shown in Figure 3, D25, D26, D27, and D28 are Zener diodes. The four-channel SPWM signals output by the driving circuit are fed into the gates of the power switching devices, respectively. Specifically, a high-level signal at the gate turns on the corresponding power switching device; conversely, a low-level signal turns it off. The MOSFET selected in this design is the ARF446 manufactured by Fairchild Semiconductor (Microsemi Corporation, California, USA). As an N-channel power field-effect transistor, the ARF446 features low on-resistance, high switching speed, excellent stability, low input capacitance, and ease of driving. It operates at a frequency up to 65 MHz, with key electrical parameters as follows: drain-source voltage (V_DSS) = 900 V, drain-gate voltage (V_DGO) = 900 V, and drain current (I_D) = 6.5 A (at a case temperature T_C = 25 °C).

The raw AC output of the inverter contains significant switching noise and cannot be used directly; therefore, a filtering stage is required. The filter can be implemented with either an LLC or an LC topology. In this work, an LLC filter is used with bipolar SPWM, while an LC filter is adopted for unipolar modulation. This flexible arrangement improves experimental configurability in later stages. The cutoff frequency of the LC filter is given by

$$f_C=1/2\pi \sqrt{LC}$$

(1)

In Equation (1), $f_C$ represents the cutoff frequency, L is the filter inductance, and C denotes the filter capacitance. It is important to note that the angular frequency, rather than the ordinary frequency, must be used in the calculation of the cutoff frequency. This is due to the time-dependent nature of signal variations in AC circuits, which necessitates the use of angular quantities to characterize the rate of change.

Another key consideration in the block diagram of Figure 1 is the acquisition of feedback signals. These primarily include the temperature variation within the inverter bridge. Because the inverter bridge operates under prolonged high-frequency switching, significant heat generation is unavoidable. Excessive temperature can result in device failure or output distortion, making temperature monitoring and control essential.

The acquisition of output signals involves sampling the output voltage, output current, and frequency, thereby enabling closed-loop control of the overall system.

As the experiments discussed in this paper were conducted with purely resistive loads, it is important to first clarify that the objective was to establish a baseline characterization of the inverter’s output performance. In an actual wireless power transfer system, the load is replaced by a resonant transmitting coil, while the receiving coil is coupled to an independent load. Therefore, resistive load testing provides an ideal controlled reference for investigating the voltage, frequency, and efficiency characteristics of the inverter, before introducing variables such as coil coupling and misalignment. Accordingly, future work will extend the methodology presented herein to resonant load conditions.

2.2. Software Design

In Ref. [4], an Infineon XE164 microcontroller unit (MCU)(Infineon Technologies, Munich, Germany) is employed. It integrates two compare/capture units (CCU61 and CCU62), each capable of generating two complementary pulse-width modulation (PWM)(Infineon Technologies, Munich, Germany) signals with configurable dead time. Specifically, CCU61 supplies driving pulses for IGBT1 and IGBT2, while CCU62 provides pulses for IGBT3 and IGBT4.

Ref. [5] utilizes a TMS320LF2407A digital signal processor (DSP)(Texas Instruments, Texas, USA) as the main controller. This DSP offers low power consumption, high operating frequency, and ample program memory. The functional requirements of the pulsed laser system are realized through DSP programming, which is structured around a main program and interrupt service routines.

This design employs an STM32 microcontroller from STMicroelectronics (STMicroelectronics, Paris, France), which utilizes an ARM Cortex-M3 core (STMicroelectronics, Paris, France). On-chip resources, including the timer and direct memory access (DMA) modules, are configured to generate sinusoidal pulse-width modulation (SPWM) signals.

The software logic implemented on the STM32 proceeds as follows: first, the timer is set to operate in PWM output mode. Next, the DMA module transfers SPWM waveform data rapidly to update the PWM duty cycles. Finally, upon completion of one output cycle, an interrupt flag is set to 1, triggering an interrupt that toggles the polarity between the positive and negative half cycles. The corresponding program flow is shown in Figure 4.

In this design, the PWM signals are generated from the TIM1 timer of the STM32 microcontroller. Specifically, Channel 1 (CH1) drives the upper switch of the left bridge leg, while its complementary output (CH1N) controls the corresponding lower switch. Similarly, Channel 2 (CH2) drives the upper switch of the right bridge leg, with its complementary output (CH2N) regulating the lower switch.

The SPWM frequency ${\mathrm{f}}_{\mathrm{S}\mathrm{P}\mathrm{W}\mathrm{M}}$ is calculated based on the period of the PWM (pulse-width modulation) and the number of sampling points N in one period. One period of the SPWM signal is composed of a series of PWM signals with the same frequency and amplitude but different duty cycles. Therefore, the period of the SPWM signal is the product of the period of the PWM signal in one period and the number of sampling points N.

$${\mathrm{T}}_{\mathrm{S}\mathrm{P}\mathrm{W}\mathrm{M}}={\mathrm{T}}_{\mathrm{P}\mathrm{W}\mathrm{M}}\ast \mathrm{N}$$

(2)

In Equation (2), T_SPWM represents the period of the SPWM signal, T_PWM denotes the period of the base (carrier) PWM signal, and N is the number of sampling points within one SPWM cycle.

The SPWM signal frequency can therefore be expressed as

$$f_{\mathrm{S}\mathrm{P}\mathrm{W}\mathrm{M}}={\displaystyle \frac{1}{{\mathrm{T}}_{\mathrm{S}\mathrm{P}\mathrm{W}\mathrm{M}}}}$$

(3)

By controlling the combination of T_PWM and N, the corresponding value can be obtained. The larger the number of sampling points N, the more accurate the value of $f_{SPWM}$ becomes. When the value of $f_{SPWM}$ is constant, the number of sampling points N is inversely proportional to the PWM frequency. For STM32, the maximum $f_{PWM}$ is 72 MHz, so when $f_{PWM}$ reaches its maximum value, if you want to increase $f_{SPWM}$, you need to reduce the number of sampling points N.

3. Experimental Investigation of Transmission Efficiency at 10 KHz and 25 KHz

The experimental setup in this work progressively increases the output sinusoidal voltage frequency from 50 Hz to 25 KHz while measuring key operational parameters of the inverter power system, thereby capturing the variation characteristics of its performance metrics with rising frequency. The output frequency was controlled by adjusting both the number of sampling points N and the PWM switching frequency, such that the sinusoidal output frequency satisfied ${\mathrm{f}}_{\mathrm{s}\mathrm{i}\mathrm{n}}$ = ${\mathrm{f}}_{\mathrm{S}\mathrm{P}\mathrm{W}\mathrm{M}}$. The test data included multiple sets of measurements, such as the output frequency, output waveform, output voltage, output current, and power factor.

3.1. 10 KHz Output Frequency Experimental Data

When the frequency of the output AC voltage was set to 10 KHz, the number of sampling points was configured as N = 20 and the PWM switching frequency was set to $f_{\mathrm{P}\mathrm{W}\mathrm{M}}$ = 200 KHz, resulting in an inverter output voltage frequency of $f_{sin}$ = 10 KHz. The DC input voltage was varied from 0 to 60 V in steps of 5 V, and the corresponding AC output voltage was measured. The experimental results for the inverter system under no-load conditions, including the output voltage and other key performance parameters, are summarized in Figure 5.

The output test data of the inverter power supply system under a load resistance of 20 KΩ are presented in Figure 6. Figure 7 illustrates the input power and output power of the inverter power supply system under a 20 KΩ load resistance.

When the frequency of the AC output voltage is 10 KHz and the DC input is 5 V, the waveform of the inverter result is shown in Figure 8. When the DC input is 60 V, the inverter result is shown in Figure 9.

3.2. 25 KHz Output Frequency Experimental Data

When the output AC voltage frequency was set to 25 KHz, the number of sampling points was configured as N = 16 and the PWM switching frequency was set to $f_{\mathrm{P}\mathrm{W}\mathrm{M}}$ = 400 KHz, yielding an inverter output voltage frequency of $f_{sin}$ = 25 KHz. The DC input voltage was varied from 0 to 60 V in steps of 5 V, and the corresponding AC output voltage was measured. The experimental results for the inverter system under no-load conditions, including the output voltage and other key performance parameters, are presented in Figure 10.

The measured output performance of the inverter power supply system under a 20 KΩ load is summarized in Figure 11. Figure 12 illustrates the input power and output power of the inverter power supply system measured under a 20 KΩ load.

When the frequency of the AC output voltage is 25 KHz and the DC input is 5 V, the waveform of the inverter result is shown in Figure 13. When the DC input is 60 V, the inverter result is shown in Figure 14.

3.3. Data Analysis and Summary

3.3.1. Improvement in Transmission Efficiency Under No-Load Conditions

As shown in the curves, when the DC input voltage is increased from 5 V to 60 V, the output voltage remains below the expected level if the inverter output frequency is below 5 KHz. In contrast, once the output frequency exceeds 5 KHz, the measured output voltage clearly approaches the expected value. However, when the frequency is further increased to a sufficiently high value, the output voltage again deviates from the target level. This deviation may be attributed to the use of the ARF446 NMOS transistor (Microsemi Corporation, California, USA), which, despite its favorable high-frequency performance, may impose limitations under very high switching frequencies.

As shown in Figure 15, for all curves, the rising slope closely follows the expected trend when the DC voltage is below 20 V. When the DC voltage exceeds 20 V, however, the output voltage increases at a slower rate and no longer varies linearly. This behavior is also likely related to the limited high-voltage capability of the ARF446 NMOS transistor.

3.3.2. Improvement in Transmission Efficiency Under Load Conditions

As shown in Figure 16, when a load is connected to the inverter power supply system, the output voltage decreases relative to the no-load condition, a result attributable to the circuit design and inverter conversion efficiency. These variations also enable the extraction of quantitative data on power conversion efficiency and inverter efficiency. Notably, when the inverter output frequency is near 4 KHz, the circuit maintains a relatively high output voltage even under loaded operation.

3.3.3. Impact of Total Harmonic Distortion on Transmission Efficiency

The system output voltage is AC, so it is essential for THD analysis. The THD value of the AC voltage output by the system is shown in

Table 1. THD Values at Input Voltages of 5 V and 60 V Across Different Frequencies.

Input Voltage	5 V	60 V
Frequency
50 Hz	36.22%	34.26%
100 Hz	47.14%	44.53%
500 Hz	49.80%	43.99%
1 KHz	76.99%	44.98%
3 KHz	57.37%	47.89%
4 KHz	49.64%	43.32%
5 KHz	53.94%	40.11%
10 KHz	43.83%	46.74%
15 KHz	42.61%	39.79%
20 KHz	46.98%	55.03%
25 KHz	52.16%	45.96%

.

We selected two typical values of DC input voltage for analysis, namely, the inverter output with DC voltage values of 5 V and 60 V. This analysis was conducted using MATLAB software (MATLAB, R2022a). Firstly, convert the captured waveform into a grayscale image and locate the position of the waveform in the image; reverse the color to extract waveform data and convert it into voltage values. Perform the Fourier transform again and calculate the amplitude of the fundamental wave and its harmonic components. Finally, calculate THD. The smaller the THD value, the smaller the total harmonic distortion.

As shown in Figure 17, in the low-to-medium frequency range, the THD at an input voltage of 60 V is consistently lower than that at 5 V, indicating that increasing the input voltage helps improve waveform quality and reduce harmonic distortion. Within the frequency band of 50 Hz to 500 Hz, the THD varies between 34% and 49%, which is relatively low and corresponds to favorable output waveform performance. Within the 1 KHz to 5 KHz band, THD rises markedly, especially under a 5 V input, where harmonic components increase significantly. In the higher-frequency span of 10 KHz to 25 KHz, THD values lie approximately between 40% and 55%, accompanied by noticeable waveform glitches, indicating greater difficulty in achieving clean filtered output. Elevated THD implies a higher harmonic content in the output voltage. Since these harmonics do not contribute to useful power transfer, they increase system losses and reduce overall transmission efficiency. It should be noted that the total harmonic distortion (THD) values reported in this study were estimated using an image-based waveform extraction method due to the temporary unavailability of the original oscilloscope data files. Although this approach is not standard practice, the extracted values were rigorously validated against numerically exported data from the selected test points, yielding a deviation of less than 3%. Therefore, the reported figures offer excellent reliability for observing the overall trend. Future work will employ direct digital sampling and fast Fourier transform (FFT) analysis to obtain more precise results.

3.4. Electromagnetic Compatibility (EMC) Considerations

Although a comprehensive electromagnetic compatibility (EMC) characterization is beyond the scope of this study, we have conducted a preliminary qualitative assessment of the expected electromagnetic emissions based on the system architecture and component selection

Conducted Emissions:

The primary sources of conducted emissions in the discussed inverter are the high-frequency switching transitions and output voltage harmonics. As the current prototype lacks filtering on the input DC power lines, switching noise is conducted directly back to the DC power source. Therefore, in practical applications, an input EMI filter, comprising common-mode chokes and X-capacitors, would be necessary to meet conducted emission limits. It is worth noting that while the LC output filter provides good attenuation of high-frequency switching ripple, its cutoff frequency (approximately 1.6 KHz for L = 10 mH, C = 10μF) is significantly lower than the PWM frequency (400 KHz), resulting in limited filtering effectiveness at the PWM frequency. To achieve stricter compliance, higher-order filters or additional filtering stages would be advisable.

Radiated Emissions:

Radiated emissions are primarily caused by high-frequency currents flowing in loops that exhibit significant antenna efficiency. The main radiating structures in the prototype include

The H-bridge layout, which contains high dV/dt nodes and high-current loops;

The gate drive traces carrying high-frequency PWM signals;

The output cables connecting to the load.

The prototype was constructed on a two-layer PCB without a dedicated ground plane, which may increase loop areas and radiated emissions. In a commercial product, shielding, proper layout techniques, and ferrite beads on gate drive traces would be necessary to mitigate radiated emissions.

4. Conclusions

To overcome the technical bottleneck of limited operating frequency in existing inverter power supplies that fail to meet the demands of modern applications such as industrial arc welding power systems, underwater wireless charging, and UAV endurance, this paper presents a high-frequency inverter power system capable of delivering output voltages up to 25 KHz. A frequency-tunable inverter prototype is constructed by integrating a software algorithm based on an ARM Cortex-M3 core with a hardware architecture comprising a driver circuit, a full-bridge inverter, and a switchable filter module. Under a DC input voltage range of 0–60 V, comprehensive measurements and comparative analyses are conducted on no-load/loaded output characteristics, output voltage waveforms, total harmonic distortion (THD), power factor, and inverter efficiency across various output frequencies.

Experimental results demonstrate that the system achieves a peak transmission efficiency of 94.01% at an output frequency of 10 KHz under a 20 KΩ load and 52.6% at 25 KHz under a 50 KΩ load. This work aims to advance the design of inverter power supplies through high-frequency operation, thereby promoting the development of wireless power transfer systems toward longer transmission distances, higher efficiency, and reduced losses. The key innovations of this study include the following:

• The system achieves precise frequency control through a software algorithm that dynamically adjusts both the number of sampling points N and the PWM frequency. This approach replaces conventional analog or fixed-frequency schemes, thereby enhancing system reconfigurability and control accuracy.
• An innovative switchable filter structure is designed and integrated, which automatically selects either the LC or LLC filtering topology based on the SPWM scheme. The parameters of the filtering components are correspondingly adjusted as the operating frequency increases.

This study serves as a reference for the design of 25 KHz high-frequency inverter power supplies. It theoretically outlines the entire operational workflow and provides implementation methodologies for high-frequency inverters. Furthermore, it elaborates on each subsystem component and examines the output characteristics, efficiency, and waveform quality, offering significant engineering guidance. However, certain limitations exist in practical implementation. First, the experimental validation in this study was conducted using purely resistive loads. While this approach effectively characterizes the core performance of the inverter, it does not fully represent practical wireless power transfer (WPT) scenarios involving resonant magnetic coupling. Second, the overall system efficiency is relatively low; incorporating more refined modulation techniques to reduce switching losses while maintaining stability could be beneficial. Third, the output waveform exhibits significant distortion in the high-frequency range (>15 KHz), necessitating improvements in the high-frequency filtering stage. Future work could further investigate the characteristics under different load conditions, such as conducting more comprehensive experimental tests or enhancing system efficiency while maintaining certain performance metrics. Additionally, integrating the inverter with resonant coil pairs (e.g., SS or LCC compensation topologies) and evaluating system performance under varying distances and load conditions would help further demonstrate the practical applicability of the proposed design.