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Low-Power Asynchronous Circuits
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Low-Power Asynchronous Circuits

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 January 2016) | Viewed by 26856

Special Issue Editor

Prof. Scott C. Smith

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, North Dakota State University, PO Box 6050, Fargo, ND 58108-6050, USA
Interests: asynchronous logic; NULL convention logic (NCL); sleep convention logic (SCL); computer architecture; embedded systems; VLSI; CAD tool development for asynchronous circuits; FPGAs; evolvable hardware; secure/trustable hardware; wireless sensor networks; cyber physical systems

Special Issue Information

Dear Colleagues,

The 2012 International Technology Roadmap for Semiconductors states that asynchronous circuits currently account for 22% of the logic within the multi-billion dollar semiconductor industry, and predicts that this percentage will more than double over the next 10 years. Asynchronous logic has been around for the past 50+ years. However, until recently, synchronous circuits have sufficed to meet industry needs. Consequently, asynchronous circuits were primarily utilized for niche markets and in the research domain. However, as transistor size continues to decrease, asynchronous circuits are being looked to by the industry to solve the power dissipation and process variability issues associated with these emerging sub-90nm circuits. This Special Issue will focus on state of the art low power asynchronous logic design, and on current applications of low power asynchronous circuits, such as mobile electronics, wireless sensor networks, etc.

Prof. Scott C. Smith
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • low power
  • asynchronous circuits
  • clockless logic
  • VLSI
  • mobile electronics
  • wireless sensor networks

Published Papers (3 papers)

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904 KiB  
Article
Radiation Hardened NULL Convention Logic Asynchronous Circuit Design
by Liang Zhou, Scott C. Smith and Jia Di
J. Low Power Electron. Appl. 2015, 5(4), 216-233; https://doi.org/10.3390/jlpea5040216 - 20 Oct 2015
Cited by 11 | Viewed by 7596
Abstract
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and [...] Read more.
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead. Full article
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)
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2872 KiB  
Article
Delay Insensitive Ternary CMOS Logic for Secure Hardware
by Ravi S. P. Nair, Scott C. Smith and Jia Di
J. Low Power Electron. Appl. 2015, 5(3), 183-215; https://doi.org/10.3390/jlpea5030183 - 11 Sep 2015
Cited by 11 | Viewed by 8077
Abstract
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This [...] Read more.
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU. Full article
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)
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454 KiB  
Article
Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology
by Liang Zhou, Ravi Parameswaran, Farhad A. Parsan, Scott C. Smith and Jia Di
J. Low Power Electron. Appl. 2015, 5(2), 81-100; https://doi.org/10.3390/jlpea5020081 - 18 May 2015
Cited by 29 | Viewed by 10666
Abstract
This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks [...] Read more.
This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster. Full article
(This article belongs to the Special Issue Low-Power Asynchronous Circuits)
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