Special Issue "Low-Power FPGA Designs for Next-Generation Artificial Intelligence Applications"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: 30 June 2020.

Special Issue Editors

Prof. Dr. Pasquale Corsonello
E-Mail Website
Guest Editor
Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Rende (CS) 87036, Italy
Tel. +390984494708
Interests: heterogeneus systems; field programmable gate arrays and reconfigurable systems low-power high-performance image processing
Prof. Dr. Michael Hüebner
E-Mail Website
Guest Editor
Embedded Systems for Information Technology, Ruhr-University of Bochum, Universitätsstraße 150, D-44801 Bochum, Germany
Interests: reconfigurable computing; system on chip; embedded systems
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Special Issue Information

Dear Colleagues,

The deployment of Machine Learning (ML) algorithms in once unexpected fields of application seems to be nowadays unrestrainable. Deep Neural Networks (DNN) are, presently, the most popular application models. Such multilayered networks, characterized by a large number of hidden layers and vast amounts of data to be trained, demand specialized, high-performance, low-power hardware architectures. DNN training and inference are both computation-intensive processes: Training demands a high throughput, whereas inference needs a low latency.

In the last few years, FPGAs and GPUs vendors engaged in a race to offer the best hardware platform that runs computationally-intensive ML algorithms quickly and efficiently. While GPUs are well-suited options for several fields of application, in all power-constrained scenarios, FPGAs are the natural choice. FPGA DNN implementations with reduced arithmetic precision, pruned networks, and custom high-performance hardware implementation lead to both latency and performance per watt advantages over GPUs.

Traditional FPGAs have recently become multi-processor high-performance system-on-chip (SoC). Prominent FPGA vendors rely on fin-FET 3D process technology to integrate unprecedented computational and memorization power in a single flexible chip. Such devices can deliver flexible architectures, as a mix of hardware programmable resources, DPS, RAM blocks and purposely-designed software.

Within the above scenario, this Special Issue focuses on the latest developments in the field of designing low-power high-performance architectures for next-generation ML applications by relying on the latest SoC FPGAs.

Topics include, but are not limited to:

  • FPGA implementations of DNN training/inference accelerators
  • Applications of reconfigurability in deep learning context
  • Domain-specific SoC FPGA architectures for ML
  • ML-based systems in IoT under highly constrained energy/power requirements
  • Application of approximate computing to FPGA implementations of DNN
  • Microarchitectures and Implementations of DNN applications on Heterogeneous FPGAs
  • New design methodologies for DNN on FPGAs

Prof. Pasquale Corsonello
Prof. Michael Hübner
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (1 paper)

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Research

Open AccessArticle
Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA
J. Low Power Electron. Appl. 2020, 10(1), 1; https://doi.org/10.3390/jlpea10010001 - 24 Dec 2019
Abstract
Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded [...] Read more.
Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached. Full article
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