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Recent Applications of Field-Programmable Gate Arrays (FPGAs)

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: 20 August 2026 | Viewed by 1179

Special Issue Editors


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Guest Editor
Department of Digital Systems, Silesian University of Technology, Konarskiego 18a St., 44-100 Gliwice, Poland
Interests: digital systems; control systems; reconfigurable control systems; embedded systems; systems-on-a-chip, programmable logic controllers; Industry 4.0

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Guest Editor
1. Electrical and Computer Engineering Department, University of Patras, 26504 Patras, Greece
2. Electrical and Computers Engineering Department, University of the Peloponnese, 22131 Patras, Greece
Interests: efficient implementations of cryptographic; 5G security; IoT security; DSP and ML primitives
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

There has been an emerging interest in field-programmable logic device technology (such as FPGAs) in recent years. The flexibility and logic capacity offered by modern FPGA devices make them a convenient platform for implementing various kinds of functionalities and a core element in various systems. Fast prototyping and a short “production” time are also factors that are often crucial in today's highly competitive economic environment.

Specific features characteristic of FPGAs, e.g., their specific architectural elements, dynamic partial reconfiguration, possibility of integrating general purpose logic resources with MCU/CPU cores, open new possibilities but also constitute a challenge both for application engineers and for scientists searching for new synthesis algorithms and design methodologies.

The aim of this Special Issue is to present recent research results, trends, developments, and achievements related to FPGAs. The research published may cover (but is not limited to) the following areas:

  • Synthesis and implementation methodsexploiting device-specific architecture elements, hard macros, and IP cores.
  • Design methodologies.
  • Verification and validation techniques, including formal verification methods.
  • Optimization techniques (e.g., power, area, delay).
  • Performance evaluation.
  • The implementation of intelligent algorithms directly in hardware. 
  • AI/ML on FPGAs.
  • Hardware architectures for 5G/6G networks.
  • Reconfigurable architectures, including reconfigurable control systems.
  • Dependable systems (cryptology, security algorithms, security aspects).
  • Non-trivial applications, including the following:
    • Real-time systems, real-time sensing, and computing.
    • Systems-on-a-chip (SoC).
    • Industrial control: programmable logic controllers, dedicated CPUs, flexible and expandable I/O modules, dedicated network controllers.
    • Digital signal processing.
    • Internet of things.

Both original research and review papers are welcome. We look forward to receiving your valuable contributions!

Dr. Miroslaw Chmiel
Prof. Dr. Paris Kitsos
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • field-programmable gate arrays
  • digital systems
  • control systems
  • reconfigurable control systems
  • embedded systems
  • systems-on-a-chip, logic synthesis
  • hardware-implemented algorithms

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Published Papers (2 papers)

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16 pages, 803 KB  
Article
FPGA Spectral Clustering Receiver for Phase-Noise-Affected Channels
by David Marquez-Viloria, Miguel Solarte-Sanchez, Andrés E. Castro-Ospina, Neil Guerrero-Gonzalez and Marin B. Marinov
Appl. Sci. 2025, 15(19), 10818; https://doi.org/10.3390/app151910818 - 8 Oct 2025
Cited by 1 | Viewed by 658
Abstract
This work extends our previous research on spectral clustering for mitigating nonlinear phase noise in optical communication systems by presenting the first complete FPGA implementation of the algorithm, including on-chip eigenvector computation with parallelization strategies. The implementation addresses the computational complexity challenges of [...] Read more.
This work extends our previous research on spectral clustering for mitigating nonlinear phase noise in optical communication systems by presenting the first complete FPGA implementation of the algorithm, including on-chip eigenvector computation with parallelization strategies. The implementation addresses the computational complexity challenges of spectral clustering through a heterogeneous CPU/FPGA co-design approach that partitions algorithmic stages between ARM processors and the FPGA fabric. While the achieved processing speeds of approximately 36 symbols per second do not yet meet the requirements for commercial optical transceivers, our hardware prototype demonstrates the feasibility and practical challenges of deploying advanced clustering algorithms on real-time hardware architectures. We detail the parallel Jacobi method for eigenvector computation, the Greedy K-means++ initialization strategy, and the comprehensive hardware mapping of all clustering stages. The system processes streaming m-QAM data through a windowed architecture and integrates a demapper to ensure label consistency, demonstrating improved bit error rate performance compared to K-means under severe phase noise conditions of −90 dBc/Hz at a 1 MHz offset. This implementation offers valuable insights into memory bandwidth limitations and resource utilization trade-offs, underscoring the crucial role of FPGAs as a bridge between algorithm development and high-speed optical system deployment. Full article
(This article belongs to the Special Issue Recent Applications of Field-Programmable Gate Arrays (FPGAs))
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Review

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36 pages, 450 KB  
Review
Reconfigurable SmartNICs: A Comprehensive Review of FPGA Shells and Heterogeneous Offloading Architectures
by Andrei-Alexandru Ulmămei and Călin Bîră
Appl. Sci. 2026, 16(3), 1476; https://doi.org/10.3390/app16031476 - 1 Feb 2026
Viewed by 126
Abstract
Smart Network Interface Cards (SmartNICs) represent a paradigm shift in system architecture by offloading packet processing and selected application logic from the host CPU to the network interface itself. This architectural evolution reduces end-to-end latency toward the physical limits of Ethernet while simultaneously [...] Read more.
Smart Network Interface Cards (SmartNICs) represent a paradigm shift in system architecture by offloading packet processing and selected application logic from the host CPU to the network interface itself. This architectural evolution reduces end-to-end latency toward the physical limits of Ethernet while simultaneously decreasing CPU and memory bandwidth utilization. The current ecosystem comprises three principal categories of devices: (i) conventional fixed-function NICs augmented with limited offload capabilities; (ii) ASIC-based Data Processing Units (DPUs) that integrate multi-core processors and dedicated protocol accelerators; and (iii) FPGA-based SmartNIC shells—reconfigurable hardware frameworks that provide PCIe connectivity, DMA engines, Ethernet MAC interfaces, and control firmware, while exposing programmable logic regions for user-defined accelerators. This article provides a comparative survey of representative platforms from each category, with particular emphasis on open-source FPGA shells. It examines their architectural capabilities, programmability models, reconfiguration mechanisms, and support for GPU-centric peer-to-peer datapaths. Furthermore, it investigates the associated software stack, encompassing kernel drivers, user-space libraries, and control APIs. This study concludes by outlining open research challenges and future directions in RDMA-oriented data preprocessing and heterogeneous SmartNIC acceleration. Full article
(This article belongs to the Special Issue Recent Applications of Field-Programmable Gate Arrays (FPGAs))
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