A Procedure for Fast Circuit Cross Section Estimation

Abstract

Semiconductor technologies are susceptible to radiation effects. The particle incidence in susceptible areas of an integrated circuit (IC) can generate physical interactions capable of producing errors. This paper predicts the IC cross sections for Single Event Effects. The cross section is a metric that provides an IC’s susceptibility to radiation. It deals with particle source interaction and physical design volumes. This work evaluates the IC cross section, exploring the physical design characteristics of susceptible regions in logic gates. It explores particles with low LET, identifying the charge collection areas. Also, the heavy ions are used to evaluate the critical cross section range. Distinct benchmark circuits were simulated to characterize sensitivity trends. The influence of circuit input conditions along with cells’ susceptibility reveals significant findings. The results indicate a difference up to ten times between low- and high-energy particles. Consequently, predicting the IC cross section at an early stage of the design flow is essential, especially for electronics devices used in radiation environments.

1. Introduction

The semiconductor industry is constantly seeking higher performance, lower power consumption, and device miniaturization. This provides new technology generations allowing faster and denser integrated circuits (ICs). As a consequence, the sensitivity of modern integrated circuits to radiation increases, also increasing the soft error rates (SERs), especially in space applications [1,2,3,4,5].

When an ionizing particle hits a semiconductor, it ionizes the material, generating electron-hole pairs that may be collected in a reverse biased PN junction of the transitions. During this process, current pulses may be produced, and these pulses can change in amplitude and duration, which, in certain circumstances, may lead to transient bit-flips. This event is named a Single Event Transient, belonging to a class of effects known as Single Event Effects (SEEs) [3,6,7,8]. Recent technological advances in semiconductor technology have contributed to new challenges, as the reduced voltages and capacitances of newer devices reduce the particle energy needed to produce a bit-flip. Denser circuits also increase the probability of charge being collected after a particle strike in the semiconductor [2].

Evaluating the impact of radiation in ICs is a complex process. It involves circuit fabrication and experiments in specialized facilities, or sophisticated simulations. These tests are time-consuming and require a deep understanding of the radiation environment. The semiconductor industry is investing significant resources in new approaches to dealing with the effects of radiation on semiconductors. The existing approaches to analyzing SEEs usually focus on individual devices or small memory blocks and usually disregard the potential impact of transients on complex circuit designs [9,10].

This work introduces a procedure for estimating SET IC cross sections in different technologies. The cross section is a measure of sensitivity to soft errors that accounts for the number of errors generated in a IC given a known particle fluence (integral of flux over time). The presented procedure can be adapted to different Linear Energy Transfers (LETs) of the incident particle. It identifies the most sensitive IC areas to SETs based on layout information and input vectors. It allows us to estimate the IC cross section. The procedure evaluates the cross sections based on logic, physical design characteristics, and particle range energy. With the estimated cross section and information on the particle spectrum of the target application, different circuit solutions can be compared in early design phases.

The focus is on providing a fast estimation of the cross section Weibull curve, given low- and high-LET-limit data. The analysis can be easily configured to be used with different technologies, allowing flexibility and adaptability in the design process. This procedure also identifies the hotspot vectors and reports essential information on circuit assessments.

This paper is structured as follows: Section 2 presents a comprehensive overview of the historical background, key definitions, and insights from prior research on radiation-induced soft errors. Section 3 details the proposed methodology for exploring and analyzing circuit cross sections, along with its implementation. Section 4 discusses the experimental results, focusing on the effects of benchmark circuits under different particle LET environment scenarios. Finally, Section 5 concludes by summarizing the key insights, providing a critical analysis of the findings, and suggesting directions for future research.

2. Single Event Effects

The study of radiation effects in semiconductors is crucial in current circuits, especially those adopted in safety critical applications. The needs of the aerospace and defense industries have driven the research in this field. Over the years, there has been a focus on identifying faults caused by SEEs and understanding how cosmic rays and other ionizing radiation sources affect ICs [4,6]. Several studies have explored the impact of radiation-induced soft errors in electronic devices in applications such as satellites, avionics, embedded systems, and most modern machine and deep learning algorithms [1,9,11].

Energetic particles such as alpha particles, protons, muons, and heavy ions can induce soft errors by ionizing regions near sensitive areas, typically reverse-biased PN junctions of transistors [6]. During this ionization process, free carriers are generated and separated by the electric field, with an amount being collected by the drain. This accumulation can temporarily charge or discharge the drain total capacitance, altering the logical state of circuit nodes and resulting in Single Event Transients (SETs) [9,10]. If the transient pulse emerges in a memory element, a Single Event Upset (SEU) takes place, leading to bit-flips [12]. Soft errors can occur, resulting from SETs in combinational logic captured by memory elements like flip-flops if the transient is not masked [12,13].

In this context, the cross section is a measurement used to describe the probability of a particle strike causing a soft error. When a circuit is exposed to a known particle fluence (F) and experiences a certain number of SEEs during the experiment time, the number of recorded errors is used to calculate the cross section. The fluence is obtained by integrating the particle flux over the experiment time (t).The flux is often expressed in units of particles/cm²/s. The cross section is given in units of area, often in square centimeters (cm²), and helps us to assess the sensitivity of ICs to radiation. A higher value indicates greater sensitivity. For a constant flux, the coss-section is calculated as follows:

$$CrossSection\left(\sigma \right)={\displaystyle \frac{{\#}_{Errors}}{F}}={\displaystyle \frac{{\#}_{Errors}}{{\int }_0^t\varphi dt}}={\displaystyle \frac{{\#}_{Errors}}{\varphi \times t}}$$

(1)

where F is the particle fluence, and $\varphi$ is the particle flux.

3. Related Work

Distinct approaches for evaluating or estimating the circuit susceptibility to SEEs can offer valuable insights, mainly those involving cross section assessment and prediction. These approaches can explore particle types, energy, strike angles, logical design, physical layout characteristics, masking effects, and diverse simulations.

Performing accelerated radiation ground tests is the most accurate method for achieving nanometer IC cross sections. Beaming particles with distinct LETs over the ICs provides high precision due to complex interactions between particles and circuit semiconductor materials. This precision is essential for mission-critical applications, such as aerospace, military, and high-reliability systems, where even a single event can be catastrophic [10]. However, a proper facility and prior circuit fabrication are required to perform this experiment, which is complex and expensive [14].

Other methodologies have been developed to detect, predict, or mitigate soft errors. These solutions estimate the chip cross section, and the trade-off between accuracy and task time. Generally, these approaches offer insights into the susceptibility of ICs to SEEs [8,15,16,17,18,19,20]. Technology Computer-Aided Design (TCAD) simulates ionizing particles interaction with semiconductors [21]. It provides detailed information on physical behavior and its dependency on parameters such as the particle strike position, track, and charge collection efficiency. Nevertheless, its bottleneck is the computing time, making a circuit-level simulation impossible [22].

Exhaustive simulations are unfeasible for complex hardware design. Therefore, alternative statistical approaches, like Monte Carlo (MC), are a good trade-off. They are based on sampling and uniform distributions to balance accuracy and computational time [19,20,23,24,25,26,27,28,29]. The MUSCA SEP³ uses physical and electrical mechanisms to calculate the SEE cross section error rates. It explores Monte Carlo to provide analytics about nuclear process, such as elastic reactions [24].

The TIARA framework assesses the electrical stimulation of radiation effects in terrestrial and space environments. Details can be found in [25], which evaluated manufacturing technologies such as CMOS Bulk, FinFET, and FD-SOI. Flodam presents a cross-layer reliability analysis, from the semiconductor to the application layer, which is proposed to quantify the risks of faults under environmental conditions [26]. FLUKA is a fully integrated particle physics MC for overall usage purposes [29].

The Geant4 simulates radiation effects considering the interaction of particles passing through various materials [27]. It is open-source and can be applied to high-energy physics, space, and radiation studies. Additionally, CREME96 is a core-based GEANT4, providing a state-of-the-art tool for predicting SEE rates. It utilizes phenomenological models to predict SEE rates [30]. MRED is a radiation transport code, which serves as the core computation engine [31]. Simulating radiation effects in electronic devices demands significant time and hardware resources. Providing new analysis models is essential for evaluating single particle radiation, especially direct ionizing radiation [31].

It is increasingly important to develop alternative techniques, including simulations and probabilistic testing, to provide cost-effective and timely solutions. A hybrid approach, combining multiple methodologies, allows for comprehensive and efficient analysis, ensuring that complex circuits can be thoroughly evaluated for radiation-induced faults without sacrificing too much accuracy or efficiency.

A methodology for evaluating the susceptibility of combinational standard cell cross sections to radiation-induced errors [32] was introduced in our prior work. The procedure extracts the most sensitive cell areas according to input vectors, indicating the radiation-sensitive charge collection areas. This work suggests different approaches for evaluating the cross section through physical design characteristics. It explores the scenario for low-LET particles, identifying the charge collection areas. Subsequently, it considers the heavy ion particle range to estimate the maximum cross section. Figure 1 presents the NAND cell layout, highlights both environments, and shows the cross section true table values, illustrating the sensitive regions for low LET, and susceptible planes for high LET. Figure 2 presents the standard cell 45 nm technology cross sections. Note that this work exclusively explores cells at the cross section level, although it is noteworthy to assess them at the circuit level. The next section introduces a procedure solution to perform this.

4. Single Event Effect Cross Section Estimation at Circuit Level

This section explores the proposed procedure, analyzing circuit SEE cross sections to identify and address radiation-induced errors using a standard cell library. The procedure consists of several steps, including setting up the environment and performing cross section analysis. Additionally, a case example is presented to illustrate the procedure application.

4.1. Layout-Based SET Model

A procedure for estimating the radiation circuit cross section of ICs, with a particular focus on SET faults, is introduced. The procedure can explore the impact of radiation on standard, mixed, or full-custom cell cross sections by identifying the radiation-sensitive charge collection areas to single events. Based on layout information and the input vectors, this work estimates the Weinbull curve limits, the minimum and maximum, related to LET, providing distinct scenarios in which particle ionization can be performed, depending on the hit location and the affected design layers show by Figure 3.

This procedure enables the analysis of and suggestions for different methods for evaluating the circuit cross section based on standard cell physical design characteristics. It explores the scenario for low-LET particles and identifies the charge collection areas. Afterward, it considers the heavy ion particle range to estimate the maximum cross section. To demonstrate the proposed procedure workflow, Figure 4 introduces the procedure flowchart, following the required principal steps: setting up the environment and cross section estimation analysis.

4.1.1. Environment Setup

In order to set up the environment, the proposed procedure reads a cell library, which can be a standard, mixed, or full-custom library. The next step is to extract the library cell cross sections, as shown in prior research [32]. Then, the lookup tables for low- and high-LET environments are generated. In the next step, the procedure reads the circuit netlist mapped to the same technology cell library, which, in other words, contains the cell logic functions. The Monte Carlo confidence interval, or simulation sample size (MC), is defined to provide a more reliable simulation interval, which means higher is better.

To begin, the procedure parses the circuit netlist (Verilog) through a graph structure. This structure represents gates as nodes, input/output, and signals as wire connections, creating a linked data structure. Then, according to the MC sample, N circuit input vectors are generated randomly and distributed among multithreading, dynamically dimensioned to set up the generated information and bind the data structure. The next important step involves assigning the environment to simulate the data structure required to run simulations, which will be used in the subsequent step.

4.1.2. Circuit SET Cross Section

In order to estimate the cross section of the SET circuit, it is essential to take into account the data structure compiled in the previous step, since it provides all the required information to support the subsequent analysis. This setup enables the procedure to systematically explore every SET propagation scenario across the circuit. For a more comprehensive understanding of this process, Algorithm 1 presents detailed explanations of each stage involved in the circuit cross section estimation.

Algorithm 1: Cross Section Estimation

For each input vector (i), Circuit Breadth-First Search (BFS) Algorithm 2, totalizing N, is performed. It propagates this vector (i) through logical simulation, interacting between circuit data structure levels, gates, and signals. For each level in Levels (total), it accesses each gate cross section $gat{e}_{\sigma }$ in this level by indexing the LUT database, which indicates the vulnerable gate regions according to a particle LET strike. In other words, it indicates the sensitive regions of each gate according to a particle LET strike. This operation results in $gat{e}_{\sigma }$ (gate cross section) being counted to $Circui{t}_{\sigma }$. When all levels are finished, the algorithm returns the circuit cross section vector(i). Then, the procedure stores at Simulation Database $Databas{e}_{\sigma }$ the cross section of the N circuit input vector.    

Algorithm 2: BFS (Circuit Breadth-First Search)

After simulating N vectors, the post-processing phase aims to organize the results from the Simulation Database and create the simulation logs. This includes storing the simulation time and specifications for cross section analysis. In addition, a cross section log is generated to indicate the crucial information of each input vector’s cross section and total area. Finally, the circuit statistics are compiled to provide a comprehensive overview, including maximum, minimum, and average cross section information, along with third information.

4.1.3. Analysis Illustration

In order to provide a clearer understanding of the proposed procedure, a case usage is introduced to illustrate it. The circuit c17 from benchmark ISCAS85, shown in Figure 5, has five inputs, two outputs, six NAND2 gates, eleven signals, and three gate levels. The circuit was synthesized using 45 nm FreePDK twin-well technology (n-well and p-well implants) [33]. This technology was used to extract cell cross sections and generate the respective lookup tables for low and high LET [32].

Table 1. LUT 45 nm susceptibility information.

Cell	Standard Deviation	Difference (Max − Min) μm2
BUFF	0.006	0.011
INV	0.016	0.022
NAND2	0.030	0.058
NOR2	0.045	0.096
NAND3	0.050	0.116
OAI21	0.051	0.118
NAND4	0.058	0.174
OAI211	0.062	0.185
XOR2	0.064	0.137
NOR3	0.065	0.177
OAI22	0.068	0.207
OAI221	0.079	0.273
NOR4	0.085	0.265
AOI21	0.089	0.185
AOI221	0.093	0.154
AOI211	0.094	0.243
AOI22	0.101	0.251

describes the NAND2 cross section vector susceptibilities. It is essential to recognize that the cross section penalizes specific input vectors more than others, which can be attributed to specific cell design characteristics.

To estimate the cross section of C17 for the input vector “00000”, the first step is establishing the environment and then generating a graph representation. In the graph representation, each node represents gates and the signals. Then, the procedure applies the BFS algorithm, starting with gate level 0. The first gate U0 is analyzed to respective input ${\sigma }_{00}$ and has a correspondent cross section of ${\sigma }_{low}$ = 0.044. This is followed by U2, with ${\sigma }_{low}$ = 0.044 for the same ${\sigma }_{00}$. Moving on, gate level 1 presents gates U4 and U1, both with ${\sigma }_{10}$ and ${\sigma }_{low}$ = 0.044. Lastly, at gate level 2, gate U5 has input ${\sigma }_{11}$ with ${\sigma }_{low}$ = 0.088, and U3 ${\sigma }_{11}$ has ${\sigma }_{low}$ = 0.088. The circuit cross section for low LET is ${\sigma }_{low}00000$ = $0.352$ μm², and for high LET, it is ${\sigma }_{high}00000$ = 4.088 μm².

5. Results

Using the proposed procedure combined with layout technology characterization, this work explores the particles LET range over layout levels, analyzing the most vulnerable regions to estimate the IC cross section. Several experiments were conducted to illustrate the procedure’s potential.

5.1. Low LET

To present the results of circuit SET cross section estimation, first, we characterize the standard cell library [33] and generate the LUT databases for low and high LET. This work has used a subset of combinational benchmarks: ISCAS85 [34], ISCAS89 [35], EPFL15 [36], and ITC99 [37]. The ABC logic synthesis software was used to map the circuit among the same logic library [38]. The cross section assessment of each circuit had five thousand distinct input vectors for Monte Carlo sample simulation (N).

Table 2. Benchmark results for SET cross section: analysed 51 combinational circuits.

Information/Specs				Low LET		High LET
Circuit	Gates	Area (SUM)	avg_low	std_low	min_low	max_low	avg_high	std_high	min_high	max_high
b18	47,991	79,918.09	5538.22	21.01	5467.18	5612.7	39,935.33	17.03	39,871.88	39,992.76
mem_ctrl	28,974	45,719.45	3378.67	18.32	3317.73	3457.03	22,693.35	14.98	22,641.86	22,746.3
sqrt	18,723	33,564.18	2671.56	91.78	2158.73	2866.11	16,568.18	19.58	16,457	16,626.97
log2	16,694	28,914.62	2061.31	13.11	2013.45	2113.54	14,504.46	16.93	14,431.45	14,560.72
multiplier	13,791	24,747.18	1819.03	23.36	1745.59	1950.16	12,303.69	43.95	12,110.18	12,468.63
voter	15,075	24,659.03	1761.95	6.3	1741.24	1783.92	12,345.56	4.39	12,331.02	12,362.59
b17	14,505	24,635.46	1746.17	12.97	1702.55	1792.17	12,314.07	12.62	12,268.49	12,359.74
b22	11,124	18,161.41	1272.58	11.71	1226.89	1317.89	9069.82	10.26	9024.33	9101.2
b21	7643	12,454.09	875.38	8.91	846.81	906.52	6213.96	7.86	6182.46	6243.72
b20	7228	11,776.92	831.8	8.26	804.58	868.89	5869.02	7.11	5844.96	5898.67
arbiter	6447	10,255.08	944.18	36.23	812.1	1072.09	5115.58	3.42	5102.95	5129.29
b15	4478	7852.83	565.6	8.08	534.88	598.08	3907.55	7.51	3885.91	3936.87
sin	3808	6358.32	445.7	4.79	429	461.21	3180.53	3.58	3167.9	3193.29
b14	3587	5890.45	409.58	6.06	390.79	432.9	2951.41	6	2925.64	2969.54
max	2559	3807.41	263.65	13.24	228.19	294.31	1897.59	8.43	1879.31	1917.61
bar	1995	3232.62	228.04	5.71	208.87	248.96	1568.02	8.37	1555.93	1578.06
c6288	1540	2510.12	191.39	6.5	169.66	223.19	1236.67	6.76	1196.55	1257.45
c7552	1262	2059.02	145.26	3.02	134.07	156.77	1031.1	2.88	1020.69	1041.11
c5315	997	1566.09	111.09	2.55	102.35	120.38	775.25	2.78	762.3	785.03
adder	825	1294.4	87.71	1.03	83.5	91.27	647.24	2.66	638.09	656.68
c3540	669	1154.17	86.43	2.11	79.28	93.68	576.73	1.84	569.95	582.57
priority	757	1081.88	75.55	0.99	71.74	79.77	531.69	0.99	528.38	535.58
vda	482	798.82	52.80	0.83	49.94	55.24	394.59	1.17	391.08	397.9
alu4	491	794.49	52.99	1.24	49.21	57.04	397.44	1.18	393.78	401.21
i9	430	714.55	45.42	2.77	39.24	50.82	370.1	3.49	366.86	381.16
x3	440	705.4	51.99	2.80	42.85	59.04	346.61	2.59	336.93	355.04
apex6	435	665.66	44.44	1.27	40.07	48.92	331.13	3.7	323.3	340.06
cavlc	391	645.82	43.21	1.13	40.46	46.96	322.74	1.2	318.75	326.13
rot	430	642.77	44.20	1.26	39.85	48.38	319.25	1.45	313.39	324.31
i7	349	614.5	38.43	6.31	30.40	53.59	321.6	1.77	318.53	327.28
b11	358	595.96	41.48	0.98	38.48	45.69	298.74	1.5	293.66	304.11
s1494	361	595.23	38.96	1.43	35.23	43.11	297.36	1.26	293.41	300.76
s1488	352	582.26	37.98	1.47	34.11	41.78	290.3	1.3	286.85	294.26
s1423	357	539.54	39.97	1.18	35.77	43.98	265.12	1.65	259.98	270.3
s1238	333	536.11	33.63	1.09	30.03	37.57	268.77	0.91	265.3	271.6
i6	285	489.57	29.86	2.54	24.01	35.28	261.05	4.27	256.44	272.8
s1196	299	477.22	30.84	0.80	28.24	33.86	238.34	0.82	235.52	240.63
alu2	288	466.29	31.63	0.90	29.18	34.09	232.63	0.89	229.66	235.12
c1908	238	423.37	29.78	1.02	26.68	33.93	210.65	1.27	204.39	214.44
dec	296	403.31	21.6	0.34	21.42	22.94	182.93	0.19	182.39	183.47
c499	180	363.53	27.47	1.08	23.38	31.56	177.84	1.42	171.1	182.02
c880	220	344.17	24.32	0.94	21.76	27.95	172.34	1.13	167.92	176.49
c432	196	316.88	22.31	0.74	20.09	25.55	157.92	0.46	156.14	159.53
router	208	304.14	19.59	0.59	17.68	21.98	153.31	1	149.65	157.48
b13	192	286.29	18.04	0.68	15.96	20.64	144.75	0.94	141.52	147.69
int2float	130	210.08	13.63	0.6	11.58	15.22	106.94	0.84	104.03	108.84
unreg	65	99.31	6.70	1.25	4.37	9.88	50.15	1.79	46.84	54.44
b01	25	40.65	3.03	0.37	2.16	3.68	20.17	0.4	19.33	20.76
cm162a	24	37.49	2.58	0.30	1.79	3.44	18.55	0.49	16.96	19.79
decod	22	37.35	2.63	0.03	2.56	2.70	16.82	0.14	16.51	17.13
cm151a	27	37.07	2.44	0.32	1.71	3.25	18.71	0.28	17.87	19.5
cm163a	22	34.57	2.33	0.28	1.63	3.13	17.26	0.46	15.62	18.48
parity	15	33.5	2.67	0.28	2.13	3.96	16.74	0.59	14.49	17.5
cm152a	17	23.41	1.43	0.20	0.94	2.02	11.9	0.18	11.44	12.32
cm42a	14	23.21	1.14	0.28	0.78	1.45	12.73	0.11	12.5	12.91
b02	15	21.73	1.46	0.23	1.17	1.86	10.87	0.19	10.4	11.19
cm138a	14	20.73	0.90	0.13	0.75	1.14	10.99	0.13	10.71	11.25
cm82a	10	17.38	1.27	0.15	0.98	1.55	8.69	0.32	8.17	9.33
s27	12	16.58	1.11	0.20	0.72	1.56	8.24	0.16	7.7	8.53
b1	8	12.6	0.92	0.14	0.67	1.12	6.26	0.23	5.84	6.62
majority	8	10.74	0.67	0.12	0.45	0.88	5.42	0.11	5.17	5.61
c17	6	7.82	0.42	0.06	0.31	0.57	4.07	0.12	3.91	4.26

presents the circuits’ cross section results.

The circuits’ specifications are described in the first three columns. In summary, this table shows the cross section benchmark results for low- and high-LET approaches. The substrate area column indicates the circuit area. We have defined the cell area as a combination of the pull up and pull down plane areas, indicating the critical area for high LET. For example, considering circuit c17, which contains six NAND2 gates, according to Table 2, the total area for NAND2 is 1.304 μm², composed of 0.704 μm² (pull up) and 0.564 μm² (pull down). Consequently, the c17 area is 7.82 μm². This table is sorted by area in descending order with the intention of observing the circuit SET cross section behavior.

In this experiment, we analyzed distinct benchmark circuits, ranging from a minimum of 6 gates (c17) to 47,991 gates (b18) at a maximum. Following this, the SET cross section column presents the circuits’ results’ vulnerability in terms of the average, standard deviation, minimum, and maximum for the LET scenarios. Starting with low-LET analysis, the results presented a linearity between the SET cross section and number of gates, as a higher cross section means that the circuit is more susceptible to SET faults.

To perform a deeper assessment, this article compared low- and high-average-SET cross sections. For all circuits, the difference is above 80%, following the relation between cell substrate (high-LET susceptible regions) and active areas (low-LET susceptible regions). In summary, the average high-LET circuit cross section is 86% higher than the low-LET cross section. The most prominent variation is cm138a (LGSynth91), which contains 14 gates (4 INV, 8 NAND3, 2 NOR4), and reaches above 90%. In contrast, arbiter (EPFL15) shows the lowest divergence, around 80%.

When comparing circuits of similar area, the decod circuit has 5 inputs and 16 outputs, while the c1m162a circuit has 14 inputs and 5 outputs, respectively, exhibiting a small variation in area and average cross section. When comparing the low-LET cross section for the minimum and maximum, we observe a significant 47% difference for cm162a, indicating a large variability in susceptible areas. In contrast, decod shows a difference of 5.18%, which is more than nine times lower compared to that of the second circuit. Decod has a function of assigning a unique output to each possible input, providing the cross section base, summing NOR4 all cases 2.254 μm², and exclusively shifting the gates INV and NANDs; this is the reason behind this lower volatility.

The standard deviation difference is 88% in comparison, reflecting a high disparity between both circuits’ cross sections. The number of inputs could influence this behavior, as the vectors could switch values more frequently than in decod. Table 1 details the standard cell LUT variation (min/max) details, and

Table 3. Decod vs. Cm162a structure comparison.

Cell	Decod	cm162a	Standard Deviation μm2	Difference vec Cell (Max − Min) μm2	Ws Decod μm2	Ws cm162a μm2
NAND2	2	1	0.030	0.058	0.116	0.058
INV	4	7	0.016	0.022	0.088	0.154
NOR4	16	1	0.085	0.265	4.240	0.265
AOI22	-	4	0.101	0.251	-	1.004
NAND3	-	1	0.050	0.116	-	0.116
NOR2	-	2	0.045	0.096	-	0.192
NOR3	-	4	0.065	0.177	-	0.708
XOR2	-	4	0.064	0.137	-	0.548
Total	22	24			4.444	3.045

presents a respective comparison of both circuits, including the difference between the maximum and minimum cell vector cross section, as well as the worst-case scenario for both circuits (Ws). Notably, this circuit presents a more balanced distinct gate usage than decod, which can balance the penalty to cross section. However, decod uses more NOR4 gates, which contribute directly, because it is one of the most penalyzed cells in this standard cell library.

Making a second comparison, multiplier (13,791) × voter (15,075), voter has 8% more gates than multiplier, around 1284 gates, but presents basically the same area. If we look for min and max (low-LET) values, differences of 10.49% (multiplier) and 2.39% (voter) are observed, indicating that multiplier is more susceptible to specific input vectors in critical cases. The use of 1166 AOI221 (vec 11,000 = 0.397 μm²) results in more cells than voter, and this cell exclusively and directly penalizes the circuit cross section because it is in the range of the worst cross section cells (LUT). In contribution, voter has a solid structure, which contributes to a lower discrepance all over gates’ susceptibility. The max − min difference also indicates a higher susceptibility range, around 75%, between the circuits. For sqrt (18,723) × log2 (16,694), even a difference of 10% more gates (sqrt), around 2K more than log2, presents a penalty of 13.85% in area, providing a difference between max and min of above 80%, and (log2), following the same behavior as others, contains mathematical blocks with the same static characteristics (representing all combinations and providing lower vector variability) if compared to sqrt (diff 24%).

The comparison between the maximum and minimum cross section vectors shows that, for unreg (LGSynth91), s27 (ISCAS89), and cm152a (LGSynth91), there is a maximum difference of 55%. This suggests that specific vectors may contribute to increasing the circuit’s susceptibility to single event transients (SETs). For instance, circuit c499 stands out when compared to c880 and c432, indicating that circuits with fewer gates could be more heavily impacted. Random inputs (Monte Carlo) have the potential to access more vulnerable areas within the cell collection compared to other circuits. Upon closer examination and comparison to c432 and c880, the minimum and maximum values already indicate that c499 may use more vulnerable cells despite having 16/40 fewer gates, which could affect the circuit vulnerability to SETs. This behavior is reflected in the standard deviation.

Comparing the average cross section with circuit area can establish a relation and is intended to highlight the circuit median susceptibility. The limits were cm138a 4.3% for the minimum, and arbiter 9.3% for the maximum, implicating more than 50% penalties when comparing both distinct benchmarks. In summary, for the worst low-LET case (situation), 1/10 of the area is really predisposed to SET faults. In contrast, as the circuit presents more gates, as seen in voter, b18, and mem_ctrl, the discrepancy between the vectors is lower and the average difference is around 3.75%. The difference for low LET is up 50%, and for high LET, it is 17%. This reinforces the idea of the future investigation of possible critical vectors.

5.2. High LET

Considering the worst situation, when high-LET particles ionize the integrated circuits, deep effects can be observed on the stability and operation of digital circuits. Unlike low-LET radiation, which imparts relatively soft energy levels, high-LET radiation introduces much greater energy deposition. This increased energy can result in significant effects, potentially leading to soft errors, data corruption, or even permanent damage to a circuit.

The results indicate that, for the b18 circuit from the ITC99 benchmark, the average high-LET value surged to 39,935.33 μm², representing a massive leap from its low-LET average of 5538.22 μm², around 50.28% of the area. Despite this dramatic increase in radiation impact, the circuit is marked by a relatively low standard deviation of 17.03 compared to 47.0 of the multiplier. This suggests that, while the b18 circuit is exposed to severe radiation, it performs within a narrow range of tolerance.

The b18 circuit shows a minimum value of 39,871.88 and a maximum value of 39,992.76. This range, along with a low difference of 0.30%, suggests that the circuit operates with remarkable consistency even when critical vectors are accessed. The small difference between the minimum and maximum values indicates that the circuit maintains stable performance, with minimal variability under distinct vectors. This consistency is crucial for ensuring that the circuit can function reliably in environments where radiation exposure is inevitable, such as in aerospace applications.

The findings show that, on average, 50% of the area is susceptible to SETs. In the best-case scenario, the susceptibility is 45.15% for cm42a, while in the worst-case scenario, it is 54.85% for decod. The metrics such as minimum, maximum, and standard deviation values provide critical insights into the performance stability and reliability of the circuits under extreme conditions. These metrics highlight how the circuits respond to severe energy deposition, and offer a deeper understanding of their resilience.

6. Conclusions

This work advances the understanding and prediction of circuit SEE cross sections under diverse radiation-prone environments. The results evidence a significant difference in cross section for low-LET particles, being 9.5 times lower compared to that for high LET, emphasizing the importance of considering both environments when assessing circuit cross sections. This work contributes a practical alternative for cross section estimation, balancing accuracy and computational time tasking efficiency, when compared to industrial software solutions. The procedure is adaptable across Process Design Kit (PDK) technologies, and if combined with RHBD techniques, it can provide robust and radiation-tolerant circuit IPs, supporting applications ranging from terrestrial safety-critical circuits to deep space electronics. Future work will investigate the effects of logic masking and particle interactions on placed physical designs under SEE analysis, and will assess how layout-dependent phenomena such as charge sharing and strike location influence circuit-level susceptibility.