Wideband CMOS Variable Gain Low-Noise Amplifier with Integrated Attenuator for C-Band Wireless Body Area Networks

Abstract

This work presents a wideband variable gain low-noise amplifier (VGA-LNA) specifically engineered for medical systems operating in the C frequency band, which require the substantial amplification of low-intensity signals. The proposed design integrates a low-noise attenuator with a low-noise amplifier (LNA), fabricated using 90 nm CMOS technology and leveraging a combined common-source and common-gate topology. The integrated LNA achieved a notable power gain of 29 dB across a broad bandwidth of 2 GHz (6.4–8.4 GHz), maintaining an average noise figure (NF) below 3.14 dB. The design ensures superior impedance matching, demonstrated by reflection coefficients of S11 < −18.14 dB and S22 < −20.23 dB. Additionally, the amplifier exhibits a third-order input intercept point (IIP3) of 21.15 dBm while consuming only 83 mW from a 1.2 V supply voltage. A low-noise attenuator was incorporated at the input side to enable effective gain control through a digitally controlled variable gain, with step sizes ranging from 0.4 to 3.3 dB. This configuration enables a dynamic range of the transmission coefficient (|S₂₁|) from 16 dB to 23 dB, adjustable by 0.4 dB to 3.3 dB with a trade-off in an NF maintained at 6 dB. The VGA-LNA demonstrates exceptional potential for integration into wireless body area networks (WBANs), balancing flexible gain control with stringent performance metrics.

1. Introduction

LNAs have attracted significant attention as a vital component of circuit design in the field of communication and medical systems, owing to their ability to amplify weak input signals while minimizing external noise. LNAs enhance the performance and efficacy of medical systems by improving the signal quality and sensitivity. Recent progress has aimed at achieving a better performance of the gain, bandwidth, and noise to meet the demands of modern diagnostic applications. For example, at 6.5 GHz, the microwave breast cancer imaging requires a minimum LNA gain of 20–25 dB, as high sensitivity is required to detect weak reflections from soft tissues. At 6.8 GHz, microwave radiometry is used for non-invasive deep tissue temperature monitoring (e.g., tumors, brain), where the signal levels are extremely low, requiring 20–30 dB gain. At 7.0 GHz, a WBAN (wireless body area network) supports high-data-rate medical telemetry over short distances, but to maintain data integrity in noisy environments, an LNA gain of 15–20 dB is needed. At 7.2 GHz, microwave brain imaging for stroke detection requires a higher gain of 25–30 dB because brain signals are very weak after passing through the skull. At 7.5 GHz, the measurement of tissue dielectric properties is mainly a research application, which requires 20–25 dB gain due to the low signal strength. At 7.8 GHz, microwave ablation monitoring (such as for liver or kidney tumors) requires real-time monitoring, which requires around 20–25 dB gain. At 8.0 GHz, implantable device telemetry (e.g., for glucose sensors) operates over short distances and typically requires 15–20 dB gain. Finally, at 8.4 GHz, deep tissue imaging research uses high-resolution microwave imaging, where weaker return signals at higher frequencies require a gain of 25–30 dB.

The design of LNAs with various topologies faces challenges in limiting their use in low-power or high-performance applications like narrowband impedance matching, selective gain, high supply voltage needs, and poor noise performance [1,2]. Achieving all features simultaneously is a major challenge, as conventional techniques often limit the ability to meet all specifications at once [3,4]. Although existing designs such as resistive shunt-feedback LNAs, and UWB LNAs address noise and bandwidth issues, many multi-stage designs consume a high power and occupy more area [5,6]. Traditional LNA architectures particularly limit the bandwidth. In contrast, CMOS-based approaches offer an improved linearity, a better frequency response, low power consumption, and a high integration potential, effectively addressing the challenges in noise suppression and bandwidth optimization. So, an UWB LNA could be highly linear, with its performance compared with advanced CMOS designs [7,8,9,10]. The scalability of CMOS technology further makes it suitable for wideband applications and RF circuit design. CMOS-based LNA strategies have been explored in RF circuit principles for LNA development. Together, these insights highlight significant advancements in LNA performance, efficiency, and integration [11]. For example, the need for low-power, high-performance CMOS RF circuits in wireless communication is emphasized in [12,13], highlighting the importance of LNAs in amplifying weak signals with minimal noise. The challenges in designing reconfigurable multiband LNAs, such as impedance matching and maintaining low noise, are discussed. The development of an effective LNA is crucial for multi-standard receivers. The design of a two-stage UWB LNA in [14] tackled challenges like noise, impedance matching, and bandwidth improvement, showing a strong performance with low noise, a high power gain, and a good power efficiency, and the paper provides a clear explanation of the LNA’s design, operation, and performance. To further contextualize our contribution, we reviewed recent LNA designs targeting frequencies within or close to the 6.4–8.4 GHz band relevant to WBANs and medical systems. For example, Kumar et al. [12] demonstrated a wideband 2–5 GHz CMOS LNA with an NF $\approx 6$ dB and |S21| $\approx 13$ dB, while Lu et al. [14] reported a UWB LNA for 3.1–10.6 GHz that achieved |S21| $\approx 16-18$ dB and an NF in the 2.5–3.4 dB range. Similarly, Huang et al. [9] designed a 65 nm CMOS resistive-feedback LNA with a bandwidth extension up to 8 GHz, but with a limited gain (≈11 dB). Compared to these works, our proposed VGA-LNA achieved a significantly higher forward gain (≈29 dB), a competitive NF (≤3.14 dB standalone), and digitally programmable variable gain control (≈7 dB range), which are features that have not been simultaneously reported in earlier designs.

The resonance frequency can limit the bandwidth, emphasizing the trade-off between the usable bandwidth and noise figures in MPI systems [15]. A multi-stage (four-stage) optimized LNA provides efficient amplification with good isolation and low noise levels [16]. Additionally, the optimized biasing technique reduces input noise and power consumption, showing strong potential for biomedical applications [17].

In LNA designs, the common gate topology is preferred in the input stage due to its ease of impedance matching, excellent noise characteristics, and widened capabilities, which make it suitable for 50 $\Omega$ source matching. Again, a common source topology can be used as an amplification stage in LNAs due to its high voltage gain for amplifying weak signals. Its high input impedance makes it appropriate for high-impedance sources and allows for easy gain control, providing flexibility in the design. Additionally, the simple design and good isolation between the input and output enhance the stability of the CS stage, making it a reliable choice for amplification. Compared to prior works, this design offers a broader applicability, low noise, and tunable gain—ideal for dynamic medical applications [18,19,20,21].

In this work, we propose a two-stage LNA using a common gate followed by a common-source topology with an input-side attenuator for improved input matching and noise performance, as shown in Figure 1. Designed in 90 nm tech., the CG-CS cascade achieved a high gain and bandwidth, targeting 7.616 GHz with a 1.7 GHz bandwidth, making it ideal for wideband biomedical applications. A buffer circuit enhanced the output noise immunity. The main challenge was balancing the power while maintaining a stable high gain, as lower supply voltages reduce the gain margin and increase the noise sensitivity. To address this, the input-side attenuator offers a gain-adjustable solution for medical applications. Circuit-level simulations showed an improved performance over previous work in Cadence Virtuoso. Section 2 details the design methodology, Section 3 covers the performance analysis, Section 4 presents the results, and Section 5 concludes the study. The design is compact and efficient, promising significant improvements in medical applications.

2. Proposed Variable Gain Low Noise Amplifier

2.1. Proposed LNA

The design of wideband LNAs becomes extremely challenging when analog and RF circuits operating in the sub-threshold zone display increased thermal noise, a poorer bandwidth, and a poor linearity, even while sub-threshold biasing gives better ${\displaystyle \frac{g_m}{I_d}}$ compared to strong inversion. Our suggested LNA provides a high linearity, a broad bandwidth, a modest gain, and a reasonable noise figure. To guarantee optimum performance, a number of crucial elements (such as the frequency range, gain, noise figure, input/output impedance, and power consumption) must be taken into account when constructing a low-noise amplifier (LNA). We first established the operational frequency range of 6.4 GHz to 8.4 GHz. A common gate (CG) stage and a common source (CS) stage with a gain-boosted, source follower buffer circuit were both included in the proposed LNA. In Figure 2, the schematic of the proposed wideband LNA is shown. The component values of LNA are summarized in

Table 1. Component values.

Aspect Ratio	${(\mathit{W}/\mathit{L})}_1$	${(\mathit{W}/\mathit{L})}_2$	${(\mathit{W}/\mathit{L})}_3$	${(\mathit{W}/\mathit{L})}_4$
	40u/100n	80u/100n	45u/100n	28u/100n
	${(W/L)}_5$	${(W/L)}_6$	${(W/L)}_7$
	45u/100n	45u/100n	45u/100n
Inductor (nH)	$L_1=1.9$	$L_2=1.2$	$L_3=4.3$	$L_4=1.4$
Capacitor (pF)	$C_1=0.6$	$C_2=0.35$	$C_3=8$
Resistors ($\Omega$)	$R_1=50$	$R_2$ = 15 × 103	$R_3$ = 1 × 103	$R_4=15$
	$R_5=50$	$R_6=18$	$R_7=15$

. The common gate amplifier circuit was utilized as a first stage because it offers superior input matching due to its low input impedance, low noise performance, and enhanced linearity. The load on the CG stage is inductive (L₁), which offers a better noise performance. C₁, the coupling capacitor, blocks the DC and passes the AC signal. An LC tank is formed by L₂ and C_gs1. The CG-CS cascaded stage was included to maintain low noise levels, supply the required gain, and permit design modifications to satisfy particular operational needs. By resonating with M₂’s total capacitance at the drain, the CS stage load L₃ offers shunt peaking; improves the low-frequency gain, which controls the peak at resonance; and expands the bandwidth. L₄ in the CS stage is used for obtaining a better gain flatness. Two mirror circuits were used here as a biasing circuit. They consisted of a transistor (M₆, M₇), resistor (R₆, R₇), and V_DD. C₃ is connected between the gate and the ground terminal to ensure a good AC grounding and to bypass the noise contributed by the biasing circuit. R₄ was used here for reverse isolation.

To match and measure the output, a source follower buffer was introduced, which isolated the output of the CS stage from the load impedance variation. After the measurement, the buffer’s influence must be eliminated to extract the LNA’s performance alone from the entire circuit. The passive component values used in the design represent idealized synthesis outcomes used for circuit-level simulations. We recognize that these values exceed the practical ranges of on-chip passives in 90 nm CMOS technology. In future work, these will be replaced with technology-compatible scaled passives and validated through layout-level EM simulations and eventual chip fabrication.

2.2. Variable Gain Attenuator

The proposed attenuator employs a single-stage $\pi$ topology integrated into the LNA input, featuring five cascaded attenuation phases. This configuration was selected for its superior impedance matching, compact control logic, and robustness against parasitic effects at the C-band, making it particularly well-suited for medical WBAN applications, where flexible gain control and reliability are critical. Each phase includes a pair of FET-switched shunt branches (transistors M₁₅/M₁₈ and M₁₆/M₁₇) alongside fixed resistors (3R/10R) to ensure smooth impedance matching at both the input and output [22]. The transistor gate widths are 2 $\mu$m, with R = 10 $\Omega$, optimized via S-parameter simulations. There are 2 attenuation states. Low-attenuation state: Series FETs are ON (minimal R), and shunt FETs are OFF. Loss is dominated by the nonzero on-resistance at low frequencies; high-frequency loss is further influenced by parasitic capacitances. High-attenuation state: Shunt FETs are ON, and series FETs are OFF.

Figure 3 illustrates the simulated frequency response of the stand-alone attenuator, demonstrating insertion loss values ranging from 6 dB to 24 dB in discrete 2 dB steps. The attenuation states are programmed through six digital control voltages (Vc), with the logic combinations summarized in

Table 2. The gain of the attenuator.

Vc	V1	V2	V3	V4	V5	Attenuation (dB)
Low	High	Low	Low	Low	Low	−6
Low	Low	High	Low	Low	Low	−8
Low	Low	Low	High	Low	Low	−10
Low	Low	Low	Low	High	Low	−12
Low	Low	Low	Low	Low	High	−14
High	High	Low	Low	Low	Low	−16
High	Low	High	Low	Low	Low	−18
High	Low	Low	High	Low	Low	−20
High	Low	Low	Low	High	Low	−22
High	Low	Low	Low	Low	High	−24

. Each control line operates in binary mode, where the high and low states correspond to 1.0 V and 0 V, respectively. A simple shift-register control manages V_c (and its complement, V_c’), enabling a compact 6-bit digital control scheme. When V_c = 0, V_c’ = 1 (M₁₆ and M₁₇ ON), the attenuation spans 22–24 dB. Reversing the logic (V_c = 1, V_c’ = 0) (M₁₅ and M₁₈ ON) yields 6–20 dB [23]. If both control bits are set to OFF (logical Low), all FETs remain OFF, causing the attenuator to default to 22 dB attenuation. This can be treated as a fail-safe high-attenuation fallback to avoid undefined gain. Optionally, the controller can flag this as an invalid state or trigger an alert [24].

2.3. Designing Method

This study was simulation-based using the Cadence Virtuoso 90 nm technology software, with the component values (resistors, inductors, and capacitors) determined by a suitable matching network. An appropriate matching network was used to estimate the values of the component. To obtain optimum power transmission, matching networks were utilized to match the impedance from the gate to the source and the source to the load. We computed the input and output impedance values first using the simulation tool Cadence Virtuoso. Subsequently, the suitable network topology was chosen; RC networks and L-networks are instances of common topologies. The performance of the matching network was analyzed by simulation, with a special focus on the bandwidth, gain, efficiency, and return loss. Initially, we began with Smith chart-based optimization and a theoretical Q-value analysis to guide the matching network design. Subsequently, these parameters were refined using Cadence Virtuoso, where Smith chart- and Q-value-guided optimization were implicitly embedded within the simulation environment. If the performance was not up to par, the design was repeated numerous times by varying the component value or topology until the intended outcome was achieved.

3. Performance Matrix Analysis

3.1. Input and Output Matching

Characterizing the impedance and admittance of a two-port network operating at low frequencies often involves using the impedance matrix (Z parameters) and admittance matrix (Y parameters). However, these two approaches are insufficient for a network that operates at high frequencies. An S-parameter analysis or scattering can be used instead. In this instance, the S-parameter matrix provides the link between the incident power waves that are reflected.

Let a₁ and a₂ be incident waves, and b₁ and b₂ be transmitted waves. Using a two-port network in the S-parameter analysis,

$$\left[\begin{array}{c}{b}_1\\ b_2\end{array}\right]=\left[\begin{array}{cc}{S}_{11}& S_{12}\\ S_{21}& S_{22}\end{array}\right]\times \left[\begin{array}{c}{a}_1\\ a_2\end{array}\right]$$

The equation representation of the matrix is as follows:

$$\begin{array}{cccc}\hfill b_1& =S_{11}{a}_1+S_{12}{a}_2,\hfill & \hfill b_2& =S_{21}{a}_1+S_{22}{a}_2,\hfill \\ \hfill S_{11}& ={\displaystyle \frac{b_1}{a_1}}(\mathrm{when}{a}_2=0),\hfill & \hfill S_{12}& ={\displaystyle \frac{b_1}{a_2}}(\mathrm{when}{a}_1=0),\hfill \\ \hfill S_{21}& ={\displaystyle \frac{b_2}{a_1}}(\mathrm{when}{a}_2=0),\hfill & \hfill S_{22}& ={\displaystyle \frac{b_2}{a_2}}(\mathrm{when}{a}_1=0).\hfill \end{array}$$

where

• $S_{11}$ is the input port voltage reflection coefficient,

  $$S_{11}=\left|{\displaystyle \frac{Z_{\mathrm{in}}-Z_s}{Z_{\mathrm{in}}+Z_s}}\right|.$$
• $S_{12}$ is the reverse voltage gain.
• $S_{21}$ is the forward voltage gain.
• $S_{22}$ is the output port voltage reflection coefficient.

Impedance matching can be achieved in various ways. For a wideband CG-LNA, input matching is accomplished by setting its transconductance to $g_m={\displaystyle \frac{1}{R_s}}$, where $R_s=50\Omega$.

This represents the source impedance. To minimize mismatching issues, the LNA’s input must be matched precisely to 50 $\Omega$. Since the impedance is purely real, achieving a 50 $\Omega$ match also enables simultaneous conjugate power matching, ensuring the best possible power transmission and fulfilling the system requirements. Therefore, selecting the appropriate methods to obtain a 50 $\Omega$ input impedance, as shown in Figure 4, is essential. The small-signal equivalent circuit for the impedance calculation is shown in Figure 5.

In Figure 5, Z_d is the impedance of the load, Z_in2 is the input impedance of the next stage, and g_m1 is the trans-conductance of the MOS transistor in common-gate configuration.

Now,

$$Z_{\mathrm{in}}={\displaystyle \frac{1}{g_{m1}+\frac{1}{Z_s}+\left(1-g_{m1}{Z}_o\right)(R_o+Z_o)}}$$

(1)

where

$$\begin{array}{cc}\hfill Z_s& =j\omega L_2 \Vert {\displaystyle \frac{1}{j\omega C_{\mathrm{gs}}}}\hfill \end{array}$$

(2)

$$\begin{array}{cc}\hfill Z_o& ={\displaystyle \frac{1}{j\omega C_{\mathrm{gd}}}} \Vert Z_d \Vert Z_{\mathrm{in}2}\hfill \end{array}$$

(3)

Based on the aforementioned deductions, the following observations can be made: Due to the dominance frequency-dependent Zs in the imaginary component, the common gate stage’s unsatisfactory matching occurs throughout the band. The tank circuit should be designed to resonate near the center of the 6.4–8.4 GHz band to ensure good broadband matching and maintain a real input impedance close to 50 $\Omega$. The best input matching over the given bandwidth was found in an MOS transistor with an aspect ratio of ${\displaystyle \frac{40u}{100n}}$ and L₂ = 1.2 nH, according to the simulations. The value of S₁₁ was −20.528 dB, suggesting better input matching at the operating frequency (7.6 GHz) in Figure 6a. Only a small amount of power—approximately 1%—was reflected back at the input side, while the majority of the power entered the amplifier rather than bouncing. Similarly, the value of S₂₂ in Figure 6b indicates good output matching, meaning that most of the power was transmitted rather than reflected.

3.2. Noise Analysis

An LNA’s noise performance is directly correlated with the matching of its input. Wideband input matching, which cannot be tuned for a specific frequency, typically results in higher inherent noise compared to narrow-band matching. Therefore, the strict trade-off between wideband input matching and the noise figure of the wideband LNA must be carefully evaluated. It should be noted that the noise contribution of the first-stage amplifier is critical, as the source noise has already been amplified up to that point. The noise factor is further degraded by a product of the total gain products up to that point when compared to the noise generated by the preceding system, along with the already-generated source noise of the system [25,26].

The key metric for assessing a system’s noise performance is the noise figure (also known as the noise factor). The partnership is as follows:

$$\mathrm{NF}=10·{log}_{10}\left(F\right)$$

The noise factor due to termination is given by the following expression:

$$F={\displaystyle \frac{\mathrm{Total}\mathrm{power}\mathrm{of}\mathrm{output}\mathrm{noise}}{\mathrm{Total}\mathrm{power}\mathrm{of}\mathrm{output}\mathrm{noise}\mathrm{due}\mathrm{to}\mathrm{source}\mathrm{alone}}}=2+{\displaystyle \frac{4\gamma }{\alpha }}·{\displaystyle \frac{1}{g_{m}R}}$$

(4)

where $\gamma$ is the MOS transistor’s coefficient of channel thermal noise and is defined as the ratio of the trans-conductance and the zero-bias drain conductance. $\gamma$ is process-dependent and difficult to control. The noise performance can be optimized by increasing the trans-conductance of the MOS transistor, i.e., trading off the 50-input matching. For the first stage,

$$F=2+{\displaystyle \frac{\gamma }{\alpha }}+{\displaystyle \frac{R_5+R_{L2}}{R_{L1}}}$$

(5)

where R_L1 is the parasitic resistance of the drain inductor L₁; (R₅ + R_L2) is the input source signal; and R_L2 is the parasitic resistance of the source inductor L₂. As shown in Figure 7b, inductively source-degraded common source topology is commonly used in wideband LNA designs because it is a better option for concurrently achieving optimal noise and good input matching.

$$Z_{\mathrm{in}}={\displaystyle \frac{g_{m_3}}{(C_1+C_{gs3}+2C_{gd})L_4}}+j\left[{\omega }_H{L}_4-{\displaystyle \frac{1}{{\omega }_H(C_1+C_{gd}+C_{gs3})}}\right]$$

(6)

where C_gs3 represents the gate to the source capacitance of M₃. By adjusting C₁, L₄, C_gd, and C_gs3 so that, at the input frequency, the imaginary term equals zero, it is possible to obtain a real term of 50 $\Omega$ without the need for a resistor. Moreover, it offers simultaneous power matching. It is most common to use this type of arrangement when developing narrow-band LNAs.

$$\begin{array}{cc}\hfill & \left({\omega }_H{L}_4-{\displaystyle \frac{1}{{\omega }_H(C_1+C_{gd}+C_{gs3})}}\right)=0\hfill \end{array}$$

(7)

$$\begin{array}{cc}\hfill & \Rightarrow {\omega }_H={\displaystyle \frac{1}{\sqrt{L_4(C_{gs3}+C_{gd}+C_1)}}}\hfill \end{array}$$

(8)

$$\begin{array}{cc}\hfill & \mathrm{and}{Z}_{\mathrm{in}}={\displaystyle \frac{g_{m_3}}{(C_1+C_{gs3}+2C_{gd})L_4}}=50\Omega \hfill \\ \hfill & \mathrm{where}\hfill \end{array}$$

(9)

$$\begin{array}{cc}\hfill & C_{gs3}={\displaystyle \frac{2}{3}}{C}_{\mathrm{ox}}{W}_{\mathrm{opt}}{L}_4,g_{m_3}={\displaystyle \frac{2I_d}{V_{\mathrm{ov}}}},W_{\mathrm{opt}}={\displaystyle \frac{1}{3{\omega }_H{L}_4{C}_{\mathrm{ox}}{R}_s}}\hfill \end{array}$$

(10)

This configuration’s noise factor is determined by the following formula:

$$F=1+\gamma g_m{R}_s{\left({\displaystyle \frac{{\omega }_0}{{\omega }_T}}\right)}^2$$

(11)

The minimum noise figure of this topology can be low.

• Transit or cutoff frequency: ${\omega }_T={\displaystyle \frac{g_{m_3}}{C_1+C_{gs3}+2C_{gd}}}$.
• Transconductance: $g_m$.
• Total effective input capacitance: $C_T=C_1+C_{gs3}+2C_{gd}$.
• Drain current: $I_d$.

3.3. Gain Analysis

The suggested wideband LNA includes a CS-CG cascaded gain-boosting stage. Decoupling the two stages, evaluating the gain of each stage separately, and then calculating the overall gain allows for the completion of the gain analysis. The first stage’s gain can be calculated by using the formula

$$A_{V1}=g_{m1}(1-\alpha )Z_{L1}$$

(12)

where

$$\begin{array}{cc}\hfill \alpha & ={\displaystyle \frac{s{C}_{gs1}p+s{C}_{gd1}{g}_{m1}}{pq+s{C}_{gd1}(g_{m1}-s{C}_{gd1})}}\hfill \\ \hfill Z_{L1}& ={\displaystyle \frac{1}{s(C_{db1}+C_{g3})}}\hfill \\ \hfill p& =\left({\displaystyle \frac{1}{Z_{L1}}}+s{C}_{gd1}\right)\hfill \\ \hfill Z_{G1}& =(s{L}_1+R_{L1})\Vert \left({\displaystyle \frac{1}{s{C}_{gb1}}}\right)\hfill \\ \hfill q& =\left({\displaystyle \frac{1}{Z_{G1}}}+s{C}_{gs1}+s{C}_{gd1}\right)\hfill \end{array}$$

We must apply the superposition concept to examine the second stage’s gain. The CS-CG stage is depicted in Figure 8b,c, where the gain block A_V1 represents the input CG-stage’s gain. Let A_V2 and A_V3 represent the gain from the gate of M₂ and M₃ to the output; then, (13) and (14) provide A_V2 and A_V3, respectively.

$$A_{V2}={\displaystyle \frac{g_{m2}{Z}_{L3}}{1+g_{m2}{Z}_{dg3}}}$$

(13)

$$\begin{array}{cc}\hfill \mathrm{where}{Z}_{dg3}& ={\displaystyle \frac{1}{s{C}_{sb2}}} \Vert \left(s{L}_4+{\displaystyle \frac{1}{s{C}_{db3}+s{C}_{gd3}+\frac{1}{r_{03}}}}\right)\hfill \end{array}$$

$$A_{V3}=\left({\displaystyle \frac{g_{m2}{Z}_{L3}}{g_{m2}+s{C}_{sb2}+s{C}_{gs2}}}\right)\left({\displaystyle \frac{g_{m3}}{1+s{Z}_3{C}_{db3}}}\right)$$

(14)

$$\begin{array}{cc}\hfill \mathrm{where}{Z}_3& =s{L}_4+{\displaystyle \frac{1}{s{C}_{sb2}+s{C}_{gs2}+g_{m2}}}\hfill \\ \hfill Z_{L3}& =(R_{L3}+s{L}_3) \Vert \left({\displaystyle \frac{1}{s{C}_{db2}}}\right) \Vert Z_L\hfill \end{array}$$

Z_L is the impedance of the load (mixer or variable gain amplifier (VGA)) connected to the LNA.

The LNA’s total gain is

$$A_V=A_{V1}·A_{V2}+A_{V3}$$

(15)

The total forward power gain, as shown in Figure 9a, indicates the larger gain, which means that the output power is hundreds of times larger than the input power. And the reverse power gain in Figure 9b demonstrates good reverse isolation with only a small amount of signal leaking backward. So, this LNA does a great job of blocking the reverse signal flow.

3.4. IIP3

One crucial characteristic that reflects the linearity of the amplifier is the input-referred third-order intercept point (IIP3) of an LNA. It stands for the fictitious input power level at which the basic signals’ power and the power of the third-order inter-modulation products are identical. A higher IIP3 value denotes a better linearity and less distortion, both of which are essential for preserving the signal integrity. For many contemporary applications, particularly in cellular and wireless communication, an IIP3 of approximately +5 dBm or greater is generally preferred. The input-referred third-order intercept point (IIP3) is shown in Figure 10. One tone was selected to test the IIP3 of the LNA. The IIP3 was found to be 21.1537 dBm, as shown in Figure 10.

3.5. Stability Analysis

Based on the input and output reflection coefficients, the stability factor—often denoted as K, or Rollet’s stability factor—is used to determine whether an amplifier is unconditionally stable, conditionally stable, or perhaps unstable. To operate reliably, a larger stability factor denotes an improved resilience to oscillations. The stability factor Kf can be calculated using the following formula:

$$K_f={\displaystyle \frac{(1-|S_{11}{|}^2-\left|S_{22}{|}^2\right)}{|S_{12}·S_{21}|}}$$

(16)

As the value of Kf = 10 > 1 and the B1f value > 0, as shown in Figure 11a,b, this indicates an unconditional stability, meaning that the amplifier is stable within a specific range of impedances, necessitating careful design considerations.

3.6. Designed LNA with Attenuator

Several traditional attenuators with series and shunt resistance adjustments use T and bridged T topologies. By controlling the FET switches, the attenuator experiences the least attenuation when the series resistance is minimal and the shunt resistances are large. In this scenario, the series switch’s nonzero on-resistance is the only source of the loss at the lowest frequencies. The insertion loss resulting from the attenuator’s minimum insertion decreases as this resistance decreases [22,23,27]. The parasitic capacitors introduce greater loss to the ground at higher frequencies; hence, reducing these capacitors lowers the insertion loss. Similarly, when the T-attenuator is set to minimal gain, the shunt component is off and the series components are fully on. In our analysis, $\pi$-topology displayed a wider frequency response when compared to T-topology. Furthermore, there was a trade-off between greater impedance matching and T-topology attenuator attenuation. Figure 12 displays the schematic of the suggested variable attenuator with the designed LNA. Five successive phases make up its single-stage $\pi$-topology. Transistors (M_15,18/M_16,17) and resistors (3R/10R) were employed in two shunt branch pairs to enhance the attenuator’s input/output impedance matching. We used an S-parameter simulation to optimize the parameter; the gate width of each FET switch was set to 2 $\mu$m, and the resistance value R was set to 10 $\Omega$ [22]. The component values of the attenuator with the T-matching network in the input side of the LNA are shown in

Table 3. Component values.

Aspect ratio	(W/L)8 ∼ (W/L)19
	2$\mu$/100n
Inductor (nH)	$L_5$
	1
Capacitor (pF)	$C_4$	$C_5$	$C_6$	$C_7$
	5	0.9	0.04	1.1
Resistor ($\Omega$)	$R_8$	$R_9$	$R_{10}$	$R_{11}$	$R_{12}$	$R_{13}$
	12	8	4	2	1	5
	$R_{14}$	$R_{15}$	$R_{16}$	$R_{17}$	$R_{18}$	$R_{19}$
	5	3	10	10	3	1.04 × 103

.

3.7. Gain Analysis of Designed LNA with the Attenuator

With a straightforward shift register control bit V_c and V_c’, where V_c’ is the complementary of Vc, the designed attenuator offers attenuation ranging from 15.97 dB to 22.70 dB. The attenuation stages reached a lesser attenuation state from 15.97 dB to 22.70 dB when the transistors M₁₆ and M₁₇ were turned on, that is, when V_c was low and V_c’ was high. Likewise, the transistors of the five stages exhibited a higher attenuation condition from 16 dB to 22.52 dB when M₁₅ to M₁₈ were turned on (V_c is high and V_c’ is low). The incorporated variable gain amplifier facilitates effective gain control through digitally programmed step adjustments ranging from 0.4 to 3.3 dB; however, the step uniformity is affected by CMOS FET switch parasitics and finite resistor values. The resulting dB linearity error is recognized as a current design limitation, with future work aimed at mitigating this effect through linearization techniques. Six digital control voltages were used in the suggested attenuator [22]. The digital control voltage combinations to choose the attenuation state are displayed in

Table 4. The gain of the LNA with the attenuator.

Control bias (H for high, L for low)
${\mathbf{V}}_{\mathbf{1}}$	${\mathbf{V}}_{\mathbf{2}}$	${\mathbf{V}}_{\mathbf{3}}$	${\mathbf{V}}_{\mathbf{4}}$	${\mathbf{V}}_{\mathbf{5}}$	${\mathbf{V}}_{\mathbf{C}}$	${\mathbf{V}}_{\mathbf{C}}^{\prime }$	${\mathbf{S}}_{\mathbf{21}}$(dB)	${\mathbf{S}}_{\mathbf{11}}$(dB)	${\mathbf{S}}_{\mathbf{22}}$(dB)	${\mathbf{S}}_{\mathbf{12}}$(dB)
H	L	L	L	L	H	L	16	−7.2	−18.4	−72
H	H	L	L	L	H	L	19.3	−9.6	−18.1	−68.4
H	H	H	L	L	H	L	20.97	−11.4	−18	−66.8
H	H	H	H	L	H	L	21.9	−12.8	−17.95	−65.9
H	H	H	H	H	L	L	22.5	−14.03	−17.9	−65.3
H	H	H	H	H	L	H	22.7	−13.5	−17.86	−65.2
H	H	H	H	L	L	H	22.2	−12.3	−17.91	−65.9
H	H	L	L	L	H	L	21.2	−11	−18	−66.8

and the performance summaries of the proposed LNA and a comparison to previously reported wideband LNAs are displayed in

Table 5. Performance summaries of proposed LNA and comparison to previously reported wideband LNA.

Ref.	Performance Type	CMOS Tech. (nm)	${\mathit{V}}_{\mathbf{supply}}$	Noise Figure (dB)	S21 (dB)	Freq. BW (GHz)	S11 (dB)	IIP3 (dBm)
This work (without attenuator)	Simulated	90	1.2	2.715	29.25	6.4 to 8.4	−20.3	21.154
This work (with attenuator)	Simulated	90	1.2	9.488	15.97 to 22.7	6.4 to 8.4	−13.5 to −7.1	–
[5]	Measured	130	1.8 V	2.2	17	0.05 to 0.83	<−8.9	−6.3
[7]	Measured	180	1.8 V	2.8–3.4	16.1	0.1–1.4	<−9	13 to 18.9
[9]	Measured	65	1.5 V	3.5–4.2	8.6–10.4	0.4–10.6	<−11	7.6 at 400 MHz
[13]	Measured	180	1.8 V	6	13	2 to 5	<−10	−9.5
[14]	Measured	90	1.2 V	1.5 and 2.48	11.2 to 12.4	1.575 to 2.4	−25.3 to −21.4	−3.12 to −2.14
[15]	Measured	180	1.8 V	3.1–5.7	15.9–17.5	3.1–10.6	<−9	-
[28]	Measured	180	1.8 V	max 24.5 and min 6.1	6 to 24	DC—4	<−10	–

.

4. Post-Layout Simulation Results and Discussion

Figure 13 shows the annotated 90 nm CMOS layout of the proposed VGA–LNA (CG input, CS gain, $\pi$-attenuator, bias, and buffer), routed on upper metals with wide straps, dense via stacks, under-pass-shielded top-metal spirals, common-centroid MIMs, and deep-n-well/guard-ring isolation. The DRC/LVS are clean, and the post-layout SpectreRF results used PEX with EM-extracted passives. Figure 14 plots the EM-derived inductor $Q\left(\omega \right)$ for L1–L4, showing $Q\approx 10$–15 across 6.4–8.4 GHz; these profiles explain the $<\pm 0.8$ dB gain ripple (shunt peaking from L3/L4), the small NF penalty from L2 series loss, and the best $S_{11}$ near the Q peak (∼7.6 GHz). Post-layout, the peak-gain shift was $<2\%$, the stability remained unconditional ($K>1$, $B_{1f}>0$), and a $\pm 10\%$ Q sweep changed $|S_{21}|$ by <0.35 dB and the NF by <0.2 dB, with $S_{11}<-15$ dB, confirming that the reported metrics are layout-realizable. The post-layout simulations were performed using Spectre RF from the Cadence design suite. For the performance analysis, we examined the SP analysis, which showed the circuit’s performance at specific points. The S parameters $S_{11}$, $S_{21}$, $S_{22}$, and $S_{12}$ provide insights into the circuit’s gain condition. Over a bandwidth of 6.4–8.4 GHz, there was a high level of agreement between the simulated and calculated values.

The design shows that the gain may be varied from 28.85 dB at higher feet to 25.24 dB at lower feet before using an attenuator on the input side. The nearly 2 dB bandwidth spans and includes the lower (6.4 GHz) and higher (8.4 GHz) transit frequencies. Plots of the input return loss ($S_{11}$) and output return loss ($S_{22}$) for the upper and lower feet are shown in Figure 15 and Figure 16b,c. $S_{11}$ for both standards stayed well below −14 dB over the entire bandwidth. The simulated plots in Figure 15 demonstrate that the higher-ft design achieved a noise figure of 3 dB, while the lower-ft design reached 2.159 dB. Our developed circuit’s gain can be easily verified from 15.97 dB to 22.7 dB over an acceptable range of bandwidth by adding an attenuator to the input side. Throughout the whole bandwidth, $S_{11}$’s value was also less than −17 dB. Both $S_{11}$ and $S_{22}$ have values of −13.52 dB and −17.86 dB, respectively, at the cutoff frequency of 7.6 GHz. For the constructed circuit, the value of $S_{12}$, which primarily measures the reverse gain, was determined to be −65.24 dB. Figure 17 illustrates the suggested design’s noise performance. The bottom band attained a noise figure of 3.14 dB, whereas the top band obtained a noise figure of 2.72 dB, according to the simulated plot in Figure 17. A power increase of $S_{21}$ 29.28 dB was obtained at the operating frequency of 7.6 GHz with a 1.2 V power supply in Figure 16a. At 7.6 GHz, the LNA’s input return and output return losses ($S_{11}$, $S_{22}$) were $-20.31$ dB and $-18.01$ dB, respectively. The reverse isolation ($S_{12}$) was $-58.78$ dB in Figure 16d, which can be attributed to the use of a cascaded structure.

A comparison was made between the noise values in the LNA arrangement with and without an attenuator simulation. With the gain shown in Figure 17, the noise figure in the LNA configuration without attenuator simulation was maintained below 3 dB across the whole band. In the simulation of an LNA with an attenuator and a gain of 22.18 dB, the noise figure was less than 9.4 dB. The elevated NF was primarily due to MOSFET switch parasitics and impedance mismatches. The noise figure varied by around 0.3 dB at the low-frequency end and by 1.2 dB at the high-frequency end of the band when the gain fell to 15.98 dB. As a result, variable gain was obtained without a significant deterioration in the noise performance. It is important to note that the integration of the attenuator introduced additional parasitic effects, primarily due to MOSFET switch resistance and capacitor loading, which resulted in an elevated noise figure compared to the stand-alone LNA. While the core LNA achieved an NF $\le 3.14$ dB, integration with the attenuator increased the NF to approximately 9.4 dB. This degradation is consistent with the expected contributions from switch thermal noise and impedance mismatch at the input network. Nevertheless, simulation studies suggest that incremental design refinements—such as reducing MOSFET switch dimensions and optimizing resistor ratios—can locally improve the NF performance toward ∼6 dB, thereby moving closer to the stringent requirements of C-band medical WBAN applications. These results highlight a clear pathway for further optimization without fundamentally altering the proposed architecture. Using the simulation calculator tool, we calculated the power dissipation of only the LNA, which was 83 mW; with the attenuator, the value became 83.4mW, which is desirable.To address process and mismatch variability, we performed SpectreRF Monte Carlo (process+mismatch, N = 500) on the proposed VG-LNA in Cadence Virtuoso. The outputs were |$S_{21}$|, the NF, and $S_{11}$ extracted at 7.6 GHz using SP/NF analyses; IIP3 was evaluated with a two-tone QPSS/PAC setup on a reduced sample due to runtime. The yield was computed against $|S_{21}|\ge 28\mathrm{dB}$, an $NF\le 3.14\mathrm{dB}$ (no attenuator), and $S_{11}\le -15\mathrm{dB}$. The post-layout robustness was evaluated across process–voltage corners (SS@1.08 V, TT@1.20 V, FF@1.32 V) and temperatures (−40 °C, 25 °C, 85 °C) over 6.4–8.4 GHz. The forward gain $|S_{21}|$ remained tightly controlled, ranging from ≈28 to 30.5 dB with a sub-dB ripple at the TT corner (see Figure 18a,d). Input matching was consistently good, with $S_{11}<-17$ dB in the worst corner and approaching $-20$ dB at TT/FF near 7.6 GHz (Figure 18b,e).

The noise figure tracked the expected $g_m$ and passive-Q variations, staying within 2.7–3.2 dB across the PVT and temperature (Figure 18c,f). With increasing temperature, a slight gain reduction and a small $S_{11}$ degradation were observed, while FF showed the best NF and SS the worst, as anticipated. These results confirm that the VGA–LNA maintains its target gain, matching, and NF across realistic manufacturing and operating conditions, supporting the stability and margin reported in the preceding subsections. Histograms and yield plots are shown in Figure 19.

Table 5 presents a comparative analysis between the proposed design and other state-of-the-art wideband CMOS LNAs. Compared to [13], which was implemented in the same 90 nm CMOS technology, the proposed design achieved an improvement of more than 10 dB in the forward gain (|$S_{21}$|) and an over 20 dB enhancement in IIP3, and it offers a variable gain range exceeding 7 dB. From Table 5, it can be seen that, while prior designs in similar bandwidth ranges ([9,13,15]) achieved a reasonable NF and bandwidth, they are generally limited in forward gain (≤18 dB) and lack variable-gain programmability. Our proposed VGA–LNA not only provides a substantially higher gain (∼29 dB), but it also offers a digitally controlled $7\mathrm{dB}$ tuning range and an excellent linearity (IIP3 $\sim +21.15\mathrm{dBm}$). These distinctions underscore the novelty and significance of the proposed architecture for medical WBAN applications operating in the 6.4–8.4 GHz band.

5. Conclusions

This work presented a wideband VGA-LNA designed in 90 nm CMOS technology using a CG–CS architecture with an integrated attenuator, achieving up to a 22.7 dB gain and dynamic step-controlled tuning. The standalone LNA demonstrated an excellent performance with an NF $\le 3.14$ dB, while the integration of the attenuator increased the NF to 9.4 dB due to MOSFET switch parasitics and an impedance mismatch. Although this degradation is expected, the design maintains competitive gain and linearity for C-band medical WBAN systems. Moreover, incremental optimizations—such as switch resizing, resistor ratio refinement, and advanced noise-cancellation techniques—are expected to lower the NF toward ∼6 dB, with future work targeting an NF < 4 dB through improved attenuator topologies. Overall, the simulation results validate the feasibility of this compact, tunable, and power-efficient architecture, highlighting its potential for next-generation biomedical and wireless body area network applications.