Search Results (569)

Capacitive sensors implemented in complementary metal-oxide-semiconductor (CMOS) technology are widely used in lab-on-chip (LoC), biomedical, and microfluidic systems. While most capacitive sensor interfaces are designed for high-resolution capacitance quantification, many practical applications require only binary decisions, event detection, or state discrimination. In such scenarios, conventional readout architectures introduce unnecessary circuit complexity, power consumption, latency, and data-processing overhead. This paper presents a CMOS cross-coupled-based capacitance detector (CBCD) that directly converts the imbalance between a sensing capacitance and a reference capacitance into a digital output. By exploiting regenerative positive feedback in a dynamic latch architecture, the proposed detector integrates sensing, comparison, and digitization within a single stage, eliminating the need for analog amplification, analog-to-digital conversion, frequency-based readout, and external thresholding circuitry. Circuit-level simulations show the ability to detect extremely small capacitance differences, demonstrate robust operation across a wide range of input capacitances, and achieve negligible power consumption. Process-corner, noise, and Monte Carlo analyses further verify reliable operation in the presence of device mismatch and process variations. Owing to its compact structure, digital-native output, and energy-efficient operation, the proposed CBCD is well suited for decision-driven sensing applications, including droplet presence detection, bubble monitoring, threshold-based diagnostics, event detection, and time-of-evaporation (ToE) measurements. The proposed architecture provides a scalable and low-complexity front-end solution for next-generation CMOS-integrated sensing platforms. Full article

The increasing computational demands of artificial intelligence (AI) inference at the edge require hardware accelerators capable of overcoming the von Neumann bottleneck while operating under power constraints. Conventional digital architectures based on multiply–accumulate (MAC) units are limited in energy efficiency and scalability for resource-constrained applications. This work presents a proof-of-concept AI accelerator based on analog frequency–domain computation implemented within a semi-systolic array architecture. The proposed approach exploits frequency mixing to perform multiplication and accumulation operations in hardware, enabling the execution of matrix–matrix operations, which constitute the General Matrix Multiplication (GEMM) methods that dominate the computational workload of convolutional and fully connected neural networks. The proposed system consists of a custom printed circuit board controlled by an ATmega328P microcontroller(Microchip Technology Inc., Chandler, AZ, USA) and a software stack designed to interface with standard machine learning frameworks such as PyTorch. The software layer enables neural network operations, including convolutional and fully connected layers, to be mapped onto hardware-executed matrix–matrix computations through an abstraction analogous to the General Matrix Multiplication (GEMM) functionality provided by Level-3 Basic Linear Algebra Subprograms (BLAS). Matrix multiplication and accumulation are partly performed directly by the hardware processing elements, while the software control unit coordinates data movement and computation scheduling. Although bias operations are not implemented in the current prototype, their comparatively low computational cost makes them less critical to the overall acceleration strategy. A quantization-aware mapping methodology constrained by analog-to-digital and digital-to-analog converter specifications is introduced to translate neural network operations into frequency–domain computations. The paper further describes the hardware architecture, communication protocols, software stack organization, and interactions between system components. In addition, the effects of analog nonidealities and error sources associated with frequency–domain multiplication are investigated, and simulations of the proposed processing elements are presented to evaluate the computational approach. Experimental and simulation results demonstrate the feasibility of performing dense linear algebra operations through analog frequency–domain processing and validate the operation of the processing elements. The study further explores converter resolution, frequency interference, and analog component nonidealities and provides a comparison with conventional digital and other low-power accelerator approaches. The results indicate that exploiting the inherent parallelism of analog computation offers a promising pathway toward ultra-low-power AI inference, making the proposed architecture a potential alternative for energy-constrained edge applications. Full article

Transimpedance amplifiers (TIAs) are the critical components for current-to-voltage interfaces in optical receivers, LiDAR front-ends, biomedical sensors, and unconventional applications such as magnetic-resonance receiver-coil arrays and wide-bandgap ultraviolet detectors, and their CMOS design is governed by a fundamental gain-bandwidth-noise trade-off whose structure is rarely made explicit. This review introduces a unifying framework rooted in three explicit assumptions underlying the classical shunt-feedback TIA limit: a single-pole core amplifier (A1), a resistive feedback element (A2), and the full input capacitance loading the feedback summing node (A3). Relaxing one or more of these assumptions is shown to be the common structural thread behind every class of bandwidth or noise enhancement in the recent literature, and all surveyed architectures are organized into a six-tier taxonomy, from Tier 0 designs operating within the classical limit to Tier 5 topologies that bypass all three assumptions simultaneously. This taxonomy is supplemented by an orthogonal configurability axis spanning single- and dual-control reconfigurable, variable-gain, and dynamic-range-extension designs. We further show that stability is not removed by these relaxations but migrates with the tier, from the global phase margin of the classical loop to a local regulating loop, a group-delay-flatness constraint, an input-passivity condition, or a multi-loop interaction, so that each architecture carries a predictable stability locus. The taxonomy is cross-referenced with application domains and closed-form noise-floor boundary plots parametrized by input capacitance and amplifier gain-bandwidth product, and with the CMOS technology landscape, where we argue that the most advanced node is not universally optimal and that node and topology act as complementary rather than competing levers. A single consistent figure of merit, applied uniformly to a representative set of CMOS realizations from 0.6 $\mathsf{\mu }$m to 16 nm FinFET, shows no monotonic improvement with publication year or node and is presented as a diagnostic indicator rather than an absolute ranking. The review closes with an outlook on 200 Gb/s/lane links, wide-bandgap sensor integration, and the FinFET-to-gate-all-around device transition. Full article

A 128-stage high-precision analog accumulator is proposed for TDI-CMOS image sensors, incorporating a decoupling capacitor multiplication technique and a noise sampling compensation circuit. The proposed decoupling capacitor multiplication technique enlarges the effective decoupling capacitance while reducing the required layout area, thereby suppressing parasitic effects during high-stage accumulation. A noise sampling compensation circuit is further employed to reduce accumulated circuit noise and improve the signal-to-noise ratio (SNR). The proposed accumulator is designed and verified using a 55 nm standard CMOS process. Post-layout simulation results indicate that the proposed design achieves a 20.945 dB SNR improvement under 128-stage accumulation, with the effective accumulation stage count approaching the ideal value. The total layout area is 4.711 mm × 88.43 mm. The proposed design demonstrates a potential approach for implementing compact, low-noise, and high-stage analog accumulators for TDI-CMOS image sensors. Full article

This paper presents an electronically tunable first-order universal filter capable of operating in multiple analog modes, realized through a compact architecture built around multiple-input operational transconductance amplifiers (MI-OTAs). By leveraging the MI-OTA’s ability to accommodate several input signals within a single transconductance stage—allowing direct arithmetic operations such as summation and subtraction—the proposed design minimizes the number of active elements traditionally required for mixed-mode filtering. Consequently, both inverting and non-inverting forms of low-pass, high-pass, and all-pass responses can be generated in voltage mode, current mode, transadmittance mode, and transimpedance mode, enabling a total of 24 distinct first-order transfer functions using one unified circuit topology. The pole for all responses can be conveniently adjusted by electronically tuning the OTA transconductance. The multiple-input capability is realized using a multi-input MOS technique, while subthreshold-biased bulk-driven transistors allow the circuit to function from a 0.5 V supply with an extended input voltage range and ensure ultra-low power dissipation. The filter was designed and evaluated in Cadence Virtuoso using a 65 nm TSMC CMOS process. Under a 7 nA bias current, the low-pass configuration achieves a consumption of 87.5 nW and a dynamic range of 44.7 dB. Additionally, experimental verification was performed using the commercial LM13700 OTA, confirming the correct operation and practicality of the proposed approach. Full article

Micro-Unmanned Aerial Vehicles (micro-UAVs) require compact radar arrays under severe Size, Weight, Power, and Cost (SWaP-C) constraints. Spread Spectrum Digital Beamforming (SSDBF) reduces receiver hardware by multiplexing multiple antenna channels before a shared RF chain, but the receiver-side switching operation folds wideband noise and injects switch-related transient noise before digital demultiplexing. This paper develops a hardware-waveform co-design framework that links the transition density of bipolar spreading sequences to high-frequency code energy and switching-event count, while explicitly distinguishing modulation-induced thermal-noise folding from switch-transient injection. Transition density is used as a physically interpretable design surrogate rather than a sufficient statistic for folded noise, and it is constrained jointly with non-zero-shift cross-correlation to preserve spatial isolation under receiver-side timing skew. An $ϵ$-constrained Greedy Coordinate Space Search ($ϵ$-GCSS) algorithm is proposed to synthesize low-transition-density SSDBF code sets. Commercial circuit-level transient simulations and system-level MATLAB R2024b simulations show that the proposed code set reduces the PRN-like transition-density level from about $0.50$ to about $0.19$, lowers the circuit-simulation-derived integrated IF noise power by $9.63$ dB relative to the Gold/PRN-like baseline, and improves the normalized maximum detection range by $8.2$ percentage points at $K=4$ without adding analog front-end hardware. Full article

To address the issues of high customization, long development cycles, and excessive power/volume in radio frequency (RF) transceiver modules for Synthetic Aperture Radar (SAR) and radar systems, this paper presents an ultra-compact universal RF transceiver module design based on a full application-specific integrated circuit (ASIC) architecture. Centered on a wideband RF System-on-chip (SoC) and a reconfigurable digital SoC, the module integrates the complete RF transceiver chain—including filtering, amplification, mixing, Analog-to-Digital/Digital-to-Analog Converter (ADC/DAC) conversion, digital preprocessing, and high-speed data transmission. Test results demonstrate that the 8-channel module achieves a 53.1% area reduction and 55.1% lower power consumption (only 40.9 W) compared with conventional architectures, while all key RF specifications meet system requirements. The proposed solution improves upon existing limitations in high integration, low power, and generality, offering a low-cost, rapid-development technical route for transceiver modules in radar and communication applications. Full article

Low-power CMOS image sensors increasingly rely on approximate analog front-end designs, including reduced ADC precision, relaxed voltage swing, and noise-tolerant readout circuits, to reduce energy consumption in always-on edge vision systems. However, the acceptable degradation boundary of such analog front-ends remains unclear when sensor outputs are consumed by downstream spatial perception workloads rather than conventional image-quality metrics. This paper presents a task-aware system-level evaluation framework for approximate CMOS image-sensor analog front-ends. We parameterize key circuit-level non-idealities, including ADC bit-depth reduction, temporal read noise, gain and offset variation, fixed-pattern noise, and dynamic-range clipping, and we evaluate how these impairments propagate through semantic, geometric, mapping, and spatial decision workloads. Across 10,500 end-to-end evaluations and 1996 geometric mapping trials, we identify a strong non-linear error cascade: semantic free-space extraction remains tolerant to aggressive quantization, whereas monocular depth and visual odometry impose much stricter analog front-end requirements. The results show that read noise and offset errors are the dominant failure sources for geometric perception, while controlled voltage swing clipping at 0.8 V can reduce front-end energy without degrading, and in some cases slightly improving, downstream reliability by suppressing high-intensity outliers. The analysis provides quantitative design boundaries for low-power CMOS image-sensor front-ends, including task-specific ADC precision, read-noise tolerance, voltage swing, PGA bypass, and offset calibration requirements. Full article

Wireless communication above $300\mathrm{GHz}$ requires highly sophisticated analog circuit design due to severe frequency dependent ohmic losses. The complexity of such electronic hardware motivates exploring wireless quantum optical communication approaches even for the 6G “terahertz (THz) range” $\left[300\mathrm{GHz},10\mathrm{THz}\right]$. In this work, the classical radio frequency (RF)-based inner physical layer (PHY) transceiver blocks of channel coded wireless communication systems are replaced by wireless quantum optical transceiver blocks. Short range concepts employing LEDs as transmitters are particularly attractive, owing to their low implementation cost and practical simplicity. In contrast to laser based wireless quantum optical transmission over multipath channels, the quantum mechanical density operator ${\underline{\mathit{\rho }}}_{\mathrm{RX},[{\mathfrak{s}}_i,b_i]}$ and the transition probability $\gamma ({\mathfrak{s}}_i,{\mathfrak{s}}_{i+1})$ required by the quantum data detection must be revised accordingly. Furthermore, the novel interpretation introduced here, in which the extrinsic information is treated as a diversity branch rather than as an estimate of the a priori information, facilitates turbo equalization that still can accomodate varying a priori information. However, due to the limited uncoded transmission performance achievable with such systems, the incorporation of sophisticated channel coding schemes appears imperative. The authors therefore investigate the combination of sophisticated channel coding techniques, such as polar coding, with LED based wireless quantum optical transmission technologies. All numerical results assume a cryogenically cooled receiver front-end (approximately 10 K), yielding thermal noise levels. Operation at room temperature in the 6G THz range $\left[300\mathrm{GHz},10\mathrm{THz}\right]$ would require an average number ${\overline{N}}_{\alpha }$ of thermal noise photon values of approximately 5 to 20, which is beyond the scope of this feasibility study. The results show that the proposed paradigm enables simple, robust, and practically viable wireless quantum optical communication systems with favorable transmission performance. Additional gains are achieved through iterative turbo equalization. The results also suggest that the proposed approach can pave the way toward robust and economically viable future communication solutions. Full article

Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance quantization, and device nonlinearity. This paper presents a differential mixed-signal architecture for accurate signed matrix–vector multiplication (MVM), integrated with a RISC-V microcontroller for edge inference applications. A structured digital-to-analog mapping framework encodes quantized neural network weights into programmable conductance values while preserving arithmetic correctness. The design employs voltage-mode input encoding, differential current summation, and transimpedance-based readout followed by analog-to-digital conversion, enabling single-cycle signed accumulation without duplicating crossbar resources. A 32 × 16 dual-layer prototype crossbar was fabricated and experimentally characterized. Measurements demonstrate a mean absolute percentage error (MAPE) below 1% within the linear operating region and below 4% over the full-scale conductance range. These results validate the robustness of the proposed mapping methodology and confirm the feasibility of hybrid analog–digital acceleration for edge AI systems. Consequently, this discrete prototype serves as a physical verification platform for the AIMC approach, providing valuable insights for more efficient mixed-signal computing integrated circuit (IC) designs. Full article

As the requirements in fields such as automobile, high-frequency signal generation, and medical applications, the resolution of time-to-digital converters (TDCs) has been pushed to the picosecond and sub-picosecond levels. In this study, a Vernier TDC was investigated with a time resolution less than the signal transition in the circuit. As generally happens in TDCs or Analog-to-Digital Converters (ADCs), bubble errors are found to degrade the resolution of their output codes. The bubble errors are usually attributed to non-idealities and mismatches in the circuits. Since the input time difference in high-resolution TDCs is much smaller than the signal transition time with the existence of bubble errors, it is an issue to determine the corresponding thermometer code from the output bit string of interleaved 0 s and 1 s. In our exploration, a Xilinx FPGA was employed to implement a Vernier Delay Line (VDL) for the TDC. In this timing-sensitive design, the timing difference between the two paths mainly comes from the interconnects rather than the Look-Up Table (LUT) devices. Timing constraints and regular placement were also imposed in addition to the simple Register Transfer Level (RTL) codes. Since the nature of uncertainty, a statistical model was proposed to analyze the output bit patterns. Three methods were employed to determine the output thermometer code. The first would count the total number of 1 s in the output. The second is to detect the position of the last 1. And the third is to detect the first 0 in the output bit string. The obtained results showed that these three methods were almost equivalent in the statistical outputs. The time resolution of our FPGA-based VDL can be around 5 ps in our measurement. According to our model, the transition time in the FPGA circuit was estimated as 100 ps. This result is reasonable for a chip made of 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. For the study of the linearity of our VDL, its differential nonlinearity (DNL) was less than ±2 LSB. The code-density-like analysis also shows the nonlinearity of this VDL. It was also found that the methods detecting the last 1 and the first 0 were sensitive to bit failures. In summary, for this study, it is confirmed that the three conversion methods are equivalent, and we found that detecting the last 1 or the first 0 was sensitive to bit defects or mismatches. Full article

The rapid growth of artificial intelligence (AI) workloads is reshaping semiconductor design across architecture, interconnect, memory hierarchy, packaging, timing, and design automation. Rather than converging on a single hardware solution, the field is expanding into a heterogeneous ecosystem that includes data-center graphics processing units (GPUs), edge neural processing units (NPUs), and application-specific integrated circuits (ASICs), field-programmable gate array (FPGA)-based and hybrid AI system-on-chip (SoC) platforms, chiplet-enabled systems, and emerging beyond-conventional-silicon approaches such as photonic, neuromorphic, and analog in-memory processors. This paper presents a comprehensive review of AI-on-chip systems from a cross-layer perspective. It examines AI chip architectures and hardware platforms, network-on-chip (NoC) designs for AI communication patterns, and algorithm–hardware co-design methods for model acceleration, including compression, quantization, and sparsity-aware optimization. It also reviews clocking, synchronization, and clock-domain-crossing (CDC) challenges in large heterogeneous systems and chiplets, as well as manufacturing, advanced packaging, and reliability issues, including two-and-a-half-dimensional (2.5D) and three-dimensional (3D) integration, thermal and mechanical constraints, assembly quality, and long-term yield considerations. In parallel, the paper surveys the growing role of AI in chip design itself, covering machine-learning-assisted analysis, Bayesian and reinforcement-learning-based optimization, and the emerging use of large language models (LLMs) and AI agents for register-transfer level (RTL) generation, design-space exploration, and autonomous electronic design automation (EDA) workflows. Finally, it discusses beyond-silicon AI chip directions and the broader economic and industry context shaping cloud, on-premises, and edge deployment. By integrating these topics into a unified framework, this review highlights the key technological drivers, system-level tradeoffs, and future research directions that will define next-generation scalable, reliable, and energy-efficient AI-on-chip systems. Full article

Flexible strain sensors have attracted considerable attention in gait recognition owing to their ability to adhere directly to the skin near joints and transduce local deformation. In existing work, however, sensor placement and orientation are largely determined by anatomical experience, while multi-channel classification still relies on back-end digital processors, whose power consumption and latency constrain system practicality in wearable scenarios. This paper presents an integrated design path that proceeds from skin-mechanics theory through sensor-layout optimization to analog-domain front-end inference. On the layout side, the lines-of-non-extension (LoNE) theory is employed to convert the selection of sensor attachment angles from empirical judgment into a calculable mechanics problem; guided by the spatial course of LoNE in the ankle and knee regions, the positions and angles of the nine sensors are determined individually—channels perpendicular to the LoNE capture maximum strain, channels offset by 45 degrees supplement non-sagittal-plane information, and a channel aligned along the LoNE provides a near-zero-strain reference. On the circuit side, the mathematical equivalence between the weighted summation of a linear classifier and Kirchhoff’s current law (KCL) nodal current superposition is exploited to map the classification operation onto current aggregation in an analog circuit, yielding an in-sensor computing (ISC) front end in which the nine-channel weighted summation is completed in a single analog step. The sensors are fabricated by screen-printing a liquid-metal–polymer composite conductive ink onto a TPU film substrate, with a gauge factor RSD of $6.8\%$ and a tensile linearity $R^2>0.99$. Using walking, running, and stair descent as verification targets, the analog classifier reaches 99% accuracy at the circuit-level functional-verification stage. On real multi-subject data, it achieves $87.0\%\pm 8.4\%$ accuracy under intra-subject cross-session validation, with an analog-domain inference response faster than $100\mathsf{\mu }\mathrm{s}$. This design path is not bound to a specific joint or sensor material; when the layout methodology is extended to additional joint regions and the circuit architecture incorporates multiple outputs to cover more classification categories, the same workflow remains applicable, offering a promising low-power, lightweight technical solution for wearable motion monitoring. Full article

It has been observed in prior research that high thermal impact—resulting from a large temperature difference between hot water vapor and cold liquid water—can enhance the thermal performance of cavitation-induced low-energy nuclear reactions (LENRs) in water, with an estimated increase in the coefficient of performance (COP) of approximately 50% for every 100 °C temperature rise. The temperature of the hot water vapor is primarily determined by the boiler output, which typically represents the highest temperature source and plays a dominant role in reactor performance. In this study, a flow oscillator was designed as an thermal conditioning component for these potential LENR reactor systems using linear flow network analysis (LFNA) to generate flow resonance that elevates the hot vapor temperature, thereby increasing thermal impact and improving LENR performance. LFNA is based on the linearization of the fluid flow equations governing mass and momentum transport and utilizes a fluid-electric circuit analogy. For a fluid flow system, various components can be modeled using analogs of electrical resistance, capacitance, and inductance (R, C, and L), allowing the system behavior to be analyzed similarly to an RLC circuit. Through this analogy, flow resonance phenomena can be predicted, potentially enabling the generation of high-temperature and high-pressure responses that are beneficial to LENR processes. The analytical model was experimentally validated and subsequently applied in the LENR reactor design. The analytical result shows that an output temperature difference exceeding 350 °C can be achieved using a 0.5 m pulse tube at a 46 Hz triggering frequency with 20 kPa perturbation, which indicates a potential COP enhancement of 175% based on prior studies. The result provides a potential mechanism to significantly enhance the thermal impact conditions and promote LENR performance in water-based reactor systems. Full article

“Spinal cord stimulation (SCS)” is an established therapy for chronic pain and an emerging modality for functional recovery after spinal cord injury (SCI) and other clinical applications. Despite its clinical potential, current implantable SCS systems remain constrained by high power consumption, limited adaptability, device size, and long-term stability. Recent advances in closed-loop neuromodulation and integrated circuit (IC) design are enabling more adaptive, efficient, and miniaturized SCS systems. This narrative review focuses on integrated circuit and system-on-chip (SoC) architectures that enable more advanced closed-loop SCS modalities, including stimulation, sensing, and wireless power/data subsystems. Specifically, the present work examines stimulation drivers and charge-balancing circuits that ensure safe and precise current delivery, wireless power transfer, telemetry methods which maintain reliable energy and data flow in implanted systems, and analog front-end circuits that enable closed-loop biopotential monitoring for adaptive feedback control. It aims to highlight innovations in IC design, energy harvesting, and wireless communication strategies while discussing trade-offs in power efficiency, die area, thermal limits, and biocompatibility. Emerging trends emphasize miniaturized and adaptive neural implants that integrate circuit-level efficiency with therapeutic flexibility, thereby advancing the next generation of closed-loop neuromodulation technologies. Ultimately, innovations in microelectronics are paving the way for enhanced long-term efficacy, safety, and clinical applicability of implantable SCS systems to optimize functional impacts. Full article