Multilevel Voltage Source Inverters with Improved Selective Harmonic Elimination Using a PAM-PWM Control Topology ^†

Abstract

Power inverters are extensively employed in a wide range of applications such as VSD, PV, UPS, and Vehicle-to-Grid systems. Different control topologies are used in power electronic inverters. Of these, PWM and MLVSIs are implemented to minimize the harmonic contents of the generated waveforms, as well as to minimize the complexity and cost of these systems. Although PWM inverters offer an acceptable waveform quality, the switching losses of the power elements is considered a major drawback. MLVSIs provide excellent waveform quality at reasonable switching losses, but at the expense of a relatively higher cost and design complexity. However, when applied to constant voltage constant frequency applications such as PV, UPS, and Vehicle-to-Grid systems, the cost and design complexity become reasonable. In this paper, a generalized analytical analysis and solution of an M-Stage MLVSI with a certain selective harmonic elimination (SHE) control topology is reported. This leads to completely eliminate certain lower-order harmonics of the generated waveforms. The number of harmonics that can be eliminated depends upon the number of the system DC link stages. The results show that as the number of stages increases, a significant improvement of the waveform quality is achieved. However, the tendency of this quality to further improve as the number of stages increases is remarkably reduced.

1. Introduction

Power inverters are extensively employed in a wide range of domestic, commercial, and industrial applications. Variable-speed drive AC motors, PV systems, uninterruptable power supplies (UPSs), and, recently, electric vehicles are important practical applications. In UPS and PV systems, the amplitude of the load voltage and its frequency are constant. While the waveform frequency is usually accomplished by the adjustment of the switching pattern of the inverter power switches, the adjustment of the amplitude of the generated voltage waveform is conventionally achieved by one of two ways: variation of the DC input voltage from outside the inverter, specifically by one or more external DC links, and the PWM technique that is conducted within the inverter itself. Different PWM control topologies are well-known; of these, the uniform PWM (UPWM) and the sinusoidal PWM (SPWM) topologies are the most common.

PWM control topology is widely used due to the attractive nature of the harmonic contents of the generated voltage and current waveforms. In this context, selection of the proper modulation frequency f_m, is a key issue. Strictly speaking, a higher ratio of modulation frequency to output power frequency f_o (i.e., f_m/f_o) creates low lower-order harmonics, while the higher-order harmonics (usually odd multiples of f_m/f_o ± 1) are dominant. Therefore, with higher modulation frequency, a relatively cheap and simple filtration requirement is needed. However, as the modulation frequency increases, the switching losses of the power switches increases, a drawback that should be seriously considered. This will limit the range of modulation frequency that can be practically applied, especially as the load power increases. A trade-off between accepted switching losses and reasonable filtration requirements is then seriously considered for proper system design and performance.

Multilevel Voltage Source Inverters (MLVSIs) are increasingly accepted, commonly recommended, and preferred in a wide range of applications, specifically those needing constant voltage and constant frequency waveforms, such as PV and UPS applications. This is simply due to the fact that MLVSIs produce voltage waveforms with superior harmonic profiles at an acceptable switching loss. Such systems can practically be designed and structured using different categories and control topologies. In this context, one can categorize three main structures; diode clamped MLIs (DC-MLIs), flying capacitor MLIs (FC-MLIs), and the cascaded H-bridge MLIs (CHB-MLIs) [1,2].

DC-MLIs with different voltage levels were reported in Ref. [3]. The required number of diodes of this structure is quadratically related to the number of waveform levels. This implies that the higher the number of waveform levels, the higher the number of diodes required, implying that the system design is bulky.

The flying capacitor multilevel inverter FC-MLI was introduced as an alternative structure to the DC-MLI [4,5]. While the main structure of this system is similar to DC-MLI, it uses DC link capacitors in a ladder form instead of the clamping diodes. The most interesting advantages of FC-MLI topology are preventing the filter demand and controlling the active and reactive power flow. However, the cost of this inverter is dramatically increased, and it becomes bulky due to the increased number of capacitors (auxiliary and DC link capacitors). Cascaded H-bridge multilevel inverter CHB-MLI is another alternative topology [6,7,8,9,10]. With CHB-MLI, fewer power devices are required compared to DC-MLI and FC-MLI topologies. This topology is based on the series connection of H-Bridges; each has its own separate but isolated DC source. The AC output voltage is synthesized by the addition of the voltages generated by the different H-bridge cells.

Of the different control topologies, the Selective Harmonic Elimination (SHE) control topology has drawn remarkable attraction of researchers since it works with low switching frequency, which ensures low switching losses. The SHE method is used to eliminate certain dominant lower-order harmonics while retaining the switching frequency of the semiconductor devices at a relatively low value. This also implies that low-cost passive filters can be used to remove higher order harmonics. The basic SHE method is implemented in two ways: SHE through Pulse Width Modulation (SHE-PWM), where the switching angles of the output voltage waveform are optimized to eliminate certain waveform harmonics, and SHE through Pulse Amplitude Modulation (SHE-PAM), where the amplitudes of the DC levels of the output voltage waveform are optimized to eliminate certain harmonics [11,12,13]. In SHE-PWM, harmonic elimination is based on the determination of the optimum switching angles while the voltage levels are multiples of each other. In SHE-PAM, harmonics elimination is based on defining variable voltage levels while the switching angles are fixed throughout the modulation index range. The number of lower-order harmonics that could be eliminated in any control topology depends upon the number of switching angles or voltage levels.

A SHE-PAM-PWM control topology is reported in Ref. [14]. Both the optimal switching angles and the optimal DC voltage levels of the output voltage waveform together are involved in the harmonic elimination process. The number of lower order harmonics that can be eliminated is doubled, implying more controllability and better waveform quality achievements.

The basic mathematical concept of the SHE technique is to formulate a set of nonlinear equations. This set of equations is then solved for pre-determination of the optimal waveform switching angles, or the optimal voltage levels. As the number of switching angles and/or the number of voltage levels increases, the real-time solution of this set of equations becomes increasingly difficult. Different solving techniques and algorithms are widely employed. The Newton–Raphson method is the most popular method [5,14]. Optimizing-based algorithms such as Genetic Algorithm (GA) [15] and Particle Swarm Optimization (PSO) [6,11] are used. With variable-voltage variable-frequency applications, which is required for wide range of applications such as variable-speed drive systems, once the set of equations is solved, a look-up table (LUT) is to be created to hold the entire pre-calculated set of parameters to be used in order for the inverter to achieve the required voltage waveform quality. However, in applications such as the UPS, PV systems, and vehicle-to-home and vehicle-to-grid systems, where the inverter enables the PV system or batteries to supply AC loads at constant voltage and constant frequency, the LUT is no longer needed, leading to simpler system design.

None of the reported research works investigate the optimum number of the DC link stages, and hence voltage levels of the generated voltage waveforms that results in a high-quality waveform at a reasonable system complexity and cost. A system of M-stage DC links is suggested. In this paper, a generalized system analysis is developed, and the generated waveform quality is investigated. The results are expected to be a guideline for inverter designers, especially those inverters involved in UPS and renewable energy systems, where the voltage amplitude and frequency of the generated waveforms are fixed.

2. Power Circuit Configuration and Conduction Patterns

Figure 1 shows the power circuit configuration of the system under consideration. The system consists of four main blocks as follows:

(a)

H-Bridge Inverter: A conventional H-bridge inverter consisting of four IGBT transistor switches T₁–T₄, and four free-wheeling/feedback diodes D′₁–D′₄ to ensure a specific frequency of the generated waveform and to force the output voltage waveform’s zero-voltage levels when required.

(b)

Identical Boost Converters: M identical boost converters, each of which is used to generate a specific non-zero DC voltage level to satisfy the requirement of the output voltage waveform. Q1, D1, C1, and L1 belong to the 1st boost converter, to generate a voltage level $V\left(1\right);$ Q2, D2, C2, and L2 belong to the 2nd boost converter, to generate a voltage level $V\left(2\right)$, and so on up to the Mth stage, where QM, DM, CM, and LM belong to the Mth boost converter, to generate voltage level V(M).

(c)

Time Switching Controller: This part of the circuit is designed to feed the inverter circuit by the boost converters output voltage levels at certain switching angles. D(M + 1) feeds V(1) at an angle $\alpha \left(1\right)$, Q(M + 2) and D(M + 2) feed V(2) at an angle $\alpha \left(2\right)$, and so on up to the Mth stage where Q(M + m) and D(M + m) feed V(M) at $\alpha \left(M\right),\mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e}$ m = 1, 2, 3, … M.

(d)

A Feedback Circuitry: A feedback circuitry has been implemented to offer feedback channels during the periods where the load voltage and current waveforms have opposite polarities. These periods, as well as the conduction patterns of the switching devices, are load-dependent. Q(f1) and D(f1) conduct over periods of the 1st voltage, Q(f2) and D(f2) conduct over periods of the 2nd stage, and so on up to the Mth stage, where Q(fM) and D(fM)) conduct over periods of the Mth stage.

Figure 2 shows the conduction patters and the typical waveforms of a 3-stage system [16] as a demonstration example.

3. System Analysis

Referring to Figure 2, the voltage waveform over the 1st quarter of the ωt axis is given as:

v_o(ωt) = V(1) forα(1) ≤ ωt ≤ α(2)

V(2) forα(2) ≤ ωt ≤ α(3)

V(m) forα (m) ≤ ωt ≤ α(m + 1)

(1)

V(M) forα(M) ≤ ωt ≤ π /2

Since the voltage waveform is an odd quarter-wave symmetric, then A(0) = A(n) = 0. B(n) can be evaluated as:

$$B\left(n\right)={\displaystyle \frac{4}{\mathsf{\pi }}}{\int }_{\alpha \left(m\right)}^{\alpha \left(m+1\right)}V\left(m\right)sin\left(n\omega t\right)·d\omega t, for n=odd.$$

(2)

Performing the mathematical operations and simplifying yields:

$$\mathrm{B}(\mathrm{n})={\displaystyle \frac{4}{\mathrm{n}\mathsf{\pi }}}{\sum }_{m=0}^{M}V\left(m\right)\left\{\right[\cos \left(n\alpha \left(m\right)\right]-\cos \left[n\alpha \left(m+1\right)\right]\}$$

Since α(0) = 0, α(M + 1) = π/2, and V(0) = 0, the above equation is rearranged to give the following form:

$$B(n)={\displaystyle \frac{4}{\mathrm{n}\mathsf{\pi }}}\sum _{m=1}^{M}E\left(m\right)\mathrm{c}\mathrm{o}\mathrm{s}\left[n\alpha \left(m\right)\right]$$

(3)

where E(m) = V(m) − V(m − 1).

Note that since A(n) = 0, the displacement angle is zero (i.e., ᴪ(n) = 0).

The RMS value of the nth harmonic component of the output voltage waveform can then be given by the expression:

$$Vo (n)={\displaystyle \frac{2\sqrt{2}}{\mathrm{n}\mathsf{\pi }}}\sum _{m=1}^{M}E\left(m\right)\cos \left[n\alpha \left(m\right)\right]$$

(4)

The instantaneous expression of the voltage waveform can then be given by the generalized expression:

$$v\mathrm{o}(\mathsf{\omega }\mathrm{t})=\sum _{n=1,3,5\dots }^{\infty }{\displaystyle \frac{2\sqrt{2}}{\mathrm{n}\mathsf{\pi }}}\sum _{m=1}^{M}E\left(m\right)\cos \left[n\alpha \left(m\right)\right]·\sin n\omega t$$

(5)

An analytical expression of the RMS load voltage can then be evaluated by the expression:

$$Vo(rms)= \sqrt{{\displaystyle \frac{2}{\pi }} \sum _{m=1}^M{\int }_{\alpha \left(m\right)}^{\alpha (m+1)}{V\left(m\right)}^2 d\omega t}$$

Performing the mathematical expressions and simplifying yield:

$$Vo(rms)=\sqrt{{\displaystyle \frac{2}{\mathsf{\pi }}}\sum _{m=1}^M {V\left(m\right)}^2\left[\alpha \left(m+1\right)-\alpha \left(m\right)\right]}$$

(6)

where α(m + 1)) = π/2.

The corresponding expressions of load current waveforms can then be given as:

The RMS value of the nth harmonic component of the load current waveform can be expressed by:

$$Io(n)={\displaystyle \frac{2\sqrt{2}}{\mathrm{n}\mathsf{\pi }\mathrm{z}\left(\mathrm{n}\right)}}\sum _{m=1}^{M}E\left(m\right)·\cos \left[n\alpha \left(m\right)\right]$$

(7)

where Z(n) is the load impedance of the nth harmonic component (i.e., Z(n) = $\sqrt{R^2+({\omega L)}^2}$). R and L are the load resistance and inductance, respectively.

The RMS value of the load current waveform can then be given as:

$$Io(rms)=\sqrt{\sum _{n=1,3,5,\dots }^{\infty }{Io\left(n\right)}^2}$$

(8)

The instantaneous load current waveform is given by the expression:

$$i\mathrm{o}(\mathsf{\omega }\mathrm{t})=\sum _{n=1,3,5\dots }^{\infty }{\displaystyle \frac{2\sqrt{2}}{\mathrm{n}\mathsf{\pi }\mathrm{z}\left(\mathrm{n}\right)}}\sum _{m=1}^{M}E\left(m\right)\cos \left[n\alpha \left(m\right)\right]·\sin \left(n\omega t- \varphi \left(n\right)\right)$$

(9)

where $\varphi \left(n\right)={tan}^{-1}\left({\displaystyle \frac{n\omega L}{R}}\right)$.

4. System Solution

As previously investigated, for a system with (M) voltage levels, the system has (2M) different unknowns, (M) switching angles, and (M) voltage levels. To evaluate these unknowns, a set of (2M) equations should be formulated. These equations can be formulated from the general expression of Equation (5). V_o(n) can be rewritten as:

$$\begin{gathered} Vo(n)={\displaystyle \frac{2\sqrt{2}}{\mathrm{n}\mathsf{\pi }}}[E\left(1\right)·\mathrm{c}\mathrm{o}\mathrm{s}(n\alpha \left(1\right))+E\left(2\right)·\cos \left(n\alpha \left(2\right)\right)+\dots \\ \dots +E\left(m\right)·\cos \left(n\alpha \left(m\right)\right)+\dots +E\left(M\right)·\cos \left(n\alpha \left(M\right)\right) \end{gathered}$$

(10)

Since it is usually desired to eliminate the lower-order harmonics, the first (2M) equations corresponding to n = 1, 3, 5, …, (4M − 1) are formulated, bearing in mind that V(1) = V_r (rated load voltage), and V_o(3) = V_o(5) = V_o(7) + V_o(9) = V_o(11) … = V_o(4M − 1) = 0. This ensures generation a specified value of the output fundamental load voltage, and elimination of (2M − 1) components of the lower-order harmonics of the output voltage and current waveform.

The above set of (4M − 1) non-linear transcendental equations can then be solved using the Newton–Raphson method for the (4M − 1) unknowns (these are: α (1), α (2), …, α (M), E (1), E (2), … E (M)). The waveform voltage levels V(m) can then be evaluated by means of the expression:

$$V\left(m\right)= \sum _1^{m}E\left(m\right)$$

(11)

Bearing in mind that E(0) = V(0) = 0, the voltage levels of the system can then be given as:

V(1) = E(1),

V(2) = E(1) + E(2),

(12)

V(3) = E(1) + E(2) + E(3) and so on… up to m = M.

Table 1. Switching angles and voltage levels versus M for a fundamental load voltage of 230 V.

M	1	2	3	4	5
α(1)	30°	18°	12.8°	10.°	8.2°
α(2)	-	54°	38.57°	30°	25.5°
α(3)	-	-	64.29°	50°	41°
α(4)	-	-	-	70°	57.2°
α(5)	-	-	-	-	73.6°
V(1)	294.84	194.27	142.32	111.82	91.95
V(2)	-	314.34	256.45	210.14	176.95
V(3)	-	-	319.78	283.13	246.66
V(4)	-	-	-	321.96	296.88
V(5)	-	-	-	-	323.05

shows the solution results of the above set of equations for a fundamental (i.e., rated) voltage of 230 V and for different values of M in order to investigate the effects of the number of stages or voltage levels on the system performance. It can be noticed that the DC input to the system (i.e., V_o(1)) varies from 294.84 V for M = 1 to 323.05 V for M = 5. It can be realized that the increment of the input DC voltage becomes smaller and smaller as M goes higher.

For demonstration purposed, typical waveforms of the load voltage and current waveforms and their harmonics spectrums are shown in Figure 3, for a load phase angle of 30° and a 3-stage system (i.e., M = 3). The quality of these generated waveforms is usually evaluated by means of total harmonics distortion factor (THDF), which is mathematically defined by the expression:

$$THDF={\displaystyle \frac{\sqrt{{Vo\left(rms\right)}^2-{Vo\left(1\right)}^2}}{Vo\left(1\right)}}$$

(13)

Variations of this factor for different values of M will be demonstrated in the following section.

5. Results

The variations of the THDF of the generated voltage waveform versus the number of DC link stages M is shown in Figure 4. This factor tends to decrease for higher numbers of M, and hence, different voltage waveform levels. The corresponding variations of the THDF of the output current waveform versus M at a load phase angle of 30° is shown in Figure 5. It can be noticed that this factor varies from just below 9% for a single-stage system (i.e., M = 1), down to almost less than 0.5% for a 5-stage system (i.e., M = 5). In between, for a 3-stage system (i.e., M = 3), the THDF of the load current is shown to be less than 2%. Figure 6 shows the variations of the load current THDF for different values for M and different values of load phase angles.

6. Conclusions

A multilevel voltage source inverter with SHE-PAM and SHE-PWM is reported in this paper. A generalized analysis and solution of the system is developed to investigate the effect of the number of DC link stages, and hence the voltage waveform levels, on the generated waveform quality. The results show that an M stage system results in the elimination of (2M − 1) lower-order harmonics. This implies that as the number of stages increases, better waveform quality is achieved.

However, the improvement of the waveform quality becomes insignificant as M becomes greater than three, implying that higher values of M are not practically justified in terms of system complexity and cost. The reported system is exceptionally suitable for fixed-voltage fixed-frequency load applications, such as PV systems, UPS systems, and home-to-vehicle and vehicle-to-home applications. This is due to the fact that the waveform parameters (i.e., voltage levels and switching angles) are calculated once during the design stage of the system. This implies a significant reduction of the system complexity and cost.