Low-Loss, Multi-Reticle-Stitched SiN Waveguides for 300 mm Wafer-Level Optical Interconnects

Abstract

With the rapid development of artificial intelligence (AI) and machine learning (ML) applications, wafer-level optical I/O is becoming increasingly attractive for massive and efficient data interconnects in future wafer-scale multi-processor-units (multi-XPU) compute clusters with unparalleled data bandwidth, energy efficiency, and low latency. In this paper, we present a 300 mm sized wafer reticle-stitched low-pressure chemical vapor deposition (LPCVD) silicon nitride (SiN) waveguide technology and demonstrate a multi-reticle-stitched ~56 cm long waveguides across 20 reticles with propagation loss of 0.13~0.15 dB/cm at 1310 nm wavelength, and <0.001~0.002 dB SiN waveguide stitch loss, which is because of <5 nm high-precision reticle lithography offset. These advantageous features of low-loss reticle-stitched SiN waveguides have the potential to significantly enhance future optically interconnected wafer-scale multi-chip compute systems.

1. Introduction

The increasing popularity of artificial intelligence (AI) and machine learning (ML) is driving a growing demand for high-bandwidth, low-latency, and energy-efficient interconnects between compute chips (such as CPUs, GPUs, …, XPUs, etc.) and high-bandwidth memory (HBM) in AI/ML compute clusters [1,2,3,4]. Wafer-level optical interconnects (WL-OIs) is an emerging technology to interconnect multiple tens of XPUs or HBMs on a single 300 mm wafer [5,6]. This technology offers superior chip edge bandwidth density, energy efficiency, and latency compared to fiber-coupled links while also providing significantly longer reach than on-wafer copper interconnects [7,8]. As interconnect distances in the envisioned WL-OIs compute clusters (see Figure 1) are expected to span tens of centimeters, there is a strong need for developing low-loss, high-confinement, low-crosstalk, and high-density waveguide arrays that can propagate across the entire 300 mm wafer to exceed the current limits of edge bandwidth density.

Compared to silicon-based (refractive index n~3.5) waveguides [9], silicon reticle-stitched waveguides offer higher optical confinement but come with higher cost, higher propagation loss, and greater sensitivity to reticle offset. The SiN reticle stitch is preferred due to its lower sidewall-scattering-induced propagation loss and lower mode-mismatch-induced stitch loss because of its moderate refractive index (refractive index n~2.0) [10,11]. SiN is also considered convenient in silicon photonic integration. Therefore, in this paper, we present a 300 mm wafer-scale low-pressure chemical vapor deposition (LPCVD) SiN waveguide with high-precision reticle-stitch lithography. Cross-wafer-stitched (up to 20 reticles) waveguides up to 56 cm long are demonstrated with waveguide propagation loss of 0.12~0.15 dB/cm at 1310 nm.

2. Prospects of High-Precision Reticle Stitching

Reticle stitching is mature and commercially available for most silicon photonic applications on 200 mm platforms with a typical 100~200 nm reticle offset. However, for future bandwidth-hungry wafer-level optical I/O, ~10 nm level or higher precision reticle stitching is critical for bandwidth-intensive wafer-level optical I/O targeting > Tbit/s/mm chip edge bandwidth density. Below

Table 1. Prospects of high-precision reticle stitching.

	~100 nm Level Precision Reticle Stitching	~10 nm Level Precision Reticle Stitching
Basic info	Normal reticle stitching precision on 200 mm silicon photonics platform; enables the fabrication of multi-reticle large-scale photonic integrated circuits (PICs).	Higher reticle stitching precision (in this paper, demonstrated ~5 nm), primarily on 300 mm silicon photonics platforms.
Waveguide	Low-confinement waveguides (e.g., 100 nm thick SiN waveguides) can be stitched due to the large waveguide mode field diameter.	High-confinement waveguide arrays (e.g., 300 or 400 nm thicker waveguides, or Si waveguides) require ~10 nm stitching precision to minimize stitch loss and interface reflection.
Prospects	Reticle stitching suitable for lower-confinement waveguides, where typical reticle offsets of ~100 nm introduce negligible issues, as the stitch loss is low. The dashed lines indicate the reticle scribe lines.	A 300 mm wafer can accommodate ~100 XPUs, HBM stacks, and laser arrays to form AI/ML compute clusters. The ~10 nm level higher precision reticle stitching allows 300 to 400 nm thick SiN waveguides; allows densely packed SiN waveguide arrays at 2~5 μm pitch, ensuring reliable and low crosstalk long-distance propagation; allows 25~50 μm bend radii flexible routing; allows return loss isolation > 50–60 dB for dense laser arrays; and allows effective and compact waveguide crossings to provide better flexibility in inter-chip connectivity.
Disadvantages	The ~100 nm level reticle stitching is suitable for low-confinement waveguides, which have a substantial drawback that limits optical I/O edge bandwidth density. For example, low-confinement waveguides require thick oxide cladding to prevent substrate leakage, require >10 μm waveguide pitches to prevent dense waveguide crosstalk, require >100 μm bend radii to minimize bending loss, and lack effective and compact low-loss waveguide crossing devices—waveguide intersections are not allowed.	Achieving ~10 nm level reticle offsets requires advanced 193 nm immersion lithography tools and a 300 mm silicon photonic platform.

is the detailed discussion on the importance of ~10 nm level high precision for future wafer-level optical I/O.

3. Multi-Reticle-Stitched SiN Waveguides

To experimentally demonstrate the multi-reticle-stitched waveguides, test vehicle wafers (total of eight wafers for statistics, in which wafers D1~D4 are with 300 nm thick SiN, and wafers D5~D8 are with 400 nm thick SiN) were implemented in imec’s 300 mm CMOS pilot line [12]. Test vehicle wafers (in Figure 2a) are simple with only one patterned SiN layer. The 300 mm sized wafer processing starts with a 2.7 µm thick buried oxide (BOX) deposition. Next, either a 300 or 400 nm thick LPCVD SiN layer is deposited. Both 300 nm and 400 nm thicknesses are commonly used in silicon photonic integration with high optical confinement. The 300 nm thick SiN waveguides are expected to exhibit less sidewall scattering and lower propagation loss, while the 400 nm thick SiN waveguides have a higher effective index, allowing for larger bend curvatures and denser waveguide arrays [13]. After lithography and SiN patterning, an oxide top cladding layer is deposited and subsequently planarized, targeting a >2 µm thick top oxide (TOX) on SiN. The LPCVD SiN layer is patterned using advanced 193 nm immersion lithography, leveraging the high alignment precision for reticle stitch. Two different reticles (as shown in Figure 2c), each covering a full 26 × 33 mm² SiN mask, are used to form wafer-scale reticle-stitched waveguides. Each mask is exposed with the chosen reticles through a dedicated lithography job, resulting in the complete wafermap exposure depicted in Figure 2b.

Several cross-wafer loopback waveguides, up to 56 cm, are patterned by arranging the long waveguide bundles on the first SiN mask (Mask A) and the waveguide bend/termination (such as grating couplers and waveguide U-turns) on the second SiN mask (Mask B). Measuring cross-wafer waveguide loss is challenging on a wafer probe station due to the large wafer-scale separation between input and output grating coupler ports. To simplify the optical measurement process, loopback waveguides are employed. The design principle of the multi-reticle-stitched loopback waveguide is illustrated in Figure 2c. By probing optical fibers at different dies at ①~⑤ different wafer locations (in Figure 2c), the corresponding optical losses for the 8.3 cm, 20.2 cm, 32.1 cm, 44.1 cm, and 56.0 cm multi-reticle-stitched loopback waveguides can be measured. The propagation loss of the stitched waveguides can be extracted using the cutback technique (optical O-band optical loss readout shown in Figure 2d). The extracted propagation loss of the SiN waveguides is 0.13~0.15 dB/cm at 1310 nm. Additionally, the propagation loss slightly increases to higher loss at the longer 1350 nm wavelength due to impurities and chemical bond absorption (Si–H and N–H) inside the deposited SiN [14,15,16]. Although the propagation loss is slightly higher than the current state of the art (i.e., <0.1 dB/cm for SiN waveguides), the LPCVD SiN waveguides used in this work are integration-friendly, cost-effective, and commercially available, without requiring complex fabrication steps such as extremely high-temperature annealing.

4. SiN Waveguide Stitch Loss Analysis

Reticle offset, normally at the 10 nm or 100 nm level, is technically inevitable in stepper lithography, with the abrupt stitch interfaces and optical mode mismatch resulting in an additional waveguide stitch loss and unwanted interface reflection. At first, high-resolution scanning electron microscopy (SEM) is used to examine the etched interfaces of the stitched SiN waveguides. SEM images (in Figure 3) reveal a visually smooth interface without defects at the reticle-to-reticle interfaces. Then, dedicated double-exposed overlay (OVL) structures (inspection methodology shown in Figure 4) are used to analyze the reticle offset using SEM image processing and inspection function. OVL measurements were fully conducted on four wafers (each wafer has 53 reticles, and each reticle has six OVL structures at separate locations on the mask scribe line), and the measured x- or y- reticle offset was <5 nm.

Since reticle offset is inspected at less than 5 nm, to analyze the SiN waveguide stitch loss, the add–drop ring resonator pairs are proposed in Figure 5a. Ring resonators are preferred and widely used to monitor the SiN loss because they require very little chip area and are not sensitive to SiN grating coupler loss variations. Figure 5a shows the design layout of the add–drop ring resonator pair, including a reference ring resonator (ref ring, green) and a stitched ring resonator (stitch ring, partly red). Figure 5b is the schematic showing the design parameters, such as the input, thru, drop ports, self-coupling coefficients r₁, r₂, bus-to-ring distance, and SiN waveguide width, all labeled on the graph. All ring resonators are identically ~6 mm long with 50 µm radius waveguide bends. More importantly, the stitch ring has 12 additional reticle-to-reticle waveguide stitches to accumulate and amplify the weak stitch loss signal. Then, by comparing the internal loss differences between the stitch ring and ref ring, the average waveguide stitch loss can be determined. The calculated internal loss for both the stitch ring and reference ring across eight wafers, each with six randomly measured dies, is shown in Figure 6. As expected, the calculated internal loss of the stitch ring is generally higher than that of the reference ring (i.e., the red markers are expectedly higher than the green markers, with a few exceptions attributable to measurement deviations). This increased loss in stitch rings is attributed to 12 additional waveguide stitches. Then, the SiN waveguide mean stitch loss can be calculated by

$$\mathrm{s}\mathrm{t}\mathrm{i}\mathrm{t}\mathrm{c}\mathrm{h}\mathrm{ }\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}={\displaystyle \frac{\mathrm{s}\mathrm{t}\mathrm{i}\mathrm{t}\mathrm{c}\mathrm{h}\mathrm{ }\mathrm{r}\mathrm{i}\mathrm{n}\mathrm{g}-\mathrm{r}\mathrm{e}\mathrm{f}\mathrm{ }\mathrm{r}\mathrm{i}\mathrm{n}\mathrm{g}\mathrm{ }\mathrm{i}\mathrm{n}\mathrm{t}\mathrm{e}\mathrm{r}\mathrm{n}\mathrm{a}\mathrm{l}\mathrm{ }\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}{12\mathrm{ }\mathrm{a}\mathrm{d}\mathrm{d}\mathrm{i}\mathrm{t}\mathrm{i}\mathrm{o}\mathrm{n}\mathrm{a}\mathrm{l} \mathrm{s}\mathrm{t}\mathrm{i}\mathrm{t}\mathrm{c}\mathrm{h}\mathrm{e}\mathrm{s}}}$$

The extracted stitch loss is shown in Figure 7. Because of the <5 nm lithography reticle offset, the stitch loss is calculated to be <0.001~0.002 dB, which is comparable to a ~50 μm SiN waveguide section propagation loss. This result is promising for the future development and application of wafer-level optical interconnects.

5. Stitch Loss with a Worse 20 nm Reticle Offset

To validate the 0.001~0.002 dB stitch loss in Figure 7, a 20 nm y-direction reticle offset was imposed on D4 and D8 wafers by slightly offsetting the whole mask B lithography job. This was designed to see an expectedly higher waveguide stitch loss at the specific locations (the purple interfaces in Figure 8a). The overlay (OVL) inspection revealed that the reticle y-offset at the purple interfaces was increased to 20 ± 4 nm (mean ± 3σ). Then, the internal loss of the stitch ring and ref ring in wafers D4 and D8 was measured. For comparison, wafers D3 and D7 (without the 20 nm imposed y-offset) were also measured. Each wafer had more than 10 random dies measured at the purple interfaces. The results of the ring internal loss of the add–drop ring resonator pairs are presented in Figure 8c. The red markers are the internal loss of the stitch rings, the green markers are the internal loss of the ref rings, and the black bars are the internal loss difference between the stitch ring and ref ring. Obviously, wafers D4 and D8 showed higher stitch ring internal loss compared to wafers D3 and D7. Then, the increased SiN waveguide stitch loss can be calculated in Figure 8d; stitch loss increases to 0.002~0.005 dB due to the worse 20 nm y-offset. Notably, the 2.5 µm wide taper-up stitch exhibits ~0.001 dB lower loss compared to the 1.8 µm wide taper-up stitch. This indicates that a wider stitch width is better when the reticle offsets worsen.

6. Conclusions

In this paper, we present a 300 mm sized wafer reticle-stitched SiN waveguide. By arranging a dedicated wafermap exposure, up to 56 cm long multi-reticle-stitched loopback waveguides are demonstrated, propagating across 20 reticle interfaces with a propagation loss of 0.12~0.15 dB/cm at 1310 nm. Although the SiN waveguide propagation loss is a bit higher than that of state-of-the-art research, these cross-wafer waveguides exhibit a very small reticle-to-reticle lithography offset of <5 nm and negligible stitch loss of <0.001~0.002 dB. By leveraging the demonstrated reticle-stitched low-loss SiN waveguide, the future wafer-scale multi-XPU compute systems can be envisioned with unparalleled interconnect bandwidth, energy efficiency, and latency, which are essential for advancing wafer-level optical interconnects beyond state-of-the-art technologies in AI/ML compute clusters.