Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

Abstract

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (V_BK) were changed slightly after adding this SJ structure. The V_BK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the V_BK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

1. Introduction

The lateral double-diffused MOSFET (LDMOS transistor) is the major dominant power component in the fabrication of power integrated circuits (PICs) because of many excellent electrical characteristics such as low on-resistance, high input-impedance, fast switching-speed and high breakdown-voltage. By the same token, due to the advantages of lower on-resistance and high voltage sustaining, UHV n-channel lateral diffused MOSFET (nLDMOS) devices have been commonly installed in many lighting, power-management systems, automotive systems, and 5G communication fields [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16]. Even these UHV LDMOSs can be operated at very high voltage purposes, but compared with low-voltage (LV) and medium-voltage (MV) circuits, the electrostatic-discharge (ESD) immunity of UHV LDMOS related components is very feeble [17,18,19,20,21,22,23,24,25,26,27,28]. Nevertheless, a UHV nLDMOS component is mainly used in input/output (I/O) blocks and switching circuits, and it acts as a UHV device and at the same time as a self-protection ESD unit. Therefore, how to improve the ESD robustness of a UHV LDMOS is an important issue in these applications.

Moreover, in Figure 1, a new device-structure concept called the drift-region embedded super-junction (SJ) implemented in the vertical power device has been available commercially, which would break through the silicon device limit [29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49]. CoolMOS is registered by Infineon Technologies [50], these high-voltage SJ MOSFETs of CoolMOS components address applications for smart-phone chargers, notebook adapters, LED lighting as well as audio and TV power supplies. Here, the SJ idea is based upon achieving charge compensation in the off-state of a power MOSFET, in a set of alternating and heavily doped N- and P-pillars in the drift region of the high-voltage component. Meanwhile, provided that all of the pillars of SJs are fairly narrow and net dopants in both pillars are approximately equal, it is possible to deplete the pillars at relatively low voltage. Under the depletion situation, the N- and P-pillars appear to be an intrinsic (very low doped) layer and a near uniform electric field in the drain-side is achieved, therefore, resulting in a high breakdown voltage. However, in Figure 2, the SJ concept can be applied for lateral high-voltage devices because the charge interaction between the substrate (bulk) and SJ region exists, which is called the substrate-assisted depletion effect [32,40,47,49]. Of course, the breakdown-voltage behavior of this structure will be influenced.

For improving the ESD capability of a UHV LDMOS, this study proposes a novel structure, where an elliptical cylinder SJ is added into the UHV circular nLDMOS. It [29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49] is known that an nLDMOS with these SJs in the drift region is quite a complicated structure and it will become quite different from a conventional UHV LDMOS. Generally, an nLDMOS-SJ composite device offers simultaneously high breakdown-voltage (V_BK) and low on-resistance (R_on) behavior [38,41,49,50]. Under normal circumstances, if there is an SJ structure (a P-pillar such as the HVPW layer) in the drain region, it will cause additional and extended extra depletion regions. These extended depletion regions will reduce the peak electric field along the conduction path, so it may cause the ability to resist ESD instant large electric fields. Then, how does this architecture change the HBM ESD capabilities of a UHV circular nLDMOS with elliptical cylinder super-junctions (SJs) structure? Moreover, in this article, we will choose two architectures (four-zone and eight-zone types) with a high degree of symmetry, and the layout is not too complicated (in order for the industrial practicality to be higher in the future). In order to realize these experimental samples, a TSMC 0.5 μm UHV bipolar-CMOS-DMOS (BCD) process is used in these UHV devices fabrications.

2. Device Layouts of UHV 300 V nLDMOS Related Devices

2.1. The Benchmarked Reference Sample (Pure nLDMOS)

The layout diagram and 3-D cross-sectional view (along the line AB of Figure 3a) of a UHV 300 V circular nLDMOS benchmarked reference device are shown in Figure 3a,b, respectively. In Figure 3a, due to the high operation voltage and high breakdown voltage need, a lightly n-doped HVNW layer is used in the drain-side drift region. The PBody and deep P-Well (DPW) layers will form a reduced surface-field (RESURF) structure, which causes the drift region to be completely depleted and increases the breakdown voltage of the device [30]. Similarly, the poly2 surround above the drift region is used to increase the breakdown voltage. In the rectangular-type layout, the current will flow through and concentrate at the electrode corner; therefore this component is easily damaged there. Instead, in Figure 3b, the layout of a UHV MOSFET adopts a circular mode due to the conduction current uniformly flowing along the shortest radial-outward path and a circular structure is used in order to prevent the current’s uneven flowing. Meanwhile, a gate-grounded MOSFET (GGnMOS) structure is commonly used in the routing architecture of an ESD protection device, which discharges the instantaneous current of an external transient pulse mainly through the parasitic bipolar-junction transistor (BJT) conduction of this GGnMOS component. These experimental samples were fabricated by a TSMC 0.5 μm UHV BCD process with a channel length L of 2.5 μm and a channel width W of approximately 394.3 μm.

2.2. nLDMOS-SJs Samples with SJs Length Modulation

The Symmetrical Eight-Zone Elliptical Cylinder Type (M8) of LDMOS-SJs

Next, the cross-sectional view and layout diagram of a UHV 300 V nLDMOS with symmetrical eight-zone elliptical cylinder SJs (type-M8) in the drain region are presented in Figure 4. This novel arrangement is taken as the length of X (length X) modulation of the HVPW layer embedded in the drain-side drift region. Then, this arrangement is set to increase the length X of the HVPW zone shown in Figure 4b, and which are 5, 10, 15 and 20 μm, respectively. Meanwhile, the width (thickness) of these entire elliptical cylinder SJs are kept to 3 μm. Therefore, this study will mainly discuss the impact of HVPW distribution and how the HBM ability is affected by the HVPW length X.

Based on these devices and the reference sample (previous sub-section) structures, an equivalent circuit of the nLDMOS-SJ devices with SJ length modulation is presented in Figure 5; R_bulk is the parasitic resistances of the source-to-bulk; the BJT is a parasitic device of the gate-grounded nLDMOS device; the parasitic resistance (R_drift)_SJ in the drift region is sufficiently high and varied with the SJs length modulation; and R_drain is the parasitic resistances of the drain electrode.

2.3. SJs Number Modulation: Six LDMOS-SJs Devices with the Symmetrical Four-Zone Elliptical Cylinder Type

In Figure 6, the following items are the SJs’ number modulation of symmetrical four-zone elliptical HVPW cylinders, which are classified as the group A (M1, M5, M9) and the group B (M2, M6, M10), respectively. In these six LDMOS-SJ devices, each has a common feature, that is, the SJ on each side is perpendicular to the SJs on the adjacent sides. Additionally the length X of the HVPWs shown in Figure 6 are 20 μm and 5 μm for the group A (M1, M5 and M9) and B (M2, M6 and M10), respectively. Meanwhile, the thicknesses of these six elliptical cylinder SJs are kept to 3 μm. In the case of increasing the HVPWs in this item, we first set the modulation without affecting the breakdown voltage of the electrical characteristics so much, and it is desirable to understand how the modulation impacted on HBM ESD reliability.

3. HBM Testing System

In the HBM ESD-reliability level testing, a KeyTek MK2 ESD testing machine was used. The ESD testing mode was human-body model (HBM) and the maximum zapping-voltage can be zapped up to ±8000 V. The testing waveforms were confirmed by the MIL-STD-883 EOS/ESD and ANSI/ESDA/JEDEC JS-001 test standards [51,52]. Then, we used the positive-to-VSS (PS) mode (applied a zapping voltage to the drain terminal of this device) for these testing samples. Furthermore, the testing arrangement is shown in Figure 7. The testing voltages for HBM testing were in the range of 500 to 8000 V and changed by 250 V per interval in the step-1 HV zapping. A quantity of I-V curve was selected as the failure judge criterion in the step-2 leakage-current measurement. Therefore, the leakage-current was fixed at 1 μA for sensing before/post HBM zapping and compared for I-V curve variations. If the voltage-shift changed by more than ±30% (ΔV_shift > ±30%), then this pin was decided as not qualified at this HBM zapped level.

4. Experimental Data and Discussion

Even LDMOSs with the super-junction (SJ) structures were recently developed to obtain the trade-off targets between the breakdown-voltage (V_BK) capability and the on-resistance behavior which are always the key issues in the design of power electronics. The SJ architecture is chiefly to gain charge compensation in the off-state (an ESD device with GGnMOS configuration is operated at the normally-off state) of a UHV device, by alternating doped N- and P-pillars comprising the drift region near the device drain side.

Firstly, the experimental results of normal output I-V characteristics of the UHV 300 V reference nLDMOS and nLDMOS-SJs type-M8 with X = 10 μm are shown in Figure 8. Obviously, these output I-V behaviors changed very little after adding elliptical cylinder SJs. For example, V_g = 5 V and V_d = 40 V, and the drain currents were equal to 2.551 mA and 2.5 mA, respectively. The output I-V variation does not exceed 1.88%. Meanwhile, on the other hand, the breakdown voltages of these nLDMOS related devices with symmetrical eight-zone elliptical cylinder SJs in the drain region are presented in Figure 9. From these experimental results, there is not much change in the breakdown-voltage (V_BK) test after adding the SJ structure, which fall between 391 and 393.5 V (the original benchmarked device under test (DUT) is 393 V). The V_BK‘s value variation does not exceed 0.51%, it means that the basic electrical properties of the nLDMOS components are carefully controlled so that they do not change much. That is, in this study, we want to enhance the ESD-reliability capability without affecting the original electrical behavior afterwards by painstakingly adding these SJ structures.

In Figure 10, the HBM immunity level of the benchmarked GGnLDMOS reference DUT is 2500 V. As the symmetrical eight-zone elliptical cylinder SJs (type-M8) are embedded in the drain-side drift region of the nLDMOS and the length X of the HVPW layer is modulated, it is found that the HBM capability of these nLDMOS-SJ samples increases as the length X of the HVPW layer (also called the HV PW/NW area ratio) becomes longer and larger. When the HVPW length X is 20 μm, the HBM capability value can be promoted up to 5500 V, so its ESD capability is improved by 120% as compared with the original benchmarked GGnLDMOS device. Due to the previous description of the equivalent circuit of Figure 5, an nLDMOS device embedded SJ in the drift region can be equivalently regarded as a variable linear resistor [53]. Therefore, by the linear-regression technique, a strongly linear relationship for the HBM immunity levels of these M8s versus the HVPW/HVNW area ratio can be found in Equation (1),

$$\begin{gathered} V_{HBM}={(V_{HBM})}_0+C\times (\begin{array}{cc}Area& Ratio\%{)}_{HVPW/HVNW}\end{array} \\ \approx 2240V+5157.1V\times (\begin{array}{cc}Area& Ratio\%{)}_{HVPW/HVNW}\end{array} \end{gathered}$$

(1)

where the (V_HBM)₀ is the HBM fitting level for the nLDMOS reference sample and C is a linear-proportional slope constant, such as here for these type-M8 samples the (V_HBM)₀ is 2240 V and C is 5157.1 V, respectively.

By using the Silvaco EDA software for electric field verifications, Figure 11a,b are the 3-D side view diagrams of a thin-slice structure for the nLDMOS reference device and the nLDMOS-SJ M8_X20 device, respectively. Then, a high voltage of 400 V was applied at the drain terminals of these two DUTs for comparing high electric-field distributions. From Figure 11c, the electric field of the circular nLDMOS reference device was concentrated at the depletion area of the LOCOS edge under this high voltage biase, and the peak value of the electric field is about 1.0247 × 10⁶ V/cm. However, in Figure 11d for the nLDMOS-SJ M8_X20 device, the electric field is concentrated between HVPW and N-EPI, and the depletion region by the SJ (HVPW and HVNW). The maximum electric field of the nLDMOS-SJ M8_X20 device is downgraded to approximately 1.9192 × 10⁵ V/cm, and the peak value of this electric field decreases to the ratio of 18.73% compared with the nLDMOS reference device. Obviously, it reveals that the nLDMOS-SJ structure can indeed reduce the peak electric field of the device.

Next, for proof again by the symmetric four-zone elliptical cylinder SJ modulation, the HVPW structures (M1, M5 and M9, and M2, M6 and M10) are embedded in the drain side, and the HBM values are presented in Figure 12. Because they are not as highly symmetrical as the type-M8 devices, the HBM capability versus the HVPW/HVNW area ratio cannot be satisfactorily linearly related, but can be with another high-order proportional relationship for these group A and B samples. Nevertheless, the HBM ESD capability is somewhat higher with the increase in the number of HVPW SJs. The highest HBM value of M5 (4500 V), its (the M5) ESD capability, is improved by 80% as compared with the original benchmarked GGnLDMOS DUT. Meanwhile, it is found that the HVPW/HVNW area ratio of the group A samples is generally higher than that of the corresponding group B devices, so their ESD HBM abilities are also relatively high. In the case of M9 and M10 (three HVPW SJ arrays in the outward direction), HBM values are downgraded than that of the M5 and M6 (two HVPW SJ arrays in the outward direction). This is caused by the thin-oxide definition (OD) distance from the outermost HVPW to the gate and the heat dissipation cross-sectional area being too small, resulting in a decreasing data value in the HBM robustness.

5. Conclusions

This paper is focused on the enhancements of HBM-immunity levels for UHV 300 V nLDMOS devices being added with 1) symmetrical eight-zone elliptical cylinder SJs (type-M8) in the drain region, in which the length Xs of SJs are 5, 10, 15 and 20 μm, respectively; and 2) symmetrical four-zone elliptical cylinder SJs in the drain region. The first part focuses on the symmetrical eight-zone nLDMOS-SJ experimental samples; we can find that the breakdown-voltages of these samples do change a little due to the addition of this SJ structure. The highest test data does not change by more than 0.51% compared to the original benchmarked GGnLDMOS sample, which means that the basic normal electrical characteristics of nLDMOS-SJ components change very little. In addition, the HBM testing values of these samples are optimal for the X20 sample, and it can be upgraded to 5500 V (120% higher than that of the benchmarked DUT). Meanwhile, a strongly linear relationship between the HBM immunity levels versus the HVPW/HVNW area ratio could be found. That is a very useful indicator of how to improve the ESD immunity in UHV nLDMOS transistors. The second part revealed that, for the symmetric four-zone elliptical cylinder SJs in the drain side, the HBM capability is generally higher with the increase in the number of HVPW SJs, with the highest HBM value of M5 (4500 V) improved by 80%. Then, it can be concluded that a UHV nLDMOS device embedded with symmetric elliptical cylinder SJs in the drift region is a good strategy and the HBM capability of these UHV nLDMOS transistors could be effectively improved without changing the basic electrical properties and adding any extra cell area. Therefore, it is a very positive method for the ESD-reliability enhancement in UHV LDMOS components.