Design of a 41.14–48.11 GHz Triple Frequency Based VCO
Abstract
:1. Introduction
2. Circuit Design
2.1. Voltage Controlled Oscillator
2.1.1. Oscillation Frequency
2.1.2. Phase Noise
2.2. Amplitude Detector and Comparator
2.3. Designing Mixer
3. Results
4. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Corners | Phase Noise (1 MHz) | Phase Noise (10 MHz) |
---|---|---|
Typical-typical (TT) | −99.47 | −121.8 |
Fast-fast (FF) | −94.41 | −119.57 |
Slow-slow (SS) | −97.49 | −120.61 |
Ref. | [3] 2 | [9] 1 | [16] 2 | [25] 2 | [26] 2 | This Work 1 | |
---|---|---|---|---|---|---|---|
Process | 56 nm SOI 5 | 0.13 µm CMOS | 65 nm CMOS | 40 nm CMOS | 65 nm CMOS | 0.18 µm CMOS | |
Frequency (GHz) | 18.57 | 25.5 | 54 | 55.45 | 46.8 | 44.62 | |
Tuning range (%) | 5.38 | 43 | 9.1 | 25.4 | 5.8 | 15.6 | |
Phase noise at offset frequency (dBc/Hz) | −117.6 | −96 | −95.5 | −100.1 | −100 | −99.47 | |
at 5 MHz | at 1 MHz | at 1 MHz | at 1 MHz | at 1 MHz | at 1 MHz | ||
PDC (mW) | 2.56 | 12 | 24 | 22 | 5 | 14 4 | 4.16 3 |
Figure of merit (FOM) (dBc/Hz) | −185.1 | −173.33 | −179 | −179.8 | −186.415 | −187.95 4 | −193.22 3 |
Total figure of merit (FOMT) (dBc/Hz) | −190.43 | −186 | −179.8 | −187.9 | −188.5 | −191.81 4 | −197.08 3 |
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Nasri, A.; Toofan, S.; Estebsari, M.; Estebsari, A. Design of a 41.14–48.11 GHz Triple Frequency Based VCO. Electronics 2019, 8, 529. https://doi.org/10.3390/electronics8050529
Nasri A, Toofan S, Estebsari M, Estebsari A. Design of a 41.14–48.11 GHz Triple Frequency Based VCO. Electronics. 2019; 8(5):529. https://doi.org/10.3390/electronics8050529
Chicago/Turabian StyleNasri, Abbas, Siroos Toofan, Motahhareh Estebsari, and Abouzar Estebsari. 2019. "Design of a 41.14–48.11 GHz Triple Frequency Based VCO" Electronics 8, no. 5: 529. https://doi.org/10.3390/electronics8050529
APA StyleNasri, A., Toofan, S., Estebsari, M., & Estebsari, A. (2019). Design of a 41.14–48.11 GHz Triple Frequency Based VCO. Electronics, 8(5), 529. https://doi.org/10.3390/electronics8050529