Soft Switching DC Converter for Medium Voltage Applications

Abstract

A dc-dc converter with asymmetric pulse-width modulation is presented for medium voltage applications, such as three-phase ac-dc converters, dc microgrid systems, or dc traction systems. To overcome high voltage stress on primary side and high current rating on secondary side, three dc-dc circuits with primary-series secondary-parallel structure are employed in the proposed converter. Current doubler rectifiers are used on the secondary side to achieve low ripple current on output side. Asymmetric pulse-width modulation is adopted to realize soft switching operation for power switches for wide load current operation and achieve high circuit efficiency. Current balancing cells with magnetic component are used on the primary side to achieve current balance in each circuit cell. The voltage balance capacitors are also adopted on primary side to realize voltage balance of input split capacitors. Finally, the circuit performance is confirmed and verified from the experiments with a 1.44 kW prototype.

1. Introduction

Medium voltage dc–dc converters have been proposed and implemented to achieve high power density and high efficiency advantages for dc light rail transportation systems [1,2], dc microgrid systems [3,4], or industry power converters [5,6]. In those applications, the high side dc bus voltage is normally at 750 V. The 1200 V SiC or Insulated Gate Bipolar Transistor (IGBT) power switches can be used to convert 750 V dc bus voltage to low voltage output through high-frequency link dc–dc converters. However, SiC devices are expensive, and the switching frequency of IGBT devices is less than 60kHz. The series-connected switches [7,8] and series-connected dc–dc converters [9,10] can be used for medium voltage converters with 600V Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) power devices. These two approaches can reduce the voltage stress on power devices. However, the voltage stresses on each power switch are difficult and unbalanced. Therefore, power devices still have an unbalanced voltage stress problem. Three-level pulse-width modulation converters or resonant converters have been presented in [11,12,13,14] to lessen the voltage rating and switching loss on power devices. Modular converters with series or parallel connection have been developed in [15,16,17] for high voltage or current applications. However, the current balance in each circuit modular should be controlled well in order to distribute equal power in each modular. To solve the current balance issue in each circuit modular, the current balance control approaches have been discussed in [18,19] by using the passive magnetic component.

This paper presents a high voltage dc–dc converter with three cascade half-bridge circuits on primary side to reduce the voltage and current ratings of power devices for high voltage and medium power applications, such as dc light trail transportation systems and three-phase ac–dc power converters. Voltage balance capacitors are also employed on the primary side in order to balance input split voltages. To prevent current imbalance on each half bridge circuit, the magnetic coupling (MC) current balance components are employed between each half bridge circuit. If the primary-side currents are unbalanced, then the primary-side and secondary-side voltages of MC component will decreased, or increased, in order to compensate the imbalance in primary-side currents. Asymmetric pulse-width modulation approach is adopted to realize the soft switching turn-on characteristic for power switches. Therefore, the switching losses of power devices at high frequency operation can be reduced. Current doubler rectifiers are used on low voltage side in order to reduce the output ripple current. The paper is organized as follows. The circuit diagram and operating principle are presented in Section 2. The circuit characteristics of the proposed converter are discussed in Section 3. In Section 4, experiments are provided to demonstrate the effectiveness of the developed circuit. Then, the conclusion of the presented circuit is discussed in Section 5.

2. Circuit Diagram and Principles of Operation

The developed high-frequency link dc–dc converter is illustrated in Figure 1 to realize the main benefits of soft switching operation, low switching loss, low output ripple current and the balance primary-side and secondary-side currents. Three half-bridge circuits with primary-series secondary-parallel configuration are used in the proposed converter to realize low voltage stress V_in/3 on power switches S₁~S₆, and low current stress I_o/6 on power diodes D₁~D₆. Therefore, 600 V power MOSFETs are used on the primary side to achieve high frequency operation and low conduction loss. Voltage balance capacitors C_f1 and C_f2 are employed on the primary side to achieve a split voltages balance at V_in/3. Half-bridge circuits are operated under asymmetric pulse-width modulation. Therefore, the soft switching turn-on of power switches can be achieved, and the circuit efficiency is improved. The magnetic coupling current balance [19] cells, MC₁ and MC₂, are used on the primary side to achieve current balance for each half-bridge circuit. Therefore, the current unbalance issue of modular converters is overcome. The current doubler rectifiers are used on the secondary side to accomplish low ripple current on load side.

Figure 2 provides the voltage and current waveforms of the studied converter in a switching cycle. Based on the pulse-width modulation waveforms shown in Figure 2, eight operating steps can be observed in each switching cycle under steady state. Power switches S₁, S₃, and S₅ have the same gating signals, and S₂, S₄, and S₆ have the same gating signals. The duty cycle of S₁, S₃, and S₅ denotes d and the duty cycle of S₂, S₄, and S₆ is 1 − d. When S₁, S₃, and S₅ are active, then S₂, S₄, and S₆ are inactive. We can obtain that v_Cf1 = v_Cin1 and v_Cf2 = v_Cin2. If S₁, S₃, and S₅ are inactive, and S₂, S₄, and S₆ are active, then v_Cf1 = v_Cin2 and v_Cf2 = v_Cin3. For steady state operation, the capacitor voltages v_Cin1 = v_Cin2 = v_Cin3 = v_Cf1 = v_Cf2 = V_in/3. Before the system analysis, the circuit parameters on the proposed circuit are assumed as follows: (1) the same voltage balance capacitances C_f1 = C_f2 = C_f, (2) the same input split capacitances C_in1 = C_in2 = C_in3 = C_in, (3) the same output capacitances of power switches C_S1 = … = C_S6 = C_oss, (4) the same dc block capacitances C₁ = C₂ = C₃ = C_c, (5) the same turns ratio n₁ = n₂ = n₃ = n, (6) the identical magnetizing inductances L_m1 = L_m2 = L_m3 = L_m, (7) the same leakage inductances L_lk1 = L_lk2 = L_lk3 = L_lk << L_m, (8) the same output filter inductances L₁ = … = L₆ = L_o, and (9) the primary-side and secondary-side voltages of the magnetic coupling (MC) current balance transformers are zero under steady state. The equivalent circuits for eight operating steps are illustrated in Figure 3, and discussed as follows.

Step 1 [t₀~t₁]: Before time t₀, all the secondary-side diodes are in the commutated interval, and the primary-side currents i_p1~i_p3 increase. After time t₀, the secondary-side diodes, D₁, D₃, and D₅, are off. In step 1, the primary-side capacitor voltage v_Cf1 equals v_Cin1, and v_Cf2 equals v_Cin2. The ac-side input voltages of three half bridge circuits v_ab, v_cd, and v_ef are clamped at v_Cin1, v_Cin2, and v_Cin3, respectively. The magnetizing inductor voltages v_Lm1, v_Lm2, and v_Lm3 are equal to V_in/3 − v_C1, V_in/3 − v_C2, and V_in/3 − v_C3, respectively. The secondary-side inductor voltages v_L1, v_L3, and v_L5 are equal to (V_in/3 − v_C1)/n − V_o, (V_in/3 − v_C2)/n − V_o and (V_in/3 − v_C3)/n − V_o, respectively, and v_L2 = v_L4 = v_L6 = −V_o. Therefore, the primary-side currents i_p1 ~ i_p3 and the secondary-side currents i_L1, i_L3, and i_L5 increase, and the output inductor currents i_L2, i_L4, and i_L6 decrease, in step 1.

Step 2 [t₁~t₂]: Switches S₁, S₃, and S₅ are turned off at time t₁. Due to the positive value of i_p1~i_p3, v_CS1, v_CS3, and v_CS5 are increased and v_CS2, v_CS4, and v_CS6 are decreased. The charged and discharged times of C_S1~C_S6 are very fast so that the primary-side and secondary-side currents are constant in step 2.

Step 3 [t₂~t₃]: When v_CS2 = v_C1, v_CS4 = v_C2 and v_CS6 = v_C3 at time t₂. The primary-side and secondary-side winding voltages of T₁~T₃ are zero voltage. Thus, the secondary-side diodes D₁~D₆ are forward biased to commutate the load current such that i_L1~i_L6 decrease, i_D1, i_D3, and i_D5 increase, and i_D2, i_D4, and i_D6 decrease in step 3. C_S2, C_S4, and C_S6 can be discharged to zero voltage if the energy on the leakage inductors L_lk1~L_lk3 is large enough, and the dead time t_d between the upper and lower switches on each half bridge leg is larger than the time interval in steps 2 and 3.

Step 4 [t₃~t₄]: The capacitor voltages v_CS2 = v_CS4 = v_CS6 = 0 at time t₃. Due to i_p1(t₃)~i_p3(t₃) being positive, the body diodes of S₂, S₄, and S₆ are conducting so that S₂, S₄, and S₆ are turned on at zero voltage switching. The secondary-side diodes, D₁~D₆, are at the commutated interval, and the primary-side leakage inductor voltages are v_lk1 = −v_C1, v_lk2 = −v_C2, and v_lk3 = −v_C3. Thus, the primary-side currents i_p1~i_p3 and the secondary-side inductor currents i_L1~i_L6 all decrease in step 4. In step 4, the current variations on i_p1~i_p3 approximate I_o/(3n) in order to accomplish the commutation interval through diodes D₁~D₆.

Therefore, the duty loss in step 4 is calculated as

$$d_{loss,4}=\frac{\Delta t_{34}}{T_{sw}}\approx \frac{L_{lk}{I}_o{f}_{sw}}{3n{v}_{C1}}$$

(1)

Step 5 [t₄~t₅]: The secondary-side diode currents i_D2, i_D4, and i_D6 are zero, and become reverse biased. In step 5, the capacitor voltages v_Cf1 = v_Cin2 and v_Cf2 = v_Cin3, and the ac side voltages v_ab = v_cd = v_ef = 0. Therefore, the magnetizing inductor voltages v_Lm1 ≈ −v_C1, v_Lm2 ≈ −v_C2 and v_Lm3 ≈ −v_C3. The output inductor voltages v_L1 = v_L3 = v_L5 = −V_o, v_L2 ≈ v_C1/n − V_o, v_L4 ≈ v_C2/n − V_o and v_L6 ≈ v_C3/n − V_o. Thus, i_L1, i_L3, and i_L5 decrease, and i_L2, i_L4, and i_L6 increase, in step 5.

Step 6 [t₅~t₆]: Power switches S₂, S₄, and S₆ are turned off at time t₅. Due to i_p1(t₅) < 0, i_p2(t₅) < 0 and i_p3(t₅) < 0, then C_S1, C_S3, and C_S5 will be discharged in step 6. Since the charged and discharged times of C_S1~C_S6 are very fast, the primary-side and secondary-side inductor currents are approximately constant in step 6.

Step 7 [t₆~t₇]: The output capacitor voltages v_CS1, v_CS3, and v_CS5 are discharged to v_C1, v_C2, and v_C3, respectively, at time t₆. Then, the primary-side and secondary-side winding voltages of T₁~T₃ are all zero voltage. In step 7, the secondary-side diodes D₁~D₆ are all conducting to commutate the inductor currents i_L1~i_L6. At time t₇, C_S1, C_S3, and C_S5 are discharged to zero voltage.

Step 8 [t₇~t₀+T_sw]: The capacitor voltages C_S1, C_S3, and C_S5 are discharged to zero voltage at time t₇. Due to i_p1(t₇)~i_p3(t₇) being all negative, the body diodes of S₁, S₃, and S₅ conduct. Therefore, S₁, S₃, and S₅ can be turned on under zero voltage after time t₇. Since D₁~D₆ are still conducting, the primary-side currents increase. The diodes currents i_D1, i_D3, and i_D5 decrease to zero at time t₀ + T_sw. The duty loss in this step 8 is calculated as:

$$d_{loss,8}\approx \frac{L_{lk}{I}_o{f}_{sw}}{3n(V_{in}/3-v_{C1})}.$$

(2)

3. Circuit Characteristics

Three half bridge circuits are used in the proposed converter with primary-series and secondary-parallel connection to distribute load power through three circuits. Therefore, the power rating of each half bridge circuit is one-third of load power, P_o/3. In order to balance the modular currents, the magnetic coupling (MC) current balance cells are presented and discussed in [19]. Therefore, the magnetic coupling current balance components MC₁ and MC₂ are used in the proposed converter to achieve current balance issue between three half bridge circuits. If the primary-side currents are unbalanced, such as |i_p2| > |i_p3|, then the induced voltage v_MC2,p is lessened to decrease current i_p2 and the secondary-side induced voltage v_MC2,s is increased to rise current i_p3. If the primary currents are balanced (|i_p1| = |i_p2| = |i_p3|), then the induced primary-side and secondary-side voltages of MC₁ and MC₂ cells are zero voltage, v_MC1,p = v_MC1,s = v_MC2,p = v_MC2,s = 0. Current doubler rectifiers are adopted on the secondary side to lessen the output ripple current. The average dc blocking voltages V_C1~V_C3 are related to the input voltage and duty cycle of S₁, S₃, and S₅. These three voltages can be calculated from the flux balance on the primary-side inductors.

$$V_{C1}=V_{C2}=V_{C3}=d{V}_{in}/3$$

(3)

The output voltage is related to input voltage, duty cycle, and turns ratio, according to the flux balance on the output inductors.

$$V_o=\frac{d(1-d)V_{in}}{3n}-\frac{I_o{L}_r{f}_{sw}}{3n^2}-V_f,$$

(4)

where V_f is the voltage drop on D₁~D₆. Due to the MC, current balance components are used on the primary side of the proposed converter, and the output currents of three half bridge circuits are balanced in steady state. The average secondary-side winding currents of T₁~T₃ are zero. Therefore, the average output inductor currents are calculated as

$$I_{L1}=I_{L3}=I_{L5}=(1-d)I_o/3,I_{L2}=I_{L4}=I_{L6}=d{I}_o/3.$$

(5)

If the duty cycle d < 0.5, then the average inductor currents I_L1, I_L3, and I_L5 are greater than I_L2, I_L4, and I_L6. The ripple currents on L₁~L₆ are calculated as

$$\Delta i_{L1}=\Delta i_{L3}=\Delta i_{L5}=\frac{V_o(1-d)T_{sw}+\frac{V_o{L}_{lk}{I}_o}{n(1-d)V_{in}}}{L_o},$$

(6)

$$\Delta i_{L2}=\Delta i_{L4}=\Delta i_{L6}=\frac{V_{o}d{T}_{sw}+\frac{V_o{L}_{lk}{I}_o}{nd{V}_{in}}}{L_o}.$$

(7)

From (5)~(7), the maximum and minimum output inductor currents are derived as

$$i_{L1,\max }=i_{L3,\max }=i_{L5,\max }=\frac{(1-d)I_o}{3}+\frac{V_o(1-d)T_{sw}+\frac{V_o{L}_{lk}{I}_o}{n(1-d)V_{in}}}{2L_o},$$

(8)

$$i_{L1,\min }=i_{L3,\min }=i_{L5,\min }=\frac{(1-d)I_o}{3}-\frac{V_o(1-d)T_{sw}+\frac{V_o{L}_{lk}{I}_o}{n(1-d)V_{in}}}{2L_o},$$

(9)

$$i_{L2,\max }=i_{L4,\max }=i_{L6,\max }=\frac{d{I}_o}{3}+\frac{d{V}_o{T}_{sw}+\frac{V_o{L}_{lk}{I}_o}{nd{V}_{in}}}{2L_o},$$

(10)

$$i_{L2,\min }=i_{L4,\min }=i_{L6,\min }=\frac{d{I}_o}{3}-\frac{d{V}_o{T}_{sw}+\frac{V_o{L}_{lk}{I}_o}{nd{V}_{in}}}{2L_o},$$

(11)

If the magnetizing inductances of T₁~T₃ are given, the ripple currents on L_m1~L_m3 are calculated as

$$\Delta i_{Lm}\approx \frac{d(1-d)V_{in}{T}_{sw}-\frac{L_{lk}{I}_o}{n}}{3L_m}.$$

(12)

Due to the conducting time on D₁~D₆ being related to the duty cycle d, the secondary-side diode average currents and voltage ratings are calculated as

$$I_{D1}=I_{D3}=I_{D5}=(1-d)I_o/3,I_{D2}=I_{D4}=I_{D6}=d{I}_o/3,$$

(13)

$$V_{D1,\mathrm{stress}}=V_{D3,\mathrm{stress}}=V_{D5,\mathrm{stress}}=(1-d)V_{in}/(3n),V_{D2,\mathrm{stress}}=V_{D4,\mathrm{stress}}=V_{D6,\mathrm{stress}}=d{V}_{in}/(3n).$$

(14)

Since the balance capacitors C_f1 and C_f2 are used on the primary side of three half bridge circuits, the input split voltages V_Cin1, V_Cin2, and V_Cin3 are balanced at V_in/3. Based on the half bridge circuit topology, the voltage rating of power switches S₁~S₆ is clamped at V_in/3. If the ripple currents on the output inductors and the magnetizing inductors are much less than the average output inductor currents at full load, then the root mean square (rms) currents of power devices are expressed in (15) and (16).

$$i_{S1,rms}=i_{S3,rms}=i_{S5,rms}\approx \frac{(1-d)I_o}{3n}\sqrt{d},$$

(15)

$$i_{S2,rms}=i_{S4,rms}=i_{S6,rms}\approx \frac{d{I}_o}{3n}\sqrt{1-d}.$$

(16)

The zero voltage conditions of power switches S₁, S₃, and S₅ are related to the primary-side currents i_p1(t₅), i_p2(t₅), and i_p3(t₅), respectively, and the input voltage. Similar, the zero voltage conditions of power switches S₂, S₄, and S₆ are related to the primary-side currents i_p1(t₁), i_p2(t₁), and i_p3(t₁), respectively, and the input voltage. The primary-side currents i_p1~i_p3 at time t₁ and t₅ are related to the load current and the ripple currents on the magnetizing inductors L_m1~L_m3, and output inductors L₁~L₆.

$$i_{p1}(t_1)=i_{p2}(t_1)=i_{p3}(t_1)\approx i_{Lm1,\max }+\frac{i_{L1,\max }}{n}\approx \frac{d(1-d)V_{in}{T}_{sw}-\frac{L_{lk}{I}_o}{n}}{6L_m}+\frac{(1-d)I_o}{3n}+\frac{(1-d)V_o{T}_{sw}+\frac{V_o{L}_{lk}{I}_o}{n(1-d)V_{in}}}{2n{L}_o},$$

(17)

$$i_{p1}(t_5)=i_{p2}(t_5)=i_{p3}(t_5)\approx i_{Lm2,\min }-\frac{i_{L2,\max }}{n}\approx -\frac{d(1-d)V_{in}{T}_{sw}-\frac{L_{lk}{I}_o}{n}}{6L_m}-\frac{d{I}_o}{3n}-\frac{d{V}_o{T}_{sw}+\frac{V_o{L}_{lk}{I}_o}{nd{V}_{in}}}{2n{L}_o}.$$

(18)

The necessary leakage inductance to achieve zero-voltage switching (ZVS) condition of S₁, S₃, and S₅ is expressed in (19).

$$L_{lk}\ge \frac{2C_{oss}{(V_{in}/3)}^2}{i_{p1}^2(t_5)}=\frac{2C_{oss}{V}_{in}^2}{9i_{p1}^2(t_5)}.$$

(19)

Similar, the necessary leakage inductance to achieve ZVS condition of S₂, S₄, and S₆ is expressed in (20).

$$L_{lk}\ge \frac{2C_{oss}{(V_{in}/3)}^2}{i_{p1}^2(t_1)}=\frac{2C_{oss}{V}_{in}^2}{9i_{p1}^2(t_1)}$$

(20)

Based on the zero-voltage condition in (19) and (20), the necessary leakage inductance can be calculated in (21).

$$L_{lk}\ge \max \{\frac{2C_{oss}{V}_{in}^2}{9i_{p1}^2(t_1)},\frac{2C_{oss}{V}_{in}^2}{9i_{p1}^2(t_5)}\}.$$

(21)

If the ripple voltage on dc blocking capacitors C₁~C₃ is less than 20% of the average voltage value, then the dc blocking capacitances C₁~C₃ are calculated as

$$C_1=C_2=C_3>\frac{5(1-d)I_o{T}_{sw}}{n{V}_{in}}.$$

(22)

4. Experimental Results

Experiments based on a laboratory prototype are provided to verify the effectiveness of the developed circuit. The input dc voltage V_in,min = 750 V and V_in,max = 800 V, the output voltage V_o = 24 V and the maximum load current I_o = 60 A. The switching frequency f_sw = 100 kHz. The circuit components of the laboratory prototype are summary in

Table 1. Prototype Circuit Parameters.

Items	Symbol	Parameter
Input voltage	Vin	750 V~800 V
Output voltage	Vo	24 V
Rated output current	Io	60 A
Switching frequency	fsw	100 kHz
Input capacitors	Cin1, Cin2, Cin3	180 μF/450 V
Voltage balance capacitors	Cf1, Cf2	2.2 μF/630 V
Power switches	S1~S6	2SK4124
Rectifier diodes	D1~D6	MBR40100PT
dc block capacitors	C1~C3	0.2 μF
Turns ratio of T1~T3	n1~n3	1.5 (33 turns/22 turns)
Leakage inductances	Llk1~Lr3	15 μH
Magnetizing inductances	Lm1~Lm3	0.6 mH
Output inductances	L1~L6	66 μH
Output capacitance	Co	4700 μF/50 V

. Figure 4 illustrates the picture of the laboratory prototype circuit. Figure 5 presents the test results of the gating signals of S₁, S₂, S₃, and S₅ under the rated power. The switches S₁ and S₂ have complementary gating signals, and S₁, S₃, and S₅ have identical pulse-width modulation signals. Figure 6 illustrates the test waveforms of the primary-side voltage v_ab and currents i_p1~i_p3 at the rated power. It is clear that the three primary-side currents i_p1~i_p3 are well balanced. The input split voltages and balance capacitor voltage at the rated power are measured and presented in Figure 7. The measured voltages are V_Cin1 = 251 V, V_Cin2 = 249.3 V, V_Cin3 = 249.7 V, V_Cf1 = 251 V, and V_Cf2 = 249 V under V_in = 750 V input. It is clear that the input split voltages and balance capacitor voltages are well balanced. Figure 8 presents the test results of the gating voltage and drain current of power switch S₁ under 20% output load, and the rated output load for both 750 V and 800 V input cases. Before the power switch S₁ is turned on, the drain current is a negative value, to discharge the drain voltage. Therefore, the soft switching characteristic of S₁ can be realized from 20% output load to the rated output load, based on the test results in Figure 8. Similarly, the measured waveforms of S₂ are presented in Figure 9. It can be observed that the zero-voltage switching characteristic of S₂ is also achieved from 20% output load. Since power devices S₃ and S₅ are operated in the same circuit manner as power device S₁, and S₄ and S₆ are controlled in the same circuit manner as S₂, it can be expected that the zero-voltage switching of power switches S₃~S₆ are all achieved from 20% output load. The secondary-side inductor currents and diode currents of first half bridge circuit are measured and presented in Figure 10a under the rated power. The output currents of three half bridge circuits under the full output power are illustrated in Figure 10b. The test results show the three output currents are well balanced. Figure 11 illustrates the measured efficiencies of the proposed circuit under different load conditions and input voltages. The measured circuit efficiencies of the developed converter are 91.5% at 20% rated power, 93.2% at 50% rated power, and 92.7% at the rated power under 750 V input. At 750 V input and the rated power, the duty ratio is close to 0.5, and the current rating on power devices and inductors are almost balanced. Therefore, the power losses are nearly distributed into each power devices and the circuit efficiency is improved, compared to the low load condition and higher voltage input.

5. Conclusions

A modular dc–dc converter with magnetic coupling current balance is presented for high power industry power units, dc light rail transportation, or dc microgrid system applications. Three half bridge circuits are employed in the proposed converter with primary-series secondary-parallel connection to lessen the voltage stress of power devices on high voltage side and current stress of passive components on low voltage side. Balance capacitors are used on high voltage side to achieve voltage balance on input split capacitors. In order to achieve current balance of three half bridge circuits, magnetic coupling current balance components are employed on the primary-side. The current doubler rectifiers are used on low voltage side to achieve partial ripple current reduction. Asymmetric pulse-width modulation approach is used to control power switches and regulate load voltage. From the experimental results, all power switches can be turned on at zero voltage from 20% output power. The other dc–dc converter topologies, such as full-bridge converter with phase-shift pulse-width modulation and resonant converter with frequency control, can also be applied in the proposed modular dc–dc converter with series-parallel connection with currents sharing and split voltages balance. Full-bridge circuit has two times of switch counts compared to the half-bridge circuits in the proposed converter. That will increase the cost and converter size. The resonant converter with frequency modulation cannot be designed at the optimal condition due to the switching frequency being related to the load condition and input voltage. Based on the analysis of circuit characteristics in Section 3 and the test results, it can be observed that the main drawbacks of the proposed converter, with asymmetric pulse-width modulation scheme, are unbalanced current rating on power devices S₁~S₆ and D₁~D₆, and inductors L₁~L₆, due to the duty cycle being related to the load current and input voltage. Similar, the average voltages on dc blocking capacitors C₁~C₃ are also related to duty cycle. If the proposed converter is operated under duty cycle equals 0.5, then the current rating of all power devices and inductors are balanced.