A Compact On-Chip Ka-Band Bandpass Filter Using Folded Crossed Interdigital Coupling Structure

Abstract

This paper proposes a millimeter-wave miniature on-chip bandpass filter (BPF) implemented using a 0.18 μm CMOS process. To address the issues of insufficient coupling capability, limited control of transmission zeros, and excessive chip area in traditional on-chip filters, a folded cross-interdigital coupling structure is proposed to enhance coupling efficiency and reduce size. The design incorporates metal–insulator–metal (MIM) capacitors to increase the coupling capacitance between resonators without increasing the area, and utilizes a defected ground structure (DGS) to modify the current distribution at the ground plane, generating additional transmission zeros to improve selectivity. An LC equivalent circuit model was established and verified through full-wave electromagnetic simulation, and the design was validated through chip fabrication and on-wafer measurements. The measurement results show an insertion loss of 3.36 dB and a fractional bandwidth of 49.1% at 32 GHz, with two transmission zeros. The core dimensions are 0.25 mm × 0.18 mm. This design achieves a good balance between miniaturization, selectivity, and insertion loss, making it suitable for millimeter-wave SoC applications.

1. Introduction

As RF wireless systems continue to move to higher frequencies, wireless communication systems must be able to handle a variety of high-frequency circuit signals [1,2,3]. Demand is increasing for high-frequency circuit devices in the millimeter wave area, which provides a wide range of broadband applications for high-speed wireless communication systems. Bandpass filters are key components, which often require high selectivity and low insertion loss (IL). The requirements for filters are low cost, compact structure, and easy system integration [4,5,6].

The millimeter-wave radio frequency integrated circuit (RFIC) chip presented as a wafer module has attracted considerable attention [7,8]. Implementing passive components together with active circuits on a chip not only improves system integrity, but also avoids the use of complex packaging techniques to increase reliability [9,10]. Among the passive components, the filter is an essential component in the RF front-end circuit, and the bandpass filter is an important basic component in the transmitter and receiver. Therefore, the filter is mainly used to reduce noise and suppress interference signals outside the system. In the technical literature, several studies of bandpass filters have been published, such as filters made by substrate synthesized waveguide (SIW) [11,12,13,14], filters designed with defected ground structure (DGS) [15,16,17] and filters implemented in the complementary metal oxide semiconductor (CMOS) process for microelectromechanical systems (MEMS) technology [18,19]. Based on the aforementioned studies, various filter implementations exhibit inherent trade-offs among performance, size, and integration capability. SIW-based filters typically achieve high quality factor and low insertion loss owing to their waveguide-like characteristics; however, their relatively large footprint limits their suitability for highly integrated RFIC applications. DGS-based designs enhance selectivity and stopband suppression by perturbing current distributions, but at the cost of increased radiation loss and design complexity, particularly at millimeter-wave frequencies. In contrast, CMOS-based and MEMS-integrated filters offer superior compactness and compatibility with system-on-chip integration. Nevertheless, their performance is often constrained by substrate losses and limited passive component quality, leading to reduced quality factor and increased insertion loss. Consequently, the realization of a compact on-chip bandpass filter that simultaneously achieves wide bandwidth, low insertion loss, and high integration compatibility in standard CMOS technology remains a challenging problem. This motivates the development of advanced design methodologies to address these conflicting requirements.

On-chip bandpass filters implemented in CMOS processes typically have low quality factors due to the effects of conductor loss and substrate coupling. In millimeter-wave applications, particularly in wideband designs, the Q-factor is usually below 5, and insertion loss typically falls within the range of 2–5 dB, varying with the degree of miniaturization and process conditions. Current on-chip filters can be broadly categorized into transmission line structures, lumped-element designs, and miniaturized topologies with enhanced coupling. Transmission line filters, while offering higher Q-factors and lower insertion loss, are relatively large in the millimeter-wave band, which hinders high integration. Lumped-element designs can effectively reduce size but are limited by insufficient coupling capability and parasitic effects; enhanced-coupling designs can improve bandwidth and selectivity but are typically accompanied by increased design complexity or loss. In CMOS millimeter-wave design, simultaneously achieving miniaturization, strong coupling, controllable transmission zeros, and reasonable insertion loss remains a key challenge.

Millimeter-wave bandpass filter devices have received particular attention in recent years, but their design requires evaluation of insertion loss, operating bandwidth, band rejection, and die size, making millimeter-wave filter design a major challenge today.

By miniaturizing passive components, it helps to reduce die size, but it also helps to reduce conductor loss and optimize overall insertion loss. Many studies have proposed design methods for miniaturization of lumped elements [20,21,22]. The most important point of this method is to use the metal stack of the wafer to enhance self-coupling. On the design side, in order to reduce the microstrip line distribution and bandpass filter area, metal–insulator–metal (MIM) capacitors are added in the middle of the multimode resonators [23,24] or defected ground structures are used to reduce insertion losses [25,26,27]. The chip filter circuit size is reduced by folding the microstrip resonator [28,29,30]. However, it can also sacrifice insertion loss, return loss, or stopband suppression.

Conventional on-chip filters suffer from insufficient coupling capability, limited control over transmission zeros, and excessive chip area. This study proposes a miniature Ka-band on-chip bandpass filter implemented using a 0.18 μm CMOS process. It employs a folded-cross interdigital structure combined with MIM capacitors to enhance coupling capability while reducing the chip area. Furthermore, a defected ground structure (DGS) is introduced to generate additional transmission zeros and improve selectivity. The design has been verified through LC modeling, electromagnetic simulation, and measurement, achieving a good balance between size, bandwidth, and insertion loss, making it suitable for millimeter-wave SoC applications.

2. Design and Implementation of the Interdigital-Type BPF

2.1. Overview of the BPF

The layout of the proposed chip millimeter wave passive element integrated with the bandpass filter is shown in Figure 1. Figure 2 depicts this design using standard 0.18 μm CMOS technology, providing six metal layers, denoted by M1-M6 from bottom to top. The height of the silicon substrate is 500 μm, the dielectric constant is 11.9, and the dielectric constant of S_iO₂ is 4.0. The resonator and feeding line of the filter are constructed in M6, which has the largest thickness and has lower conduction loss. The grounding layer is selected at M1, when the maximum height of the substrate between the two layers can reduce the conduction loss. The additional MIM capacitor layer is located between M1 and M5.

The bandpass filter is composed of crossed interdigital-type resonators, as shown in Figure 3. The folding and overlapping are used to reduce the size. The end and middle branches of the resonator are loaded by MIM capacitors, while the branch near the feed-through end is connected to ground using a through-hole (VIA) from M1 to M6. These layers are connected to the open end of the resonator and to the ground layer through vias. A defected ground structure is etched below the resonator to improve performance.

2.2. LC Equivalent Circuit Model of the BPF

The designed lossless LC equivalent circuit model of RF CMOS Ka-Band bandpass filter is in Figure 4. The LC circuit model consists of four combinations: The first is the series circuit of $L_1$, $C_1$, and $R_1$. The second is the series circuit of $L_2$ and $C_2$. The third is the defected ground structure effect of $L_3$, $C_3$, and $R_1$. And the fourth is the high-frequency coupling of the parallel branch of $L_4$ and $C_4$. Since the transmission zeros (TZs) are able to be adjusted by the defected ground structure, the mathematical formula for the TZs can be derived as in (1).

$$f_{TZ}={\displaystyle \frac{1}{2\pi \sqrt{L_3{C}_3}}}$$

(1)

The resonant frequency $f_0$ of the BPF can be determined by $L_1$ and $C_1$. The relationship between $f_0$, $L_1$ and $C_1$ can be represented by 3-D mapping as shown in Figure 5. It can be observed that the lower values of $f_0$ occur at the larger values of $L_1$ and the larger values of $C_1$. Finally, the resonant frequency can be determined by adjusting $L_1$ and $C_1$.

The coupling coefficient k between resonators can be expressed in terms of the resonance frequencies of the even and odd modes as [31]

$$k={\displaystyle \frac{f_{even}^2-f_{odd}^2}{f_{even}^2+f_{odd}^2}}$$

(2)

where $f_{even}$ and $f_{odd}$ represent the resonance frequencies of the coupled resonators under even-mode and odd-mode excitation conditions, respectively. Even and odd modes correspond to cases where the electric field distributions between the resonators are in phase and out of phase, respectively; the difference in their frequencies reflects the coupling strength between the resonators. Therefore, the coupling coefficient k can be used to quantify the strength of the interaction between the coupled resonators. From a circuit perspective, the coupling coefficient is directly related to the equivalent coupling capacitance between adjacent resonators. By introducing metal–insulator–metal (MIM) capacitors in the overlapping region, the equivalent coupling capacitance can be effectively increased, thereby enhancing the coupling strength between resonators. This effect can be observed in the parametric analysis shown in Figure 5, Figure 6, Figure 7 and Figure 8; changes in capacitance values have a significant impact on the bandwidth and the location of the transmission zero.

The LC equivalent circuit was then verified by the Advanced Design System (ADS). Figure 6 shows the bandwidth of the Ka-band bandpass filter architecture design with 52.3% fractional bandwidth (FBW) (from 24.8 to 42.4 GHz). The transmission zero of the lower resistance band is at 14.4 GHz, which can suppress the low frequency band by 30 dB. This provides good suppression in the low-orbit satellite band and the sub-6 GHz band.

To further analyze the proposed bandpass filter design architecture, the equivalent circuit model is investigated by ADS 2023 for the parameters. The analysis of the transmission zero is performed for the bandpass filter in Figure 7. When $L_3$ = 0.17 nH and $R_1$ = 300 ohms, the transmission zero point of the lower resistance band can be adjusted from 15.6 to 13.2 GHz with the value of $C_3$ from 0.14 to 0.20 pF, while the transmission zero of the upper resistance band is almost unchanged. Therefore, when the value of $C_3$ becomes larger, the transmission zero point will move to a lower frequency. Similarly, the transmission zero for higher frequencies can be adjusted by $L_2$ and $C_2$. As shown in Figure 8, when $L_2$ = 0.097 nH, the transmission zero point of the upper band can be adjusted from 51.5 to 66.7 GHz as the value of $C_2$ changes from 0.057 to 0.097 pF. The transmission zero of the lower band remains unchanged.

2.3. Implementation of the BPF with DGS

The DGS can create a new transmission zero at the edge of the passband and improve performance through additional coupling. This design takes advantage of this additional coupling to improve insertion loss. The DGS improves the magnetic and electrical coupling between the resonators.

Electrical coupling is also improved due to the reduced coupling between the ground plane and the resonator.

Figure 9a shows the interdigital-type bandpass filter without DGS, and Figure 9b shows the ground structure by introducing a rectangular defect below the coupling resonator. Comparing the effect of the ground structure with and without the defect on the electromagnetic simulation in Figure 9c, the bandpass filter has a similar ratio bandwidth and an improvement from 14 to 9 dB in insertion loss. In addition, due to the variations in the effective capacitance and inductance of the circuit, a new transmission zero point is formed at 60 GHz.

To demonstrate the validity of the filter, the circuit structure model has to be converted into a specific physical layout. The proposed bandpass filter layout is a symmetric structure consisting of feed-in transmission lines, interleaved interdigital-coupled resonators, MIM capacitors, and defected ground. The final proposed design layout of the Ka-band bandpass filter is shown in Figure 10, and the alignment width is unified to 10 μm.

Figure 11 illustrates the bandwidth of the electromagnetic simulation and the LC equivalent circuit simulation for the Ka-band bandpass filter proposed in Figure 4, and it can be seen that the electromagnetic simulation has an FBW of 53.4% from 24.8 to 42.9 GHz, while the transmission zero of the lower resistance band remains the same as the LC equivalent circuit at 14.8 GHz. However, the insertion loss is reduced from 1.47 to 2.69 dB, which is the result of the difference caused by the effect of the silicon substrate, but it does not affect the functionality.

3. Bandpass Filter Fabrication and Measurement Results

The designed bandpass filter is fabricated with TSMC 0.18 μm CMOS technology. Figure 12a shows the chip of the interleaved interdigital-type bandpass filter with a core size of 0.25 mm × 0.18 mm. If a probe test point is included, the size is 0.28 mm × 0.48 mm. The probe spacing used for measurement is 100 μm. Figure 13 shows the measurement environment using an Agilent E8257D vector network analyzer (Agilent Technologies, Santa Clara, CA, USA), which provides measurements up to 67 GHz, as shown in Figure 14. The electromagnetic simulations and measurements show good agreement. The bandpass filter measured an insertion loss of 3.36 dB at 32 GHz, with a passband band from 25.0 GHz to 41.3 GHz and an FBW of 49.1%. There is a small variation between simulation and measurement, which may be due to probe measurement errors or manufacturing tolerances. The quality factor of this filter is evaluated based on the measured center frequency and bandwidth; with a center frequency of 32 GHz and a bandwidth of 16 GHz, its loaded Q is approximately 2.

The measured S-parameters are not de-embedded and include the effects of probing pads and access interconnections. These parasitic effects may contribute to additional insertion loss, but the impact is limited due to the compact layout.

The performance of the fabricated bandpass filters and several CMOS chip bandpass filters recently proposed in the literature are summarized in

Table 1. Comparison of recent research on chip bandpass filter.

Ref	Technology	fc (GHz)	Fractional Bandwidth (%)	IL (dB)	No. of TZs	Core Size (mm2)	Core Size (λ2)	Q-Factor
Proposed	0.18 μm CMOS	32	49.1	3.36	2	0.045	$5.12\times {10}^{-4}$	2
[10]	0.13 μm BiCMOS	26.5	50.9	3.8	-	0.1755	$1.37\times {10}^{-4}$	1.96
[23]	0.13 μm BiCMOS	27 29	17.5 26.7	2.5 3.5	-	0.022 0.028	$1.78\times {10}^{-4}$ $2.62\times {10}^{-4}$	5.71 3.75
[24]	0.13 μm BiCMOS	18	66.7	2.9	3	0.176	$6.34\times {10}^{-4}$	1.5
[29]	0.13 μm BiCMOS	23 26.6	78 70	2.3 2.6	-	0.148 0.066	$8.7\times {10}^{-4}$ $5.19\times {10}^{-4}$	1.28 1.43
[32]	45 μm CMOS	33	66.7	1.5	4	0.07	$8.47\times {10}^{-4}$	1.5
[33]	0.13 μm BiCMOS	23	16.7	3.8	1	0.017	$1.0\times {10}^{-4}$	5.99
		31	11.4	3.2	2	0.024	$2.56\times {10}^{-4}$	8.77
		31	17.5	2.7	2	0.044	$4.7\times {10}^{-4}$	5.71
[34]	0.13 μm GaAs	67.5	35.3	1.7	-	0.586	$2.97\times {10}^{-4}$	2.83

. The proposed design has successfully demonstrated a good balance between compactness, selectivity and in-band insertion loss level. The smaller size achieved by the defected ground structure design is more dimensionally advantageous compared to [10,24,29,32]. In addition, the bandpass filter has lower or equivalent insertion loss compared to [10,23,33]. Due to the lossy silicon substrate and ohm loss, the silicon-based BPF has a higher insertion loss compared to the filter implemented in [34], but the overall size of the proposed bandpass filter is much smaller.

4. Conclusions

A compact interdigital-coupled bandpass filter implemented in 0.18 μm CMOS technology is presented. Interleaved, overlapped and defected ground structures are utilized to produce compact size, small insertion loss and highly selective filter performance. The DGS generates transmission zeros at lower frequencies. Reasonable agreement is obtained between the electromagnetic simulation and measurement results.

The results illustrate that a small insertion loss of 3.36 dB is achieved over 25.0 to 41.3 GHz with a chip size (without probe test points) of only 0.045 mm². The achieved results demonstrate the possibility of design miniaturization and the proposed aggregate component approach is very suitable for chip bandpass filters.

The performance is mainly affected by substrate loss, process variations, and increased parasitic effects at higher frequencies, which may limit the achievable quality factor and introduce deviations between simulation and measurement. Despite these inherent limitations of CMOS-based millimeter-wave implementations, the proposed design maintains stable filter characteristics and demonstrates its effectiveness for compact on-chip bandpass filter applications.