Dual-Layer Multi-Port High-Gain DC-DC Power Converter with Hybrid Voltage/Current Distribution Strategy

Abstract

In light of the global issue of “Carbon Neutrality”, a high proportion of renewable energy integrated into modern power systems has become the key to energy strategic transformation, which has escalated the demand for high-gain, high-power converters for DC energy conversion. In this paper, a non-isolated double-layer multi-port parallel-connected high-gain DC–DC conversion system has been proposed. The system consists of two energy layers: the upper layer is designed as a non-isolated high-gain three-port DC conversion topology, which includes two energy inputs and one output port, and the bottom layer is a three-port constant current output module. The output ports of these layers are connected in parallel, while the input ports are independent. Thus, both high output voltage gain and power capacity were fulfilled for the renewable power application condition. The system is capable of operating in both input-parallel–output-parallel (IPOP) and multi-input–independent-output-parallel (MIIOP) modes, thereby enabling multi-port high-gain DC power conversion. Detailed analysis of the operation strategies under a switching cycle for both energy layers is presented. A small signal was introduced to establish the mathematical model of both energy topologies. In order to simultaneously regulate the output voltage and achieve dynamic current sharing between the layers, an adaptive current-sharing control strategy was developed based on the established system models. The proposed control strategy can control the output voltage through the upper-layer topology and dynamically allocates output current between the layers based on the output power level, which will effectively enhance the system’s power rating. The simulation mode was built in the PSIM environment, open-loop simulations were carried out for obtaining system characteristics, and closed-loop simulations were conducted for control efficiency validation. Finally, a 2000-W experimental prototype was developed based on the digital control center dsPIC33FJ64GS606. Open-loop and closed-loop experiments were carried out for system performance evaluation. Both simulation and experimental results successfully evaluated the power transfer performance and control system performance of the proposed system, and a peak efficiency of 95.7% under 10 times voltage gain was achieved.

1. Introduction

The escalating severity of global environmental issues, coupled with relentless growth in energy demand, has compelled countries worldwide to vigorously promote the development of renewable and clean energy [1]. This effort aims to address the dual challenges of ensuring a sustainable energy supply and mitigating environmental degradation. In this context, applications such as grid-connected photovoltaic systems, electric vehicle fast charging, and data center power supplies are imposing increasingly stringent requirements on the design of DC–DC converters, particularly necessitating high voltage gain and high-power capacity [2,3]. DC–DC converters can be broadly classified into two structural types: isolated and non-isolated. Isolated converters generally employ isolation devices, such as transformers, to provide electrical isolation between ports, which effectively enhances system safety [4]. However, this approach inevitably increases the system volume and cost. In contrast, non-isolated converters offer higher integration density and improved overall system efficiency [5]. As voltage levels in renewable energy power systems continue to rise and requirements for system power density become more stringent, conventional Boost converters face limitations due to the maximum duty cycle constraint of their switching devices. Achieving high voltage gain often necessitates the use of multi-stage cascaded architectures. However, such configurations require the entire power to be processed through each sequential stage, which adversely affects the overall power handling capability of the converter [6]. In response to these challenges, significant research efforts have been devoted in recent years to the co-optimization of voltage gain and power capacity in DC–DC converters. In the domain of boost converter topology optimization, current research efforts are predominantly concentrated on advancements in coupled inductors and hybrid topological configurations. Studies cited in [7,8,9] utilize coupled inductor techniques to achieve higher output voltage gain. Nevertheless, these topologies exhibit discontinuous input current characterized by pulsed waveforms, and the voltage spikes induced by leakage inductance pose persistent challenges for effective suppression. In response to these limitations, the approaches presented in [10,11] integrate switched-capacitor networks to augment voltage gain while concurrently harnessing and recycling leakage energy via capacitors. This mechanism facilitates zero-voltage switching (ZVS) turn-on of the power switches, thereby contributing to improved converter efficiency. A hybrid switched-capacitor topology was proposed in [12], which employs a multilevel structure to achieve high voltage gain while maintaining low voltage stress across power devices and sinusoidal input currents. Similarly, the resonant switched-capacitor converter presented in [13] achieves a high voltage gain with a reduced number of switches and enables zero-voltage switching (ZVS) and zero-current switching (ZCS), thereby improving efficiency and reducing switching losses. In addition, isolated high-gain converters based on resonant switched-capacitor structures have also been investigated. The topology proposed in [14] integrates a switched-capacitor boosting unit with an isolated transformer stage, providing both high voltage gain and electrical isolation, which makes it suitable for sustainable energy applications such as electric vehicles and wind energy systems. Moreover, research in [15] proposed a switched-capacitor-based high-gain converter with a reduced number of switches and lower voltage stress on semiconductor devices, which contributes to improved converter efficiency and reduced system cost. However, despite these advantages, switched-capacitor-based converters still suffer from several inherent limitations. The use of multiple capacitors may increase circuit complexity and component count, which can negatively affect system reliability and power density. In addition, the charging and discharging processes of capacitors often lead to large current spikes and increased conduction losses.

Furthermore, interleaved parallel architectures introduced in [16,17] reduce dependence on large passive filters and high switching frequencies for ripple mitigation, leading to enhanced overall efficiency. Although these refined methodologies have yielded notable progress in achieving elevated voltage gains, conventional single-converter structures continue to demonstrate inadequate performance in high-power industrial applications. Regarding system architecture, current research efforts have largely concentrated on the refinement of Input-Parallel Output-Series (IPOS) configurations. A multi-port architecture introduced in [18] facilitates multi-source integration and hybrid voltage/power regulation. However, its closed-loop control scheme exhibits considerable complexity, and its stability necessitates further verification. The Sigma converter topology presented in [19] comprises an upper LLC resonant stage operating as a DC transformer (DCX) with a fixed voltage conversion ratio, combined with a lower Buck converter stage that provides dynamic output voltage compensation through duty cycle modulation. Expanding on this concept, the work in [20] developed a high-efficiency, high-gain IPOS-based converter architecture supporting dynamic voltage adjustment. Additionally, ref. [21] resolved the fundamental compatibility issue preventing conventional non-isolated high-gain converters from being deployed in IPOS arrangements through the integration of non-isolated high-gain modules and their symmetric topological derivatives, resulting in a substantial improvement in overall voltage gain. Collectively, these hybrid strategies offer insightful guidance for system-level advancements in DC–DC power conversion.

This paper proposes a non-isolated dual-layer multi-port parallel high-gain DC–DC power conversion system. The proposed architecture consists of two power stages: the upper layer employs a multi-port high-gain DC topology to achieve a high voltage boost ratio, while the lower layer adopts a multi-port current-mode DC topology to realize output current sharing. This configuration not only satisfies the high-gain requirement for renewable energy integration but also improves the overall power handling capability under high-gain operating conditions. In addition, the system supports both Input-Parallel Output-Parallel (IPOP) operation and multi-input independent with output-parallel operation, enabling flexible multi-port high-gain DC power conversion. To verify the feasibility of the proposed architecture and control scheme, detailed theoretical analysis, simulation studies, and experimental validation are carried out. The main contributions of this paper are summarized as follows:

• A novel non-isolated dual-layer multi-port high-gain DC–DC converter topology is proposed. Unlike conventional single-stage high-gain converters, which suffer from limited power capacity and high device stress, the proposed architecture decouples voltage boosting and power sharing into two coordinated layers. The upper layer achieves high voltage gain, while the lower layer enables flexible current sharing among input ports. This dual-layer structure effectively enhances both voltage conversion capability and system power scalability.
• An adaptive current-sharing control strategy based on small-signal modeling is developed to regulate the output voltage and dynamically distribute current between the two layers. Compared with conventional control methods that focus only on voltage regulation or fixed current sharing, the proposed strategy enables coordinated voltage regulation and real-time current allocation according to load conditions. A 2000 W experimental prototype controlled by a dsPIC33FJ64GS606 digital controller is built to validate the proposed topology and control scheme, achieving a peak efficiency of 95.7%.

The remainder of this paper is organized as follows. Section 2 presents the converter framework and the overall control system structure. Section 3 provides a detailed analysis and modeling of the proposed system, including the operating modes of the upper-layer topology, the voltage and current stresses of switching devices, and the analysis of the lower-layer topology. Section 4 describes the design of the control system for both the upper-layer and lower-layer topologies. Section 5 presents the simulation studies carried out in PSIM to evaluate the open-loop and closed-loop performance of the proposed converter. Section 6 reports the experimental results obtained from a laboratory prototype, including steady-state characteristics, dynamic responses under input voltage disturbances and load transients, as well as efficiency evaluation. Finally, Section 7 concludes the paper.

2. Analysis of the Converter Framework and Control System Structure

This paper presents a parallel Input-Parallel Output-Parallel (IPOP) high-step-up, high-power converter, the schematic of which is illustrated in Figure 1. The converter employs a dual-layer stacked architecture, where in the input side incorporates a parallel configuration to accommodate DC sources at various voltage levels, and the output side utilizes a parallel-connected structure for power delivery. The upper-layer topology functions in voltage-source mode, whereas the lower-layer topology operates in current-source mode. Dynamic current sharing is realized via the lower-layer topology, which distributes the output current I, from the upper layer at an arbitrary ratio, thereby enabling flexible power allocation between the two stages.

The upper layer of the converter employs a dual-input high-step-up topology designed to significantly increase the overall voltage boost ratio. The first input unit is composed of inductors $L_1$ and $L_2$, capacitor $C_1$, switching transistors $S_{1a}$ and $S_{1b}$, and diode $D_1$. Similarly, the second input unit incorporates inductor $L_3$, capacitor $C_2$, switching transistor $S_2$, and diode $D_3$. Transistors $S_{1a}$ and $S_{1b}$ operate synchronously under a duty cycle of $d_1$, whereas the turn-on instant of $S_2$ is delayed by $d_1{T}_s$ with respect to $S_1$, operating at a duty cycle of $d_2$, where $T_s$ represents the switching period.

A dual-loop control strategy is implemented using the inductor current $I_{L1}$ as the inner control loop and the output voltage $V_o$ as the outer loop. This configuration not only ensures dynamic voltage regulation but also improves the system’s resilience to external disturbances. The lower layer of the converter employs a single-inductor multiple-input topology. Its input stage comprises two parallel-connected input units, each consisting of a switch and a diode. The switches, denoted as $S_{3a}$ and $S_{3b}$, are synchronously controlled via closed-loop regulation of the inductor current $I_{L4}$. This current, $I_{L4}$, acts as a constant current source (CSM) for the output unit, imposing no specific constraints on switching timing. The control system is enhanced with a lower-layer adaptive current-sharing controller, building upon the existing upper-layer dual-loop control structure. A global reference is established by taking N times the ratio of the upper-layer output current $I_1$ to the duty cycle $d_4$ of switch $S_4$. This reference enables independent high-bandwidth current-sharing control of the lower-layer output units. A disturbance observer (DOB) is incorporated into the current-sharing controller and embedded directly within the current-sharing loop. By dynamically compensating the PI controller parameters, the DOB adaptively adjusts the control action, effectively mitigating inherent dynamic current-sharing challenges in parallel-connected architectures. The proposed parallel structure offers superior flexibility: the upper-layer topology regulates the output voltage, while the lower layer shares the upper-layer current at an arbitrary ratio, resulting in enhanced dynamic performance. Moreover, the converter exhibits considerable scalability. From the perspective of port count, both the upper- and lower-layer topologies can be extended to incorporate additional input sources through the integration of more input units. In terms of operational modes, the converter is capable of operating not only in Input-Parallel Output-Parallel (IPOP) mode but also with multiple independent input ports and a parallel output configuration, thereby facilitating high-gain DC power conversion across multiple ports.

3. Analysis and Modeling of the Proposed System

Figure 2 depicts the proposed high-step-up upper-layer topology. In contrast to most coupled-inductor-based non-isolated topologies, the proposed structure not only achieves high voltage gain but also significantly reduces the voltage stress on both the switching devices and diodes. Within the overall converter system, this topology primarily serves as a voltage source that enhances the voltage conversion ratio.

3.1. Analysis of Operating Modes in the Upper-Layer Topology Based on Switching Period

In DC microgrids and emerging power system applications, power converters predominantly operate in Continuous Conduction Mode (CCM) for the inductor current. Under this operating condition, the upper-level topology exhibits three distinct operating states, which are determined by the combinations of duty cycles of switches $S_{1a}$, $S_{1b}$, and $S_2$. Specifically, the duty cycles of $S_{1a}$ and $S_{1b}$ are denoted as $d_1$, while that of $S_2$ is designated as $d_2$. A hybrid control strategy integrating Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) is employed. The switching period and switching frequency are represented as $T_s$ and $f_s$, respectively. Based on the switching sequence depicted in Figure 3, a time-domain model for this topology can be derived. The energy transfer paths of the upper-level topology in each operating state are illustrated in Figure 4. Furthermore, the time instants $t_1$, $t_2$, and $t_3$ in Figure 3 satisfy the following relationships with the switch duty cycles:

$$\left\{\begin{array}{cc}\hfill t_1& =(d_1+d_2-1)T_s\hfill \\ \hfill t_2& =d_1{T}_s\hfill \\ \hfill t_3& =T_s\hfill \end{array}\right.$$

(1)

Mode 1 $[0,t_1]$: During this interval, all switches ($S_{1a}$, $S_{1b}$, and $S_2$) remain in the on-state. Energy from the DC input source is stored in the inductors. Specifically, inductor $L_1$ is charged directly by the input voltage source $V_1$ through switch $S_{1a}$, while inductor $L_2$ is charged by capacitor $C_1$ via the conduction path formed by switches $S_{1a}$ and $S_{1b}$. The output power delivered to the load is supplied exclusively by the output capacitor $C_{o1}$. The equivalent circuit diagram representing the power flow in this operating mode is shown in Figure 4a. The dynamical behavior of the circuit during this mode is characterized by the following equations:

$$\left\{\begin{array}{c}{v}_{L_1}=V_1\hfill \\ v_{L_2}=v_{C_1}\hfill \\ v_{L_3}=V_2\hfill \end{array}\right.$$

(2)

Mode 2 $[t_1,t_2]$: During this interval, switches $S_{1a}$ and $S_{1b}$ maintain their on-states, whereas $S_2$ is turned off. The input source $V_1$ supplies energy to inductor $L_1$, while capacitor $C_1$ charges inductor $L_2$. Simultaneously, energy from both input source $V_2$ and the stored energy in inductor $L_3$ is transferred to capacitor $C_2$ via diode $D_3$ and switches $S_{1a}$ and $S_{1b}$. The output capacitor $C_{o1}$ continues to supply power to the load. The equivalent power circuit corresponding to this operating mode is illustrated in Figure 4b. The dynamical behavior of the circuit during this mode can be described by the following equations:

$$\left\{\begin{array}{c}{v}_{L_1}=V_1\hfill \\ v_{L_2}=v_{C_1}\hfill \\ v_{L_3}=V_2-v_{C_2}\hfill \end{array}\right.$$

(3)

Mode 3 $[t_2,t_3]$: During this interval, switch $S_2$ is in the on-state, whereas switches $S_{1a}$ and $S_{1b}$ remain off. The input source $V_1$, together with the energy previously stored in inductor $L_1$, charges capacitor $C_1$ through diode $D_1$. Concurrently, energy from the input source $V_2$, along with the stored energies in inductors $L_1$, $L_2$, and capacitor $C_2$, is delivered to the load through diodes $D_1$ and $D_2$. Meanwhile, input source $V_2$ supplies energy to inductor $L_3$, thereby charging it. The equivalent power circuit corresponding to this operating mode is presented in Figure 4c. The dynamical characteristics of the circuit during this mode are described by the following set of equations:

$$\left\{\begin{array}{c}{v}_{L_1}=V_1-v_{C_1}\hfill \\ v_{L_2}=v_{C_1}+v_{C_2}-V_o\hfill \\ v_{L_3}=V_2\hfill \end{array}\right.$$

(4)

Based on the principle of volt-second balance, the following system of equations is derived:

$$\left\{\begin{array}{c}{d}_1{V}_1+(1-d_1)(V_1-v_{C_1})=0\hfill \\ d_1{v}_{C_1}+(1-d_1)(v_{C_1}+v_{C_2}-V_o)=0\hfill \\ (d_1+d_2-1)V_2+(1-d_2)(V_2-v_{C_2})+(1-d_1)V_2=0\hfill \end{array}\right.$$

(5)

By simplifying Equation (5), the following expression can be obtained:

$$v_{C_1}={\displaystyle \frac{V_1}{1-d_1}}$$

(6)

$$V_o={\displaystyle \frac{v_{C_1}}{1-d_1}}+v_{C_2}$$

(7)

$$v_{C_2}={\displaystyle \frac{V_2}{1-d_2}}$$

(8)

By substituting Equations (6) and (8) into Equation (7), the functional relationship between the output and input voltages can be derived as follows:

$$V_o={\displaystyle \frac{V_1}{{(1-d_1)}^2}}+{\displaystyle \frac{V_2}{1-d_2}}$$

(9)

The proposed converter demonstrates significant scalability in its upper-level structural design. The number of input channels can be expanded by incorporating additional fundamental units—composed of switches, inductors, diodes, and capacitors—into the peripheral circuitry of the existing input cells. A schematic representation of the extended input sources achieved through this modular expansion in the upper-level topology is illustrated in Figure 5. Building upon the modeling and analytical approach developed earlier for the dual-input configuration, the generalized voltage gain expression for the n-input mode can be formally derived through mathematical induction as follows:

$$V_o={\displaystyle \frac{V_1}{{(1-d_1)}^2}}+\sum _{i=2}^n{\displaystyle \frac{V_i}{1-d_i}}$$

(10)

where $V_i$ represents the input voltage of the i-th input unit, and $d_i$ denotes the duty cycle of the switch in the i-th input unit. The corresponding control strategy and switching signal generation mechanism are relatively straightforward.

3.2. Analysis of Voltage and Current Stresses on Switching Devices and Diodes

The voltage stresses imposed on the switching devices and diodes constitute key parameters for evaluating system stability and managing implementation costs. Based on the operational mode analysis presented in the preceding sections, the analytical expressions for the voltage stresses across these components under Continuous Conduction Mode (CCM) operation are derived as follows:

$$PI{V}_{S_1}=PI{V}_{D_1}=V_{C_1}={\displaystyle \frac{V_1}{1-d_1}}$$

(11)

$$PI{V}_{S_2}=V_o-V_{C_1}-V_{C_2}={\displaystyle \frac{d_1}{{(1-d_1)}^2}}{V}_1$$

(12)

$$PI{V}_{S_3}=V_{D_3}=V_{C_2}={\displaystyle \frac{V_2}{1-d_2}}$$

(13)

$$PI{V}_{D_2}=V_o-V_{C_2}={\displaystyle \frac{V_1}{{(1-d_1)}^2}}$$

(14)

As indicated by (11)–(14), the voltage stresses on switches $S_1$ and $S_3$ increase gradually with the duty cycle. However, the growth rate remains moderate and the absolute values are consistently maintained at relatively low levels. This characteristic provides a solid foundation for further performance enhancement and structural optimization of the input units. In contrast, the voltage stress on switch $S_2$ remains limited at lower duty cycles but exhibits a pronounced nonlinear increase as the duty cycle rises. Nevertheless, the overall stress magnitude remains within practically acceptable limits. As illustrated by the energy flow diagrams of the upper-level topology under different operating modes in Figure 4, the currents through the switching devices and diodes exhibit the same magnitude characteristics as their corresponding inductor currents. By utilizing this fundamental property, the current ripple expressions for inductors $L_1$, $L_2$, and $L_3$ can be analytically derived as follows:

$$\Delta i_{L_1}={\displaystyle \frac{d_1{V}_1}{L_1{f}_s}}$$

(15)

$$\Delta i_{L_2}={\displaystyle \frac{d_1{v}_{C_1}}{L_2{f}_s}}={\displaystyle \frac{d_1{V}_1}{(1-d_1)L_2{f}_s}}$$

(16)

$$\Delta i_{L_3}={\displaystyle \frac{d_2{V}_2}{L_3{f}_s}}$$

(17)

Let $I_{L1}$, $I_{L2}$, and $I_{L3}$ denote the average currents of inductors $L_1$, $L_2$, and $L_3$, respectively. The expressions for the maximum inductor currents can then be obtained as follows:

$$I_{L_{1max}}=I_{L_1}+{\displaystyle \frac{\Delta i_{L_1}}{2}}={\displaystyle \frac{V_o}{R{(1-d_1)}^2}}+{\displaystyle \frac{d_1{V}_1}{2L_1{f}_s}}$$

(18)

$$I_{L_{2max}}=I_{L_2}+{\displaystyle \frac{\Delta i_{L_2}}{2}}={\displaystyle \frac{V_o}{R(1-d_1)}}+{\displaystyle \frac{d_1{V}_1}{2(1-d_1)L_2{f}_s}}$$

(19)

$$I_{L_{3max}}=I_{L_3}+{\displaystyle \frac{\Delta i_{L_3}}{2}}={\displaystyle \frac{V_o}{R(1-d_2)}}+{\displaystyle \frac{d_2{V}_2}{2L_3{f}_s}}$$

(20)

Accordingly, the analytical expressions for the current stresses experienced by the switching devices and diodes are derived as follows:

$$I_{Stress-S_1}=I_{Stress-D_1}={\displaystyle \frac{V_o}{R{(1-d_1)}^2}}+{\displaystyle \frac{d_1{V}_1}{2L_1{f}_s}}$$

(21)

$$I_{Stress-S_2}=I_{Stress-D_2}={\displaystyle \frac{V_o}{R(1-d_1)}}+{\displaystyle \frac{d_1{V}_1}{2(1-d_1)L_2{f}_s}}$$

(22)

$$I_{Stress-S_3}=I_{Stress-D_3}={\displaystyle \frac{V_o}{R(1-d_2)}}+{\displaystyle \frac{d_2{V}_2}{2L_3{f}_s}}$$

(23)

Beyond voltage and current stress analysis, the frequency-dependent loss stress of switching devices demands critical attention in high-frequency, high-power applications. This necessity arises from the pronounced frequency sensitivity of both switching losses $P_{sw}$ and conduction losses $P_{co}$, which are directly affected by operational frequency fluctuations. The energy dissipated during a single switching transition can be formulated as

$$E_{sw}={\displaystyle \frac{PIV}{2}}{I}_{stress}(t_r+t_f)$$

(24)

where $t_r$ and $t_f$ denote the rise and fall times of the switch’s gate drive signal, respectively. $K_f$ denotes the frequency factor, which characterizes the skin effect and eddy current losses. The total switching loss stress can be expressed as:

$$P_{sw}=f_s·E_{sw}·K_f\left(f_s\right)$$

(25)

3.3. Analysis of the Lower-Level Topology

The lower-level stage of the proposed converter is implemented using a single-inductor multiple-input (SIMI) topology, depicted schematically in Figure 6. This architecture employs a parallel-input cell design, enabling scalable integration of input sources while maintaining consistent output performance. Within the overall converter system, this stage operates as a controlled current source, providing stable power processing under dynamic input variations. Given that the current source mode (CSM) cells require a constant current source input, the proposed topology can only operate under inductor current closed-loop control and lacks open-loop operational capability. The detailed design of the closed-loop controller will be elaborated in the following section.

4. Design of the Control System

A hierarchical control architecture is proposed for the two-layer converter system presented in this work, consisting of an upper-layer voltage–current dual-loop controller and a lower-layer current-sharing controller. The upper-level voltage controller is primarily responsible for regulating the output voltage and optimizing transient response, while the lower-level current sharing controller is primarily responsible for current and power distribution among the layers. The upper-layer controller adopts a cascaded control structure, where the inductor current $I_{L4}$ serves as the inner control loop and the output voltage $V_o$ forms the outer control loop. This configuration regulates the output voltage while improving the dynamic response of the system. The lower-layer current-sharing controller, which is also based on the inductor current $I_{L4}$, forms a closed-loop control system to achieve adaptive dynamic current sharing. Its primary function is to scale the upper-layer output current $I_1$ by a specified ratio, thereby enabling flexible power distribution within the converter. Moreover, natural decoupling between the two control layers is achieved through the variable $I_1$.

4.1. Design of the Upper-Level Topology Controller

For the high-gain upper-level topology, the primary control objective is output voltage regulation. The controller adopts a dual-loop control structure composed of an inner inductor current loop and an outer output voltage loop. The duty cycles of switches $S_{1a}$ and $S_{1b}$ ($d_1$) and switch $S_2$ ($d_2$) are set to the same value, i.e., $d_1=d_2=d$. In addition, the turn-on signal of $S_2$ is generated after the turn-on intervals of $S_{1a}$ and $S_{1b}$ have ended. This switching sequence effectively reduces the voltage stress across the switches, thereby improving the reliability of the control system. The block diagram of the closed-loop control system for the upper-level topology is illustrated in Figure 7.

Based on small-signal modeling theory, a frequency-domain model of the dual-loop control system is established. The transfer function from the duty cycle d to the average inductor current is derived as (26), while the transfer function relating the average output voltage to the average inductor current is expressed in (27). Using the system parameters, the Bode plots of the inner current-loop transfer function and the outer voltage-loop open-loop transfer function, both before and after PI controller compensation, are generated in MATLAB (version 2022b) and presented in Figure 8.

$$G_{I_{L}d}\left(s\right)={\displaystyle \frac{{\widehat{i}}_L\left(s\right)}{\widehat{d}\left(s\right)}}={\displaystyle \frac{V_1+V_2}{{(1-d)}^{2}R{C}_{o1}\left(s+\frac{1}{R{C}_{o1}}\right)}}$$

(26)

$$G_{V_o}\left(s\right)={\displaystyle \frac{{\widehat{V}}_o\left(s\right)}{{\widehat{I}}_L\left(s\right)}}={\displaystyle \frac{R}{1+sR{C}_{o1}}}$$

(27)

As shown in Figure 8, the uncompensated open-loop characteristics exhibit a relatively low low-frequency gain and a pronounced phase lag in the inner current-loop transfer function. Meanwhile, the outer voltage-loop open-loop transfer function shows an almost flat magnitude slope in the low-frequency region. These characteristics indicate insufficient dynamic response and limited stability of the original control system. To improve both the dynamic performance and stability, PI controllers are introduced to compensate the inner current loop and the outer voltage loop. The final controller parameters are selected as $K_p=0.79$ and $K_i=0.03$ for the current loop, and $K_p=0.21$ and $K_i=0.071$ for the voltage loop. Stability analysis of the compensated closed-loop system shows that the phase margins are ${49}^{\circ }$ for the current loop and ${50}^{\circ }$ for the voltage loop, while the gain margins of both loops are infinite. These results confirm that the designed control system satisfies the stability and dynamic response requirements.

4.2. Design of the Lower-Level Topology Controller

Due to the strong reliance of the lower-level topology on closed-loop regulation, small-signal modeling is not adopted for its analysis in this study. For the CSM cells, a direct relationship exists between the input current and the output current. Therefore, implementing closed-loop control directly on the inductor current $I_{L4}$ is sufficient to achieve current sharing at the system output. The corresponding control system configuration is illustrated in Figure 9.

When closed-loop constant current control is applied to all input units, the power absorbed by each input source is proportional to its input voltage value under the constant current regulation, as expressed by the following relationship:

$${\displaystyle \frac{P_{in1}}{P_{in2}}}={\displaystyle \frac{V_1{d}_3{I}_{L4}}{V_2{d}_3{I}_{L4}}}={\displaystyle \frac{V_1}{V_2}}$$

(28)

To achieve efficient parallel operation of the upper- and lower-level outputs, high current delivery capability, accurate current sharing among parallel paths, and flexible power distribution between the two layers, an adaptive active current-sharing strategy based on a global current reference is proposed in this work. The schematic flowchart of the proposed control strategy is illustrated in Figure 10.

The proposed strategy employs the product of the upper-level output current $I_1$ and N times the duty cycle $d_4$ of switch $S_4$ as a global reference, thereby enabling independent high-bandwidth current-sharing control of the inductor current $I_{L4}$ in the lower-level topology. The reference signal for the current-sharing controller is defined as follows:

$$I_{ref}\left[k\right]={\displaystyle \frac{N-1}{d_4}}{I}_1\left[k\right]+K_i\sum _{j=0}^k(I_{LA}\left[j\right]-{\overline{I}}_L\left[j\right])T_s$$

(29)

where k denotes the discrete-time index, $I_{LA}\left[j\right]$ is the inductor current of the considered lower-layer cell ${\overline{I}}_L\left[j\right]$ denotes the average inductor current of all lower-layer cells, $K_i$ is the integral gain of the PI controller, $T_s$ is the switching period, and N, denotes the desired current reduction factor associated with the upper-layer output current. The first term in (29) provides the global current reference derived from the upper-layer output current, while the second term represents the integral compensation of the current-sharing error, which is introduced to reduce the steady-state current mismatch among the lower-layer cells.

To estimate and compensate in real time for the equivalent disturbance $d_k$ caused by component variations such as inductor tolerances and mismatches in conduction resistance, a disturbance observer (DOB) is incorporated into the current-sharing control loop. By applying the circuit superposition theorem and analyzing the CSM cell under short-circuit conditions, the transfer function of the lower-level output stage can be derived based on the relationship between the inductor current and the duty cycle of the input-cell switches, as follows:

$$G_p\left(s\right)={\displaystyle \frac{I_2\left(s\right)}{d_3\left(s\right)}}={\displaystyle \frac{V_1{V}_2}{sL+R}}$$

(30)

Based on the preceding derivation, the nominal inverse model of the disturbance observer (DOB) after the Tustin transformation, together with the expression of the discrete filter Q, can be obtained as follows:

$$G_n^{-1}\left(z\right)={\displaystyle \frac{(2L_n+R_n{T}_s)+(R_n{T}_s-2L_n)z^{-1}}{V_1{V}_2{T}_s(1+z^{-1})}}$$

(31)

$$\left\{\begin{array}{cc}\hfill Q\left(z\right)& ={\displaystyle \frac{a(1+z^{-1})}{(1+a)+(1-a)z^{-1}}}\hfill \\ \hfill a& ={\displaystyle \frac{T_s}{2\tau }}\hfill \end{array}\right.$$

(32)

where $L_n$ and $R_n$ denote the nominal values of inductor $L_4$ and the output resistor R, respectively. The difference-equation forms of (31) and (32) can be written as follows:

$$u\left[k\right]={\displaystyle \frac{[(2L_n+R_n)I_1\left[k\right]+I_1{R}_n[k-1]-T_{s}u[k-1]]}{V_1{V}_2{T}_s}}$$

(33)

$$q\left[k\right]={\displaystyle \frac{a}{1+a}}(u\left[k\right]+u[k-1])-{\displaystyle \frac{1-a}{1+a}}q[k-1]$$

(34)

Thus, the estimated disturbance is obtained as

$${\widehat{d}}_k\left[k\right]=Q\left(z\right)\left[G_n^{-1}\left(z\right)u\left[k\right]-q\left[k\right]\right]$$

(35)

Furthermore, the control objective of the current-sharing controller is generated by a modified PI controller integrated with a disturbance observer (DOB), which can be expressed as follows:

$$\left\{\begin{array}{cc}\hfill d_k\left[k\right]& =K_p\left[k\right]e_k\left[k\right]+K_i\left[k\right]\sum _{j=0}^k{e}_k\left[j\right]\Delta T+{\widehat{d}}_k\left[k\right]\hfill \\ \hfill e_k\left[k\right]& =I_{ref}\left[k\right]-I_2\left[k\right]\hfill \end{array}\right.$$

(36)

The expression for adaptive adjustment of the PI parameters is given by

$$K_p\left[k\right]=K_{p0}+\alpha \left|e_k\left[k\right]\right|+\beta \left|{\displaystyle \frac{e_k\left[k\right]-e_k[k-1]}{T_s}}\right|$$

(37)

$$K_i\left[k\right]=\left\{\begin{array}{cc}{K}_{i0}\hfill & \left(\right|e_k\left[k\right]|<e_{kmax})\hfill \\ 0\hfill & \left(\right|d_k\left[k\right]|\ge d_{max}\&e_k·\mathrm{sgn}\left(d_k\right)>0)\hfill \end{array}\right.$$

(38)

In terms of parameter selection, the values are determined as follows: $\alpha$ is set to $0.1$ and $\beta$ to $0.05$ using the least-squares method, while the nominal values $L_n$ and $R_n$ are chosen as $L_{min}$ and $R_{max}$, respectively, in order to account for the worst-case operating conditions. The expression for the cutoff frequency of the Q filter is given by

$$f_c=min\left({\displaystyle \frac{1}{5}}{f}_s,{\displaystyle \frac{1}{2\pi ·0.1T_d}}\right)$$

(39)

where $T_d$ represents the system delay, which mainly consists of the control-loop delay. To account for device temperature variations and to suppress potential high-frequency instability of the converter, a second-order low-pass filter is adopted. Its transfer function is expressed as follows:

$$H_a\left(s\right)={\displaystyle \frac{f_s^2}{0.01s^2+0.707·\left(10f_s\right)s+1}}$$

(40)

To prevent converter and power system failures caused by circulating currents resulting from current-sharing failure, a current-sharing result verification mechanism is designed.

$${\delta }_k={\displaystyle \frac{\left|I_1-N\overline{I_2}\right|}{\overline{I_1}}}\times 100\%$$

(41)

The current-sharing accuracy is evaluated every ten switching cycles. If the deviation exceeds $2\%$, the converter is automatically shut down to ensure safe operation. Due to the presence of inductor tolerances, the nominal inverse model in (31) cannot perfectly cancel the transfer function in (30), which leads to estimation errors in the output of the disturbance observer (DOB). To alleviate this issue, an online inductance identification scheme is adopted to measure the inductor current ripple and estimate the inductance value in real time. The estimated inductance is then used to update $L_n$ in (31) through the recursive least-squares (RLS) algorithm:

$$L\left[k\right]=L[k-1]+\gamma \left(i_{L4}\left[k\right]-{\widehat{i}}_{L4}\left[k\right]\right)·d_3\left[k\right]$$

(42)

where $\gamma$ denotes the identification gain, and $i_{L4}\left[k\right]$ represents the predicted current obtained from the nominal model. To further compensate for parameter deviations, a tolerance factor is introduced into the nominal inverse model, resulting in a revised model that incorporates a tolerance-compensation term.

$$\eta ={\displaystyle \frac{L}{L_n}}$$

(43)

$$G_n^{-1}(z,\eta )={\displaystyle \frac{(2L_n\eta +R_n{T}_s)+(R_n{T}_s-2L_n\eta )z^{-1}}{V_1{V}_2{T}_s(1+z^{-1})}}$$

(44)

The introduction of DOB, adaptive PI, and RLS algorithms in the lower-level controller is primarily intended to improve current distribution accuracy, disturbance rejection, and robustness to parameter changes, rather than to directly improve voltage transient response.

5. Analysis of Simulation Results for the Parallel Dual-Mode DC–DC Converter Based on PSIM

To validate the feasibility of the proposed converter topology, the effectiveness of the designed control system, and the dynamic performance of the parallel architecture under input-voltage and load disturbances typically encountered in photovoltaic applications, simulations were carried out using the power electronics simulation software PSIM (version 2023). Both open-loop sweep analysis and closed-loop dynamic simulations were performed, with the system parameters summarized in

Table 1. System Component Parameters.

Component	Model
Input Voltage $V_1$	5 V–24 V
Input Voltage $V_2$	5 V–24 V
Switching Frequency	100 kHz
Inductor $L_1,L_2,L_3$	$1500\mathsf{\mu }\mathrm{H},1000\mathsf{\mu }\mathrm{H},2000\mathsf{\mu }\mathrm{H}$
Capacitor $C_1,C_2,C_{O1},C_{O2}$	$88\mathsf{\mu }\mathrm{f},47\mathsf{\mu }\mathrm{f},220\mathsf{\mu }\mathrm{f},220\mathsf{\mu }\mathrm{f}$
R	5–200 $\Omega$
Inductor $L_4$	$1500\mathsf{\mu }\mathrm{H}$

. In addition, the simulation time step was selected to be less than $0.1$ times the switching period to ensure accurate representation of the overall dynamic behavior of the system.

5.1. Open-Loop Sweep and Closed-Loop Simulation of the Upper-Level Topology

The open-loop sweep of the upper-level topology is conducted to identify the key factors influencing the output voltage and to evaluate the voltage stresses on the switches and diodes. According to the previously designed control strategy, switches $S_{1a}$, $S_{1b}$, and $S_2$ operate with an identical duty cycle, while a phase shift between $S_2$ and $S_{1a}/S_{1b}$ is introduced through a C-block. To clearly observe the relationship between the control variable and the controlled variable, both input ports are set to the same voltage level ($d_1=d_2=D$, $V_1=V_2=V=12\mathrm{V}$). Figure 11 illustrates the converter voltage gain and output voltage as functions of the duty cycle. As shown in Figure 11, the open-loop sweep results of the upper-level topology, obtained under the conditions of equal input voltages and identical switch duty cycles, exhibit excellent agreement with the theoretical predictions. This close correspondence validates the theoretical analysis and confirms the suitability of the selected simulation parameters.

In practical renewable energy power systems, the voltage levels of the two input ports are not necessarily identical. To emulate this operating condition, the voltage of the input port 1 ($V_1$) was fixed at $12\mathrm{V}$, while the voltage of the input port 2 ($V_2$) varied from $5\mathrm{V}$ to $24\mathrm{V}$ in increments of $1\mathrm{V}$. Meanwhile, the switch duty cycle D was swept from $0.5$ to $0.85$ with a step size of $0.05$. The resulting scan data are presented in Figure 12. The simulation results demonstrate that the obtained topological characteristics are consistent with the theoretical analysis, thereby confirming the feasibility of applying the proposed converter in renewable energy systems.

To further investigate the voltage stresses on the switching devices and diodes, a simulation was conducted under the conditions $D=0.7$, $V_1=12\mathrm{V}$, and $V_2=10\mathrm{V}$. The resulting voltage waveforms of the key components in the upper-level topology are illustrated in Figure 13. As observed, the voltage stresses across switches $S_{1a}$, $S_{1b}$, and $S_2$ are $40.52\mathrm{V}$, $93.35\mathrm{V}$, and $39.62\mathrm{V}$, respectively, while the corresponding voltage stresses on diodes $D_1$, $D_2$, and $D_3$ are $40.62\mathrm{V}$, $133.87\mathrm{V}$, and $40.62\mathrm{V}$. Within an acceptable margin of error, these simulated results agree well with the theoretical predictions, thus verifying the accuracy of the proposed operating-mode analysis.

To validate the performance of the upper-level topology controller, a closed-loop simulation was carried out. The open-loop sweep results revealed a positive correlation between the output voltage ($V_{\mathrm{o}}$)/voltage gain (G) and the switch duty cycle (D). Based on these observations, a dual-loop control scheme was implemented. In this configuration, the sampled output voltage ($V_{\mathrm{o}}$) is compared with its reference value, and the resulting error is fed into the outer voltage loop. Similarly, the inductor current ($I_{L1}$) serves as the input to the inner current loop. This hierarchical control strategy ensures that the output voltage ($V_{\mathrm{o}}$) rapidly tracks its reference, thereby enhancing the dynamic response of the system.

Under the operating conditions of an input voltage of 12 V, a load resistance of $R=15\Omega$, and a reference voltage of 220 V, the closed-loop simulation results are presented in Figure 14. For comparison, the system response under a single voltage-loop control for the upper-level topology is also shown. The analysis indicates that the proposed dual-loop controller achieves approximately a 70% reduction in dynamic response time relative to the single-loop voltage control scheme. The improvement in dynamic response is attributable to the dual-loop control structure at the upper level.

As shown in Figure 14, the output current ($I_1$) of the upper-level topology remains constant once the controller stabilizes the output voltage. This steady output provides a necessary condition for the lower-level topology to achieve dynamic current sharing via closed-loop control of the inductor current ($I_{L4}$). Additionally, the input limit of the inner inductor current loop is set as the ratio of the output current to n (where n denotes the number of input ports). This configuration ensures proper power distribution among the upper-level input ports while preventing converter failure due to a short circuit in any single port.

5.2. Open-Loop Sweep and Closed-Loop Simulation of the Lower-Level Topology

Although the lower-level single-inductor multiple-input topology operates under closed-loop control of the inductor current ($I_{L4}$), an open-loop sweep of the duty cycles for the input and output unit switches was performed to determine the feasible operating range of $I_{L4}$. The results presented in Figure 15, indicate that the inductor current ($I_{L4}$) varies from 0.1 A to 65 A.

Based on the configuration of the lower-level single-inductor multiple-input topology and its open-loop characteristics, the controller was designed to regulate the inductor current ($I_{L4}$). In the closed-loop simulation, both input voltages were set to $V_1=V_2=12$ V, and the load resistance was $R=15\Omega$. The reference inductor current was set to 4 A. The results, shown in Figure 16, indicate that the ripple coefficient (r) of $I_{L4}$ is approximately 0.9%. This low ripple demonstrates effective controller performance, which contributes to enhanced system efficiency and output stability.

As previously discussed, for hierarchical dynamic current sharing, the reference value of $I_{L4}$ is set to N times the ratio of $I_1$ to the duty cycle ($d_4$) of switch $S_4$. Switch $S_4$ is employed to establish the current path. Once the inductor current closed-loop control is stabilized, $I_2$ can be regulated by adjusting $d_4$. To validate the effectiveness of this strategy and further assess its efficiency, a sweep test was conducted under the conditions of $V_1=V_2=12$ V and an $I_{L4}$ reference of 4 A. The resulting efficiency curve is presented in Figure 17. The results show that the power transfer efficiency of the lower-level topology remains above 90% and reaches its optimum when $d_4$ is within the range of 0.5 to 0.8. At lower $d_4$ values, power utilization is insufficient. As $d_4$ increases, the efficiency initially rises but subsequently decreases after reaching a peak, as switching losses become the dominant factor.

5.3. Closed-Loop Simulation of the Overall Converter Operation

Under different input voltage conditions ($V_1=12$ V, $V_2=10$ V) with the load resistance fixed at $R=15\Omega$, closed-loop simulations of the overall converter were conducted. The output voltage reference values were set to 180 V, 220 V, and 300 V, corresponding to N values of 1, 2, and 3, respectively. The simulation results are shown in Figure 18.

The transformer rapidly reached the preset voltage within 50 ms, achieving a closed-loop maximum gain of up to 30, which demonstrates the effective performance of the controller. Simultaneously, the current-sharing controller enabled the lower-level output current ($I_2$) to promptly track the upper-level output current ($I_1$). This precise tracking allows the upper-level topology, operating as a voltage source, to achieve a higher voltage gain, thereby enabling the overall converter to deliver greater power. Furthermore, the current-sharing error ${\delta }_k$ was calculated to be less than 2%, confirming the satisfactory performance of the current-sharing controller.

A dynamic response simulation was conducted under the following conditions: both input port voltages were maintained at 12 V, while the load resistance (R) was subjected to a step change from 15 $\Omega$ to 10 $\Omega$. The voltage reference was set to 220 V, corresponding to $N=2$, with all other conditions kept unchanged. The simulation results are presented in Figure 19.

As demonstrated in Figure 19 and Figure 20, the designed control system endows the proposed converter with excellent dynamic performance. The dynamic response time remains consistently within 100 ms, and the current-sharing controller exhibits high precision. These results collectively validate the correctness of the theoretical analysis and the parameter selection for the controller.

6. Analysis of Experimental Results

To further verify the theoretical analysis and the effectiveness of the designed control system, an experimental platform was constructed in the laboratory, as illustrated in Figure 21. The two input ports of the platform were connected to DC sources. The parameters of the key components in the converter circuit were kept consistent with those used in the simulations, while the detailed specifications of other components are provided in

Table 2. Circuit Parameters of the Experimental Prototype.

Components	Model/Part Number
Current Sensor	CHCS-PS3.3 Closed-loop Hall-effect Sensor (Microchip Technology, Chandler, AZ, USA)
Voltage Sensor	HVS-AS3.3 High-Precision Voltage Sensor (Microchip Technology, Chandler, AZ, USA)
Digital Controller	dsPIC33FJ64GS606 (Microchip Technology, Chandler, AZ, USA)
Power Switch	80 V/200 A SiC N-Channel MOSFET (Microchip Technology, Chandler, AZ, USA)
Diode	STTH30R04 (Microchip Technology, Chandler, AZ, USA)
Load Resistor (R)	15 $\Omega$

.

6.1. Analysis of Upper-Layer Topology Experimental Results

Based on the preceding theoretical analysis and simulation results, the DC power flow at the energy output port of the upper-layer topology is regulated via PWM. To validate this, an experiment was conducted with a fixed load of 15 $\Omega$ and input port voltages set at 12 V. The duty cycle (D) of the control switch was swept from 0.5 to 0.85 in increments of 0.05. As depicted in Figure 22, the measured practical gain and output voltage of the topology under this open-loop scan are in close agreement with the simulation results, thereby confirming the theoretical premises.

As shown in Figure 22, the measured output voltage and gain exhibit close agreement with the simulation results across the investigated duty cycle range. This consistency validates the theoretical predictions for the proposed topology and ensures that the overall boost ratio of the converter is maintained. To further validate the performance of the proposed topology and the designed dual-loop controller under unequal input voltage conditions, an experiment was conducted with a fixed load of 15 $\Omega$. The input voltages were configured as $V_1=12$ V and $V_2=10$ V, with a reference voltage set to 220 V. The resulting waveforms from the closed-loop control experiment are presented in Figure 23, while the corresponding PWM drive signals and switch node voltage waveforms are shown in Figure 24.

Experimental results demonstrate that the designed dual-loop controller exhibits excellent dynamic performance, enabling the output voltage ($V_0$) to rapidly and accurately track and stabilize at the reference value, thereby validating the proposed control strategy. Furthermore, the current waveforms in Figure 23 clearly indicate that the inner current loop, which regulates the inductor current ($I_{L1}$), not only accelerates the response of the outer voltage loop but also stabilizes the other inductor currents, effectively suppressing current spikes.

6.2. Analysis of Lower-Layer Topology Experimental Results

Theoretical analysis and simulation results indicate that the duty cycle of the input-unit switch in the lower-layer topology can be effectively regulated via an inductor current closed-loop control strategy. To validate the feasibility and practical performance of this control scheme, an experiment was conducted under the following conditions: a fixed load (R) of 15 $\Omega$, input voltages $V_1=12$ V and $V_2=10$ V, an inductor current ($I_{L4}$) reference of 5 A, and a duty cycle ($d_4$) of 0.75 for the output-unit switch ($S_4$). The corresponding experimental results are presented in Figure 25.

The experimental results demonstrate that the implementation of closed-loop control substantially enhances the current steady-state accuracy and dynamic response of the lower-layer topology, thereby ensuring stable and efficient operation of the input unit across various working conditions. These findings robustly validate the effectiveness of the theoretical analysis and simulation predictions.

6.3. Analysis of Overall Converter Experimental Results

To comprehensively evaluate the integrated performance of the designed dual-loop upper-layer controller and the lower-layer current-sharing controller, a system-level output current-sharing experiment was devised for the converter. The experimental protocol comprises three key procedures: (1) Steady-state output voltage and current-sharing characterization: The converter was operated at a specified output voltage to assess the current-sharing accuracy under steady-state conditions. (2) Dynamic response to input voltage disturbance: A step change in input voltage was introduced while maintaining the output voltage, to observe the system’s dynamic response and the variation in current-sharing precision. (3) Robustness test under load transients: With fixed input voltage and output voltage reference, a step load disturbance was applied to examine the control system’s robustness and the stability of the current sharing.

6.3.1. Steady-State Characterization of Output Voltage and Current Sharing

During the steady-state output voltage and current-sharing characterization, the dual-input power ports were set to different voltage levels ($V_1=12$ V, $V_2=10$ V) with a load resistance of 15 $\Omega$. The output voltage was set to 180 V, 220 V, and 300 V, corresponding to current-sharing multiples (N) of 1, 2, and 3, respectively. The closed-loop experimental results are presented in Figure 26. As observed, the output voltage rapidly converges to the setpoint with minimal overshoot and exhibits high steady-state accuracy. Furthermore, the lower-layer output current ($I_2$) accurately maintains a ratio of N times the upper-layer output current ($I_1$), demonstrating high current-sharing precision and validating the effective power distribution across the converter stages.

6.3.2. Dynamic Response to Input Voltage Disturbance

In the dynamic response test under input voltage disturbance, the load resistance (R) was fixed at 15 $\Omega$, with the output voltage reference set to 220 V and the current-sharing multiple (N) set to 2. One of the dual-input energy ports was connected to a 12 V DC source, while the other was supplied by a programmable DC power supply. The voltage of the programmable power supply was stepped from 10 V to 18 V to introduce the disturbance. The corresponding dynamic response of the converter is illustrated in Figure 27. As shown, when the input port voltage undergoes a step change, both the output voltage closed-loop controller and the current-sharing controller exhibit response times of less than 50 ms.

6.3.3. Robustness Test Under Load Transients

In the load transient robustness test, the converter was configured with $V_1=12$ V, $V_2=10$ V, an output voltage setpoint of 220 V, and a current-sharing multiple (N) of 2. The load resistance (R) was subjected to a step change from 15 $\Omega$ to 10 $\Omega$ using a programmable electronic load. The dynamic response of the converter under this transient is illustrated in Figure 28. As observed, both the output voltage controller and the current-sharing controller achieved response times of less than 100 ms following the load step.

The experimental results on the converter’s dynamic response demonstrate that the designed control system can rapidly regulate the output voltage and achieve precise current-sharing between layers, even during abrupt changes in input voltage and load resistance. These findings confirm the system’s excellent robustness and dynamic performance.

6.4. Investigation into Converter Transfer Efficiency

Following the dynamic response tests, the relationships among load power, output voltage, and converter efficiency ($\eta$) were further investigated. The closed-loop efficiency was characterized by scanning the output voltage setpoint from 100 V to 230 V in 10 V increments, under the condition of fixed dual-input port voltages of 12 V and a load resistance (R) of 15 $\Omega$. As illustrated in Figure 29, the system efficiency of the converter reaches its maximum at an output voltage of 220 V. Further increases in the voltage setpoint beyond this optimal point result in a degradation of system efficiency.

Subsequently, with the output voltage setpoint fixed at 220 V and both input port voltages maintained at 12 V, an efficiency scan was performed by varying the load resistance (R) from 10 $\Omega$ to 150 $\Omega$ in 10 $\Omega$ increments. The results, presented in Figure 30, demonstrate that the system-level efficiency of the converter remains above 90% across the entire load range, peaking at 95.7% at 20 $\Omega$. Furthermore, the power transfer efficiency for each individual input port also exceeded 90%. These findings collectively affirm the converter’s strong potential for application in new-type power systems.

7. Conclusions

This paper proposes a novel non-isolated, dual-layer, multi-port, parallel-connected DC–DC power conversion system designed for high voltage gain. The architecture employs two distinct power stages: an upper layer utilizing a multi-port, high-gain DC topology to achieve a high voltage boost ratio, and a lower layer based on a multi-port current-source DC topology to facilitate output current sharing. This configuration not only satisfies the high-gain requirements for integrating renewable energy sources but also enhances the system’s power capacity under such conditions. The system supports operation in both Input-Parallel Output-Parallel (IPOP) mode and a mode with independent inputs and parallel outputs, providing flexible multi-port, high-gain power conversion. A time-domain analysis based on the switching cycle was performed to detail the operational states of each layer, and a small-signal model was developed to enable precise control design. Building on this model, an adaptive current-sharing control strategy was devised. This strategy regulates the upper layer’s output voltage and dynamically allocates the output current between the two layers according to load demand, thereby effectively increasing the system’s power rating. Key performance metrics—including voltage gain, current sharing, and semiconductor stresses—were validated through both open-loop characterization and closed-loop verification using a PSIM simulation model. Furthermore, a 2000 W prototype, controlled by a dsPIC33FJ64GS606 digital controller, was constructed. Open-loop tests and dynamic response evaluations demonstrated a peak efficiency of 95.7%, successfully confirming the validity of the system design and the efficacy of the proposed control strategy. For the future, the proposed dual-layer architecture exhibits strong scalability for high-power applications. By employing a multi-port structure in the lower layer, additional input ports can be integrated in parallel to increase the overall power capacity.