Short-Circuit Characteristic Analysis of SiC Trench MOSFETs with Dual Integrated Schottky Barrier Diodes

Abstract

A 4H-silicon carbide (SiC) trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) with dual integrated Schottky barrier diodes (SBDs) was characterized using numerical simulations. The advantage of three-dimensional stacked integration is that it allows the proposed structure to obtain an electric field of below 0.6 MV/cm in the gate oxide and SBD contacts and achieve ~10% lower forward voltage of SBDs than the planar gate SBD-integrated MOSFET (PSI-MOS) and the trench gate structure with three p-type-protecting layers (TPL-MOS). The dual-SBD-integrated MOSFET (DSI-MOS) also highlights the better influences of the more than 70% reduction in the miller charge, as well as the over 50% reduction in switching loss compared to the others. Furthermore, the short-circuit (SC) robustness of the three devices was identified. The DSI-MOS attains the critical energy and the aluminum melting point in a longer SC time interval than the TPL-MOS. The p-shield layers in the DSI-MOS are demonstrated to yield the huge benefit of improving the reliability of the contacts when SC reliability is considered.

1. Introduction

Due to superior material properties and improved device performance, power MOSFETs in 4H-SiC (SiC) can provide significant loss reduction at high temperatures and high frequencies and are becoming mainstream in a variety of high-power applications [1,2,3,4,5,6,7]. In particular, the use of SiC MOSFETs in electric vehicles and photovoltaic applications is gaining market acceptance and showing superior benefits compared to Si devices. However, large-scale demonstration of SiC MOSFETs is delayed by issues such as gate oxide defects, high chip cost, and short-circuit (SC) reliability concerns [8,9,10]. Despite all these facts, the development of the SiC trench gate MOSFET (UMOSFET) is an important technology trend, enabling lower specific on-resistance (R_on-sp) and smaller pitch size compared to the planar gate MOSFET (DMOSFET). It is believed that trench UMOSFETs can significantly improve the performance of power modules as well as the tradeoff between on-resistance and chip cost. It is also known that the technology of incorporating a Schottky barrier diode (SBD) into a MOSFET is another promising design approach for reducing the total cost of wafer fabrication [11,12,13,14,15] because it can realize the elimination of the external anti-parallel SBD, reducing the chip area and the switching losses induced by the results of the minority injection and relatively larger turn-on voltage (~2.6 V) of the intrinsic pin diodes in a SiC MOSFET. Furthermore, the advantage of an SBD-embedded MOSFET also lies in its improvement of reliability due to the inhibited conversion of basal plane dislocations into stacking faults caused by the conduction of intrinsic pin diodes [16]. Therefore, SBD-integrated MOSFET topologies are key device prototypes for achieving reduced total chip size, compact power modules, enhanced reliability, and low package cost in the future.

Several conceptual structures with integrated SBDs or MOS-channel diodes have been proposed and demonstrated to have improved static and dynamic characteristics [17,18,19,20,21]. They have also been fabricated in a production-grade wafer line, with the SiC DMOSFETs showing high unipolar current density in the third-quadrant operation [11]. Such technology has also been repurposed in SiC UMOSFETs with a small cell pith [15]. However, an SBD-embedded SiC UMOSFET is not readily achievable because it poses challenges, such as improving the reliability of trench oxide and SBD contacts simultaneously, and allocating the conduction layer in a small-dimension device without area penalty [22,23]. Meanwhile, verifying the short-circuit (SC) capability of an SiC UMOSFET is of great significance for their widespread adoption as replacements for available silicon insulated gate bipolar transistors (IGBTs) in key automotive applications. Under SC conduction, the SiC UMOSFET demonstrates a reduction in the capability to withstand SC. Different failure mechanisms have been identified by other groups. However, so far, there have been few investigations into the SC robustness of SiC SBD-integrated MOSFETs, especially considering the simultaneous occurrence of high temperature and high electric field in an SiC UMOSFET.

In this paper, a dual-SBD-integrated UMOSFET (DSI-MOS) is proposed using numerical simulations. The planar gate SBD-integrated MOSFET (PSI-MOS) [11] and the trench gate structure with three p-type-protecting layers (TPL-MOS) [19] were chosen for a performance comparison in this article. Furthermore, a comparative study of the SC capability between them was conducted. The possible failure mechanisms were also provided and demonstrated together.

2. Models and Methods

The software used for the simulation was Sentaurus TCAD 2013 [24]. The simulator uses physical models to simulate electrical and thermal effects in a wide range of power devices fabricated utilizing wide-bandgap material like SiC and GaN. The boundary conditions were specified in the electrode defined for each device. The electrodes had a voltage or a current boundary condition, along with contact resistance or Schottky barrier height. For dynamic simulation, the time step was chosen and bounded dynamically for use in mixed-mode simulations. For thermal simulation, thermally resistive boundary conditions were implemented to accurately characterize the thermal interface between the semiconductor and the adjacent material.

Moreover, some essential model parameters were covered in the simulator, such as the impact ionization, carrier recombination, incomplete ionization, and anisotropic material properties of SiC [25,26,27,28,29,30,31]. Also, tunneling models were involved so as to characterize the diode performance [1].

$$G\left(r\right)=A^{*}·F\left(r\right)·P_{\mathrm{t}}\left(r\right)·{\displaystyle \frac{T}{k_{\mathrm{B}}}}·ln\left[{\displaystyle \frac{1+exp\left(\frac{\left(E\left(r\right)-E_{\mathrm{s}}\right)T}{k_{\mathrm{B}}}\right)}{1+exp\left(\frac{\left(E\left(r\right)-E_{\mathrm{m}}\right)T}{k_{\mathrm{B}}}\right)}}\right]$$

(1)

where $A^{*}$ is the effective Richardson constant, F(r) is the electric field, P_t(r) is the Wentzel–Kramers–Brillouin (WKB) approximation for the tunneling probability, E(r) is carrier energy, E_s is the carrier quasi-Fermi energy of SiC, and E_m is the carrier Fermi energy of the metal. When accounting for Schottky barrier lowering, the band edges are modified by a position-dependent lowering potential, described by [32] as

$$∆{\mathsf{\Phi }}_{\mathrm{B}}\left(r\right)=min\left({\displaystyle \frac{Aq}{16\pi \epsilon r}},BL\_max\right)$$

(2)

where $\epsilon$ is the material dielectric constant, $r$ is the distance from the interface or contact, $A$ is a dimensionless fitting parameter, and $BL\_max$ is the maximum value for the lowering potential.

For the electrical simulations of the SiC MOSFET, the following models were used:

Shockley–Read–Hall (SRH) model, Auger recombination model, and Okuto–Crowell model, specifically for the simulation of breakdown voltage. Furthermore, the inversion and accumulation layer mobility model (IALMob), the carrier high-field saturation model, bandgap-narrowing effects, and anisotropic models for mobility and avalanche processes were also incorporated into the simulation [31]. Also, the Poisson equation, along with the carrier continuity equations and the temperature equation, were systematically solved. This process yielded the distributions of the electric field, the electrostatic potential, the Joule heat, the carrier temperature, and the lattice temperature, among other parameters.

Herein, we emphasize the significance of models that characterize channel mobility in SiC MOS-based devices. These models are essential for achieving accurate simulation results. Based on Matheissen’s rule, the total low-field mobility μ_LF can be expressed as follows [33]:

$${\mu }_{\mathrm{L}\mathrm{F}}={\displaystyle \frac{1}{{\mu }_{\mathrm{B}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{S}\mathrm{P}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{C}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{S}\mathrm{R}}}}$$

(3)

where ${\mu }_{\mathrm{B}}$ is bulk mobility, ${\mu }_{\mathrm{S}\mathrm{P}}$ is surface phonon mobility, ${\mu }_{\mathrm{C}}$ is Coulomb mobility, and ${\mu }_{\mathrm{S}\mathrm{R}}$ is surface roughness mobility. Coulomb scattering has both inversion and accumulation layer contributions, which are critical for the performance of SiC MOSFET devices. Additionally, this phenomenon exhibits a dependency on the local layer thickness, highlighting its significance in device characterization and optimization [10].

$${\displaystyle \frac{1}{{\mu }_{\mathrm{C}}}}=erf\left({\displaystyle \frac{t+t_1}{t_{\mathrm{C}\mathrm{o}\mathrm{u}\mathrm{l}\mathrm{o}\mathrm{m}\mathrm{b}}}}\right)\left({\displaystyle \frac{1}{{\mu }_{\mathrm{C},\mathrm{i}\mathrm{n}\mathrm{v}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{C},\mathrm{a}\mathrm{c}\mathrm{c}}}}\right)$$

(4)

where

$${\mu }_{\mathrm{C},2\mathrm{D},\mathrm{i}\mathrm{n}\mathrm{v}}={\left[{\left({\displaystyle \frac{D_{1,\mathrm{i}\mathrm{n}\mathrm{v}}{\left(T/300K\right)}^{{\alpha }_{1,\mathrm{i}\mathrm{n}\mathrm{v}}}{\left(c/N_{\mathrm{s}\mathrm{c},\mathrm{r}\mathrm{e}\mathrm{f}}\right)}^{v_{0,\mathrm{i}\mathrm{n}\mathrm{v}}}}{{\left(N_{\mathrm{i}\mathrm{n}\mathrm{v}}/N_{\mathrm{d}\mathrm{o}\mathrm{p},\mathrm{r}\mathrm{e}\mathrm{f}}\right)}^{v_{1,\mathrm{i}\mathrm{n}\mathrm{v}}}}}\right)}^2+{\left({\displaystyle \frac{D_{2,\mathrm{i}\mathrm{n}\mathrm{v}}{\left(T/300K\right)}^{{\alpha }_{2,\mathrm{i}\mathrm{n}\mathrm{v}}}}{{\left(N_{\mathrm{i}\mathrm{n}\mathrm{v}}/N_{\mathrm{d}\mathrm{o}\mathrm{p},\mathrm{r}\mathrm{e}\mathrm{f}}\right)}^{v_{2,\mathrm{i}\mathrm{n}\mathrm{v}}}}}\right)}^2\right]}^{1/2}$$

(5)

$${\mu }_{\mathrm{C},2\mathrm{D},\mathrm{a}\mathrm{c}\mathrm{c}}={\left[{\left({\displaystyle \frac{D_{1,\mathrm{a}\mathrm{c}\mathrm{c}}{\left(T/300K\right)}^{{\alpha }_{1,\mathrm{a}\mathrm{c}\mathrm{c}}}{\left(c/N_{\mathrm{s}\mathrm{c},\mathrm{r}\mathrm{e}\mathrm{f}}\right)}^{v_{0,\mathrm{a}\mathrm{c}\mathrm{c}}}}{{\left(N_{\mathrm{a}\mathrm{c}\mathrm{c}}/N_{\mathrm{d}\mathrm{o}\mathrm{p},\mathrm{r}\mathrm{e}\mathrm{f}}\right)}^{v_{1,\mathrm{a}\mathrm{c}\mathrm{c}}}}}\right)}^2+{\left({\displaystyle \frac{D_{2,\mathrm{a}\mathrm{c}\mathrm{c}}{\left(T/300K\right)}^{{\alpha }_{2,\mathrm{a}\mathrm{c}\mathrm{c}}}}{{\left(N_{\mathrm{a}\mathrm{c}\mathrm{c}}/N_{\mathrm{d}\mathrm{o}\mathrm{p},\mathrm{r}\mathrm{e}\mathrm{f}}\right)}^{v_{2,\mathrm{a}\mathrm{c}\mathrm{c}}}}}\right)}^2\right]}^{1/2}G\left(P\right)$$

(6)

The function of $G\left(P\right)$ minority impurity scattering.

In addition, with the thermodynamic model, the lattice temperature is calculated from [34]:

$$\begin{array}{cc}\hfill {\displaystyle \frac{\partial }{\partial t}}\left(c_{\mathrm{L}}T\right)-\nabla ·\left(\kappa \nabla T\right)=& -\mathsf{\nabla }·\left[\left(P_{\mathrm{n}}T+{\mathsf{\Phi }}_{\mathrm{n}}\right){\overrightarrow{J}}_{\mathrm{n}}+\left(P_{\mathrm{p}}T+{\mathsf{\Phi }}_{\mathrm{p}}\right){\overrightarrow{J}}_{\mathrm{p}}\right]-{\displaystyle \frac{1}{q}}\left(E_{\mathrm{C}}+{\displaystyle \frac{3}{2}}kT\right)(\nabla ·{\overrightarrow{J}}_{\mathrm{n}}-q{R}_{\mathrm{n}\mathrm{e}\mathrm{t},\mathrm{n}})-\hfill \\ & {\displaystyle \frac{1}{q}}\left(E_{\mathrm{V}}+{\displaystyle \frac{3}{2}}kT\right)\left(-\mathsf{\nabla }·{\overrightarrow{J}}_{\mathrm{p}}-q{R}_{\mathrm{n}\mathrm{e}\mathrm{t},\mathrm{p}}\right)+\hslash \omega G^{\mathrm{o}\mathrm{p}\mathrm{t}}\hfill \end{array}$$

(7)

where $\kappa$ is the thermal conductivity, $c_{\mathrm{L}}$ is the lattice heat capacity, $E_{\mathrm{C}}$ and $E_{\mathrm{V}}$ are the conduction and valence band energies, respectively, $G^{\mathrm{o}\mathrm{p}\mathrm{t}}$ is the optical generation rate from photons with frequency, $R_{\mathrm{n}\mathrm{e}\mathrm{t},\mathrm{n}}$ and $R_{\mathrm{n}\mathrm{e}\mathrm{t},\mathrm{p}}$ are the electron and hole net recombination rates, respectively, and ${\overrightarrow{J}}_{\mathrm{n}}$ and ${\overrightarrow{J}}_{\mathrm{p}}$ are the electron and hole current densities, respectively.

The simulation model was calibrated to the measured characteristics of SiC MOSFET fabricated by our group. The simulated on-state and blocking characteristics are in good agreement with the measured results (Figure 1a). Furthermore, a comparison was made with the results obtained using other software (Silvaco 2021 simulator [35]), demonstrating consistent agreement between the experimental and simulated characteristics across the evaluation curve. Furthermore, as shown in Figure 2b,c, the measured forward current of SiC SBD with respect to both temperature and applied voltage closely aligns with the simulation results attained from the electrothermal modeling. This correlation validates the applicability of the model for evaluating the temperature characteristics of SiC devices.

3. Device Structures and Mechanism

Figure 3 shows the schematic cross-sections of the three structures. Both the PSI-MOS and TPL-MOS have split p-type doped well in order to open a window for the SBD contacts. The width of the SBD window is L_SBD. The DSI-MOS features dual SBD contacts. One is located in the mesa regions and the other is formed on the trench bottom regions. Herein, they are set to be the same Schottky barrier height (SBH) value. The width of the junction field effect transistor (JFET) regions is L_JFET for all the structures. It is noted that the DSI-MOS features a reverse channel, resulting in an upside-down carrier conduction path in the first-quadrant mode. Due to the unique channel structure, both the MOSFET and SBD can share the forward conduction regions in the DSI-MOS.

One of the existing challenges in the proposed MOSFET design is establishing an opening for the SBD contacts at both the mesa and the trench bottom regions. Specifically, since a thick inter-metal dielectric layer (IDL) is deposited to ensure isolation between the gate and source electrodes, it is necessary to carefully allocate the SBD opening window at a selective position orthogonal to the trench. Another challenge lies in defining the vertical distance between the p-base regions and the mesa surface of the DSI-MOS. This is because the coupling effect between the p-shield regions and the Schottky contacts can affect the on-state of the MOSFET. The design of these critical parameters was created with reference to the findings in the previous work [36].

The possible fabrication process and a workable solution for the UMOSFET have also been presented. The DSI-MOS can be fabricated by utilizing almost the same process as that proposed in the UMOSFET, apart from the approach of contact opening to form the Schottky contacts. Figure 3a,b show the revised process flow for the formation of the Schottky contacts in the SBD-integrated DSI-MOS. The contact opening is performed on the mesa surface and at the trench bottom as shown in Figure 3a. Then, the segmented contact holes are placed at selective positions along the gate fingers so as to separately allocate the source and Schottky contacts area in the trench bottom. Afterward, the source and drain electrodes are defined by the ohmic alloy as shown in Figure 3b. It is known that a single-metal, single-thermal-treatment process was developed to simultaneously form ohmic contacts to the n+ and p+ implanted regions and Schottky contacts to the n-4H-SiC [14]. These results will lay a meaningful foundation for the consideration of electrode formation in the DSI-MOS.

In this work, all the devices have a p-base layer with a doping concentration of 1 × 10¹⁷ cm⁻³, a gate oxide thickness of 50 nm, a channel length of 0.5 μm, an n-drift region with a thickness of 10 μm (from the source contacts to the n buffer region), and a doping concentration of 7 × 10¹⁵ cm⁻³. The vertical distance between the p-base regions and the mesa surface of the DSI-MOS is d = 1.1 μm. The maximum channel mobility is 50 cm²/V·s and the mobility degradation models are considered. Meanwhile, positively trapped charges of 1 × 10¹² cm⁻² are added at the SiC/SiO₂ interface. These values come from literature reports [37,38]. Our modeling shows that these channel parameters can be used for the calibration of mobility and drive-current, thereby yielding appropriate on-state performance. In the on-state of MOSFET, the specific on-resistance (R_on-sp) is obtained at the gate–source voltage (V_GS) of 15 V. In the on-state of SBD, the forward voltage drop at the current density (J) of 500 A/cm² is V_F. The triggering-on voltage of body pin diodes is determined by the threshold forward voltage (V_Fh), at which the hole current density (J_h) reaches 10 A/cm². In the off-state, the maximum electric field in the gate oxide (E_ox-max) and that in the SBD contact surface (E_SBD-max) are all obtained at the drain-source voltage (V_DS) of 1200 V.

4. Results and Comparisons

The tradeoffs between R_on,sp and E_ox-max are shown in Figure 4a. L_JFET is 3.0, 2.5, 2.0, and 1.5 μm for the PSI-MOS, and it is 2.6, 2.4, 2.2, and 2.0 μm for the TPL-MOS and DSI-MOS. The JFET doping concentration is D_JFET with the values of 2 × 10¹⁶, 3 × 10¹⁶, and 4 × 10¹⁶ cm⁻³, respectively. In Figure 4b, L_SBD is 1.8, 1.6, 1.4, 1.2, and 1.0 μm for the PSI-MOS, and it is 1.25, 1.0, 0.75, and 0.5 μm for the TPL-MOS (L_JFET = 2.0 μm). The values of cell pitch are 10, 6, and 5 μm for the PSI-MOS, TPL-MOS, and PSI-MOS, respectively. Due to the smaller cell pith, the TPL-MOS exhibits lower R_on,sp than the DSI-MOS. Nonetheless, the behavior of the depletion extension induced by the Schottky barrier is beneficial for the significant reduction of E_ox-max in DSI-MOS. Therefore, with the JFET doping concentration (D_JFET) ranging from 2 × 10¹⁶ to 4 × 10¹⁶ cm⁻³, there is always a superior compromise between R_on,sp and low E_ox-max in it. Figure 4b compares the tradeoffs between V_F and E_SBD-max for the SBD. Because of the structural feature of deep p-buried layers, E_SBD-max can be reduced below 0.6 MV/cm in the proposed device and TPL-MOS. The SBD will consume 25% and 18% of the overall area in one unit cell in TPL-MOS and PSI-MOS, respectively. However, it occupies above 55% of that in the DSI-MOS, leading to ~10% lower V_F than others.

Figure 5 shows the effects of the cell pitch on the devices’ static characteristics. The triggering-on voltage of body pin diodes is determined by a forward voltage drop across the spreading resistance (R_S) (see Figure 3c). If it is larger than the built-in voltage of the pn junction, the body pn diode will be turned on. The applied source-drain voltage consists of the voltage drop at the Schottky contact, the voltage drop across the R_S, and the voltage drop across the drift layer and substrate. Thus, high current density can induce high source-drain voltage if the voltage drop across the R_S is still kept at a low value. This means that large V_Fh can be obtained by reducing the spreading resistance.

Then, it is known that a small cell pitch in the SBD-integrated MOSFET will result in a reduction in the spreading resistance underneath the SBD contacts [9,15]. This is the reason why the TPL-MOS shows a higher V_Fh than the PSI-MOS. With regard to the proposed DSI-MOS, it features larger L_SBD than the others. The result of two parallel-connected SBD diodes also contributes to further reduction in the spreading resistance, leading to a significant increase of V_Fh in it. Form Figure 5a, it is noticeable that the V_Fh of the DSI-MOS decreases with decreasing cell pitch. This is because the cell pitch is reduced by minimizing the width of the opening window for the SBD in the trench bottom. Paradoxically, the DSI-MOS requires larger trench width so as to ensure isolation between the gate and the source electrodes in the trench. Then, in the PSI-MOS and TPL-MOS, the SBD width is kept constant. However, cell pitch cannot be continuously reduced because additional areas are required to target enough space for the formations of the p+ base, n+ source, and source metal regions in a common plane. In consideration of these factors, the roughly optimized values of the cell pitch are 8, 5, and 5.6 μm for the PSI-MOS, TPL-MOS, and DSI-MOS, respectively.

Furthermore, from Figure 5b, it can be seen that V_F in the PSI-MOS and TPL-MOS shows a reduced value with decreasing cell pitch. However, it features a slightly increasing value when the cell pitch is decreased in DSI-MOS. This is attributed to the area ratio between the Schottky contact regions and the equivalent p implantation regions being increased with decreasing cell pitch in the PSI-MOS and TPL-MOS, whilst it is moderately decreased with decreasing cell pitch in the DSI-MOS. Despite this fact, the DSI-MOS has the lowest V_F owing to the integrated dual SBD in a three-dimensional stacked trench structure. In addition, the R_on,sp of all the devices is reduced with decreasing cell pitch. The effect of scaling down technology yields more obvious benefits in the SiC UMOSFET than in the DMOSFET. Meanwhile, it is noticed that a small cell pitch device reveals only a little difference in R_on,sp between the DSI-MOS and TPL-MOS. Consequently, the DSI-MOS boasts the lowest value of R_on,sp × E_ox-max = 2.6 mΩ·MV·cm as compared to those of 3.3 and 8.3 mΩ·MV·cm for the TPL-MOS and PSI-MOS, respectively.

The dynamic performances of the devices are characterized by gate charges and double pulse-switching behaviors. As indicated in Figure 6a, the total gate charge (Q_G) of the TPL-MOS is slightly higher than that of the PSI-MOS. This is attributed to the smaller cell pitch and larger overlap between the gate electrode and the p-shield regions underneath the trench bottom. In particular, a miller charge (Q_GD) of 46 nC/cm² is obtained in the DSI-MOS. It is extremely lower than those obtained in TPL-MOS and PSI-MOS which show the values of 169 nC/cm² and 205 nC/cm², respectively. This is because the DSI-MOS has the smallest overlap between the gate electrode and the n-drift layer among the three. Therefore, the superior switching characteristics of this device are also justified by the loss simulation via a double pulse test with a DC voltage of 600 V and V_GS = 15/0 V. From Figure 6b, the calculated total switching loss is 9.1 mJ/cm² for the DSI-MOS, which is lower by over 50% in comparison to the values of 22.2 mJ/cm² and 23.8 mJ/cm² for the TPL-MOS and PSI-MOS, respectively.

Comparisons of SC characteristics were conducted by using electrothermal simulations. The previously reported works have demonstrated that the junction temperature during SC may reach 1000 K in an SiC MOSFET [39,40]. It is revealed that the formation of a crack in SiO₂ dielectric occurs when the temperature of aluminum metal reaches its melting point [41], but the SiC MOSFET does not suffer from a permanent failure at this mode. Additionally, SiC planar and trench MOSFETs encounter a high temperature of above 1700 K, leading to a different failure mode as compared with that in Si IGBTs. The maximum lattice temperatures within the range of 1500–2200 K for the SiC MOSFET were revealed and verified by numerical methods in previous works [9,10,42,43]. The electrothermal simulations were calibrated by using TCAD Synopsys Suite. They concluded that catastrophic failures show a strong dependence on the lattice temperature.

In the simulations, thermodes with a thermal resistive boundary condition can be connected to a circuit. The main component of the thermal condition is the thermal resistance from the chip bottom to the case [44,45] because the diffusion direction of the heat is mainly from the chip surface to the bottom of the case owing to the presence of a heat sink. This will be influenced by the properties of electrodes and packaging. Herein, the drain electrodes have a thermal resistive boundary condition with 0.3 K/W thermal resistance, which is a typical value from a two-sided cooled Si thyristor [44]. It is noted that this value is also close to that of the SiC MOSFET manufactured by Wolfspeed, which has an approximate value of 0.32 K/W (C3M0021120K) [46]. During the SC transients, high power passes through the device, leading to extensive self-heating and temperature-rising phenomena in the SiC. Then, the thermoelectric powers in the SiC are computed automatically by solving the temperature equation. In addition, the temperature-dependent models for mobility and carrier density, such as the heat transport models and lattice heat capacity, are utilized to improve the accuracy of thermal simulation [47,48].

In SC characteristic simulations, the DC bus connected to the device under test (DUT) was set to be 400 V or 800 V. The SiC MOSFET was turned on and off by using a pulse gate voltage with the values of 15 and 0 V. Then, the drain current achieved its saturation current at the pulse time. Different SC waveforms were obtained by changing the SC time period. Accordingly, the energy dissipated in the chip resulted in the increase in the lattice temperature.

Figure 7 plots the lattice temperature distribution in SBD-integrated MOSFETs with varied SBH and increased heating times after turning off the devices. It is used to characterize the lattice temperature fluctuation at the Schottky contacts after the melting of aluminum. The maximum temperature is limited to the value of around 1000 K in order to make the results reasonable. As indicated by the dashed box, the maximum lattice temperature (T_max) point emerges at the Schottky contacts and gate oxide in the PSI-MOS and TPL-MOS, respectively, when the SBH is 1.3 eV. However, it is manifested in the middle regions of the spreading layer below the JFET regions of the DSI-MOS. Meanwhile, if the SBH is increased, T_max is decreased in all the devices, suggesting that the effect of SBD leakage current may be suppressed.

Meanwhile, the SBH in the SiC SBD is in the range from 1.0 eV to 1.6 eV, which is depended on the specific type of Schottky metal employed [49,50,51]. However, the value of the SBH significantly affects the leakage current at high temperature. Then, in SBD-integrated MOSFETs with varied SBH, the lattice temperature increases as a result of leakage and extended heating periods following the short-circuit events. Herein, the maximum temperature in Figure 7 is limited to the value of around 1000 K in order to make the results reasonable. It has been reported in reference [52] that a lattice temperature was attained during the short-circuit evaluation of the SWITCH-MOS by establishing a barrier height of 1.51 eV. The simulated lattice temperatures were observed to range from 1000 K to 1200 K, as indicated in references [42,52,53,54]. These findings have been corroborated by experimental results, confirming that our temperature values are in good agreement with previously reported data. It is reasonable in a first step to predict the SC capability in the SiC SBD-integrated MOSFET and provide insights into the failure mode in it.

Figure 8 compares the SC waveforms and lattice temperature of the devices at SBH = 1.5 eV. The DSI-MOS shows higher current density in the saturation region as compared to the PSI-MOS due to the lower specific on-resistance. Thus, the DSI-MOS would have a larger heat dissipation per unit area during SC transient, causing a higher rise in lattice temperature. Likewise, the TPL-MOS has the lowest value of R_on,sp as compared with the others, owing to its smallest cell pith and highest channel density among the three. Therefore, the TPL-MOS will boast a higher saturation current density than the DSI-MOS as indicated in Figure 8a. It is evident that the TPL-MOS will suffer from amounts of heat during the identical SC time period, making the temperature rise greater than the others.

Also, the SC energy can be calculated by integrating the product of current and voltage over the corresponding time intervals. From Figure 8b, assuming similar overlay metals of aluminum with the melting point of approximately 933 K [42], the average critical energy per unit area (E_SCPU) is 3.1, 3.2, and 3.6 J/cm² for the PSI-MOS, TPL-MOS, and DSI-MOS at the approximate time points of 10, 5, and 9 μs, respectively. However, the critical energy (not as E_SCPU) of the SiC UMOSFET may be lower than that of the DMOSFET because the trench devices have smaller chip size for a rated current. As a result, it does not have adequate area to conduct the heat flux generated in the chip, which means that trench devices reach critical energy in shorter times and have lower values of energy than planar devices [55,56]. Anyway, the DSI-MOS reaches the critical energy and the aluminum melting point in longer times than the TPL-MOS.

The DC voltage is intentionally increased to 800 V so as to evaluate the leakage characteristics at approximately 50% of the breakdown voltage. Then, the off-state gate voltage is changed from 0 V to −5 V because it could reduce the channel leakage of the turning-off device caused by high temperature and the decreased threshold voltage. From Figure 9a, the peak electric field of the gate oxide is over 2.5 MV/cm in both the TPL-MOS and PSI-MOS, which is higher than that in the DSI-MOS. The former devices suffer from significant power dissipation during the SC transient, corresponding to amounts of heat generated in the chip. Then, the effective barrier height of SBD may be significantly reduced owing to the coexistence of a high temperature and high electric field, resulting in a severe leakage current of devices after SC transient.

The leakage current can also flow into the source contacts in both the PSI-MOS and TPL-MOS. Then, the heat increases the temperature near the gate–source edges (see the blue arrows in Figure 9b), indicating the possible degradation process of the gate oxide or the source aluminum in it [11,41]. With regard to the DSI-MOS featuring one SBD, the peak electric field of SBD contacts is reduced to half compared with the PSI-MOS, and the T_max is lower than that in the TPL-MOS at the same SC event (see Figure 7b,c). The lowest leakage current mainly flows through the JFET regions and the energy dissipation at the gate–source edges can be effectively decreased. Therefore, by shielding the temperature-sensitive regions of the chip surface and splitting the leakage paths of the source and Schottky contacts, the reliability of the electrodes and gate oxide can be further improved in the proposed DSI-MOS.

We selected a state-of-the-art SiC MOSFET, called the SBD-wall integrated trench MOSFET (SWITCH-MOS) [1,2], to perform a broader comparison. Herein, the main device characteristics are summarized in

Table 1. Comparisons of the characteristics for the SWITCH-MOS, the PSI-MOS, the TPL-MOS, and the DSI-MOS.

Parameter	SWITCH-MOS	PSI-MOS	TPL-MOS	DSI-MOS
Cell pitch (μm)	5	8	5	5.6
BV (V)	1576	1636	1596	1586
a Eox-max (MV/cm)	<1.5	2.78	1.4	0.95
a ESBD-max (MV/cm)	<1.5	0.91	0.33	0.56
b Ron,sp mΩ·cm2)	c 3.3	2.97	2.39	2.75
QGD (nC/cm2)	/	205	169	46
d VFh (V)	>15	6.94	8.25	16.88
Etotal (mJ/cm2)	e 24.8	23.8	22.2	9.1
SC time (μs)	f 6/g 7.7	10	5	9
QGD × Ron,sp (mΩ·MV·cm)	/	8.3	3.3	2.6

^a: when V_DS = 1200 V; ^b: when V_GS = 15 V and I_DS = 500 A/cm²; ^c: when V_GS = 20 V; ^d: when J_h = 10 A/cm²; ^e: when the junction temperature is 175 °C; ^f: when V_DS = 800 V and SBH is 1.2 eV. ^g: when V_DS = 800 V and SBH is 1.51 eV.

.

5. Discussion

Several factors can influence the simulation results. First, SiC MOSFETs exhibit a substantial number of interface traps that are distributed throughout the bandgap [31,33]. This phenomenon contributes to a degradation in the performance of the carrier transport. Thus, these band-tail states give rise to an accurate simulation of the MOS channel properties, which significantly affect the static and dynamic performances of the devices. Then, with the variations in temperature, the interface density of states may change, making it more difficult to extract the electrical characteristics. Secondly, fluctuations in fabrication processes result in different doping concentrations, channel length, oxide thicknesses, etc. [57]. Therefore, the evaluation of these sensitive parameters is of utmost importance and necessitates careful calibration to mitigate their effects on the simulation results. Thirdly, the precise extraction and analysis of interfacial damages are essential for a comprehensive investigation into short-circuit degradation mechanisms. Nevertheless, it is beneficial for researchers to concentrate more on the package when elucidating the mechanisms underlying short-circuit failures [58]. Finally, conducting electrothermal modeling under transient conditions presents significant challenges. Thermal runaway is a critical factor that can contribute to short-circuit failures in SiC MOSFETs. The substantial dataset generated in these scenarios can be instrumental in enhancing simulation accuracy or modeling the underlying failure. Overall, it is essential to highlight that the simulation results may not accurately reflect the actual outcomes. This limitation arises from factors such as simulation accuracy and model bias. However, the findings should be regarded as a general case study rather than definitive results.

In addressing the short-circuit failure mechanism associated with SBD-integrated MOSFET, it is imperative to consider the susceptibility of both the Schottky contact and the gate oxide interfaces. For the Schottky diode, it was found that the leakage current passing through the SBD can be significantly increased at high lattice temperature and high electric field [51]. For the MOSFET, elevated temperatures lead to a reduction in the threshold voltage [4]. Such a decrease triggers a positive feedback mechanism that increases the on-state current, consequently resulting in enhanced Joule heating during short-circuit transients. Furthermore, it is revealed that the formation of a crack in SiO₂ dielectric occurs between the ploy-gate and the source contacts. By comparing Figure 7 and Figure 9, it is noted that high temperatures and high electric fields exist concurrently in the PSI-MOS. The possible failure mechanism for a SC event may be attributed to the leakage current in the Schottky region and the progressive degradation of the gate oxide. Then, upon reaching a sufficiently high lattice temperature, the generated hole current may transition into the p-base regions adjacent to the n+ source contact. This interaction can lead to the activation of the parasitic npn bipolar transistor, thereby increasing the risk of device failure. Consequently, TPL-MOS devices with low E_SBD-max are subject to significant power dissipation and are susceptible to the activation of the npn transistor due to elevated saturation currents and the associated current flow into the p-base regions, as illustrated in Figure 8. However, for the DSI-MOS, T_max primarily manifests in the central regions of the spreading layer located beneath the JFET regions. Furthermore, the proposed device boasts both low E_SBD-max and E_ox-max values. The leakage current of thermionic-field emission ($J_{\mathrm{T}\mathrm{F}\mathrm{E}}$) generated in the bulk regions predominantly diffuses toward the Schottky contacts [52].

$$J_{\mathrm{T}\mathrm{F}\mathrm{E}}={\displaystyle \frac{A^{*}Tq\hslash E}{k}}\sqrt{{\displaystyle \frac{\pi }{2m_{\mathrm{n}}^{*}kT}}}\times exp\left[-{\displaystyle \frac{1}{kT}}\left({\varnothing }_b-∆{\varnothing }_b-{\displaystyle \frac{{\left(q\hslash E\right)}^2}{24m_{\mathrm{n}}^{*}{\left(kT\right)}^2}}\right)\right]$$

(8)

where ${\varnothing }_{\mathrm{b}}$ is the SBH, $\hslash$ is the reduced Planck’s constant (=h/2π), $m_{\mathrm{n}}^{*}$ is the electron effective mass in 4H-SiC, $A^{*}$ is the effective Richardson constant with the value of 146 (A/cm²/K²), and E is the electric field at the Schottky interface. The analysis of Equation (1) reveals that if the SBH is low, there will be a significant increase in leakage current. This situation can trigger a positive feedback loop at elevated temperatures, ultimately leading to a thermal runaway failure mechanism in DSI-MOS devices. Moreover, excessive heat can degrade the gate oxide, resulting in a shift in the threshold voltage. Therefore, it is essential to safeguard the Schottky contacts of DSI-MOS devices from high electric field and high temperature.

We also provide some insights on the reliability and stability of device performance. Firstly, thermal parameters and the packaging material will affect the reliability of the SBD-integrated SiC MOSFET due to the leakage current of SBDs at high temperature. Therefore, it is essential to design the heat sink to keep the device’s junction temperature T_j within safe limits. Secondly, the proposed device is characterized by low switching losses, which makes it advantageous to enhance energy efficiency by increasing the operational frequency. However, rapid fluctuations in current (dI/dt) can result in issues such as overvoltage or gate oscillation. These complications may lead to dynamic threshold voltage instability and diminish the reliability of the gate oxide in SiC MOSFETs [59,60]. To address these concerns, it is advisable to implement the protective devices or fault protection circuits. Additionally, there is a need for improvements in surge current management within the third quadrant of SiC MOSFETs, as extremely high current levels in this quadrant can contribute to bipolar degradation and other reliability challenges in MOSFET operation.

We explore how the DSI-MOS might perform in specific applications. For grid applications, SiC MOSFETs with large chip sizes are designed to support high voltage and high current levels. However, the presence of stacking faults within the thick SiC epitaxial layer has hindered improvements to the body diode characteristics. The proposed approach will eliminate this effect and reduce the number of packages, thus reducing the costs associated with implementing this technology in megawatt (MW) converters. For high-voltage aircraft applications, this design can ensure both high current capacity and high efficiency in bidirectional power converters. Furthermore, it will enhance efficiency and increase switching frequency by eliminating the parasitic inductance found in separately packaged devices.

6. Conclusions

An SBD-integrated UMOSFET with dual Schottky contacts is proposed. This design concept results in low V_F by taking advantage of the properties of three-dimensional surfaces in the trench structure. The DSI-MOS also boasts the lowest value of R_on,sp × E_ox-max = 2.6 mΩ·MV·cm among the three devices. Moreover, Q_GD is separately lower by 73% and 78% compared to the conventional TPL-MOS and PSI-MOS, leading to a more than 50% reduction in its total switching loss. The benefit of the DSI-MOS also lies in the strong shielding effect of the buried p-type layers during the SC event, causing a shift in high temperature and high electric field from the chip surface to the bulk regions. Thus, the DSI-MOS can make itself achieve improved reliability, and reach the critical SC energy and the aluminum melting point in longer times than the TPL-MOS. These results will provide considerable insights into the optimization of the device structure and the understanding of the short-circuit robustness in SBD-integrated SiC trench MOSFETs.