Design of a Sub-6 GHz CMOS Power Amplifier with a High-Q Glass Transformer for Off-Chip Output-Matching Networks

Abstract

This paper investigates and evaluates a compact, high-Q glass transformer with a 3D spiral structure that offers low loss and high area efficiency. Furthermore, we designed a CMOS power amplifier (PA) with an output-matching network implemented using an off-chip high-Q glass transformer to validate its operation. Two transformer types were developed: a five-port transformer with a center-tap and a four-port transformer without a center tap. The high-Q property of the transformer leads to low loss and tight coupling, as evidenced by an increase in maximum available gain (MAG). Compared with an integrated CMOS transformer, the high-Q transformer exhibits significantly lower loss while maintaining similar area and inductance, despite being an external component. A test PA comprising the CMOS PA and the off-chip transformer was evaluated with simulations and measurements, and it was also compared with a fully integrated PA at the simulation level to verify performance improvements. The proposed PA achieved a saturation power of 29.8 dBm, which was 1.7 dB higher than that of the fully integrated PA. The PAE also improved by 11 percentage points, from 32.1% to 43.1% in simulation. The results show substantial performance gains in simulation, while the total area increases only slightly. Measurements show the same trend as the simulations; with shorter bond-wire lengths, the measured results are expected to approach the simulated performance. These findings demonstrate the feasibility of an ultra-compact CMOS–off-chip hybrid PA that delivers high performance while maintaining a footprint comparable to that of a fully integrated PA, enabling applications in compact devices including mobile products.

1. Introduction

With advances in modern integrated circuit (IC) fabrication processes, ICs have been applied across a wide range of fields, spanning both commercial and military domains. Although process technology continues to improve, and printed circuit board (PCB)-based modules are increasingly consolidated into integrated implementations, planar layout constraints and process-driven passive losses still impose fundamental limits. To address these limitations, several approaches have been explored; among them, the hybrid circuit method—placing the IC on a PCB with discrete passive components—has been widely adopted, as discrete passives generally exhibit much higher Q (lower loss) than their on-chip counterparts [1,2,3]. While this approach often achieves better performance than fully integrated solutions, the overall circuit size increases significantly, as shown in Figure 1a,b [4,5,6,7,8,9]. These size–loss trade-offs constrain system performance in applications requiring compact circuits, making this issue increasingly critical.

Modern wireless communications, such as 5G NR, demand not only a small RF circuit area to suit ever-slimmer devices but also sufficient output power and low power consumption. To meet these constraints, CMOS processes are well suited, offering acceptable performance in low-power applications [10,11,12]. However, despite advantages such as small device size and low fabrication cost, CMOS suffers from performance degradation due to limited metal thickness and width as well as significant passive losses associated with substrate effects [13,14,15]. These drawbacks critically affect the PA, which determines the final output of the transmitter.

The overall performance of the power amplifier, including output power and power-added efficiency (PAE), is primarily determined by the output-matching network [16,17,18]. Reducing its loss directly improves performance. This suggests that implementing the output-matching network with ultra-compact external off-chip components can minimize loss while achieving a footprint comparable to that of a fully integrated chip, as shown in Figure 1c.

In this paper, to achieve both minimal size and high performance, a CMOS PA with an external low-loss compact glass-based high-Q transformer was designed and analyzed through simulations and measurements. The target frequency is sub-6 GHz, the 5G NR FR1 band, which is currently the most widely used for 5G communications. The effectiveness of this approach was verified by applying the transformer to the output-matching network of a differential CMOS power amplifier, yielding substantial improvements in output power and efficiency while maintaining a footprint nearly identical to that of an integrated on-chip matching transformer.

2. Design of High-Q Glass Transformer

To fabricate a high-Q transformer with a compact size, a glass-based 3D wire-wound structure was designed. Compared to on-chip CMOS transformers suffering from lossy silicon substrate or bulky off-chip solutions such as discrete components or PCB-based transformers, glass provides a low-loss, high-resistivity substrate that enables both high Q and compact size. Together with through-glass via (TGV) and thick-Cu processing, it enables compact 3D passives with dense vertical interconnects, thereby achieving high-Q characteristics [19,20,21,22]. Photosensitive glass was used as the core of the windings, forming a 3D spiral via etching and metal filling to create interconnects. The glass has a relative permittivity of 5.1 and a loss tangent of 0.036. The top and bottom passivation layers have a relative permittivity of 3.7 and a loss tangent of 0.028. The total height of the transformer is 330 μm, while the glass core height is 280 μm. Interconnect widths range from 40 μm to 60 μm, and the spacing is fixed at 30 μm, which is appropriate for the target frequency range in this work. Two types of transformers were designed: one has a 5-port with center-tap (CT) for the primary winding (Pri.) and no center tap for the secondary winding (Sec.); the other is a 4-port without a center tap. The details of the designed transformers are illustrated in Figure 2.

Figure 3a shows the dimensions of the 5-port transformer. The transformer has a center tap between the two coupled coils, with an inner diameter (ID) of 95 μm. The transformer has six variants: metal widths (Ws) of 50 and 60 μm and turns ratios of 1:1, 1.5:1, and 2:2. The total size of the 5-port transformers is a width of 620 μm and a length ranging from 650 to 845 μm.

The 4-port transformer has a single pair of coupled coils, as shown in Figure 3b, with inner diameters of 140 or 180 μm. Width options were 40 and 60 μm, so four variants were designed and fabricated. The overall size of the transformers is a width of 620 μm and a length ranging from 570 to 650 μm.

The characteristics of the center-tapped transformers are shown in Figure 4 and

Table 1. Characteristics of 5-port transformer at 3.5 GHz.

Turns	Width	Inductance (Primary)	Inductance (Secondary)	Q Factor (Primary)	Q Factor (Secondary)	MAG
1:1	50 μm	1.26 nH	886.0 pH	45.2	36.5	−0.60 dB
	60 μm	1.21 nH	869.7 pH	47.3	38.9	−0.47 dB
1.5:1	50 μm	1.32 nH	1.67 nH	44.6	38.9	−0.51 dB
	60 μm	1.22 nH	1.53 nH	45.0	36.8	−0.51 dB
2:2	50 μm	2.33 nH	2.17 nH	38.7	26.5	−0.47 dB
	60 μm	2.16 nH	2.06 nH	40.0	26.8	−0.47 dB

. There are a total of six center-tapped transformers, with three turn-ratio types (1:1, 1.5:1 and 2:2) and two winding-width variations (50 μm, 60 μm). The reference frequency for these values is 3.5 GHz, which is the target frequency in this work.

The inductance versus frequency characteristics of the transformers are shown in Figure 4a. The primary winding inductances range from 1.21 nH to 2.33 nH, and the secondary inductances range from 869.7 pH to 2.17 nH.

Thanks to the proposed structure, Q factors of primary windings range from 38.7 to 47.3, significantly higher than those of integrated transformers. Secondary-winding Q values are slightly lower (26.8 to 38.9) than the primaries, yet remain much higher than on-chip counterparts. Overall Q versus frequency is shown in Figure 4b.

The maximum available gain (MAG) results, which indicate the minimum loss of the transformers, are shown in Figure 4c. All six transformers exhibit low loss, consistent with their high-Q properties: MAG is no worse than −0.60 dB across all cases, with the best being −0.47 dB.

The 4-port transformers without a center-tap are also evaluated, as shown in Figure 5 and

Table 2. Characteristics of 4-port transformers at 3.5 GHz.

Width	Diam.	Inductance (Primary)	Inductance (Secondary)	Q Factor (Primary)	Q Factor (Secondary)	MAG
40 μm	140 μm	975.7 pH	969.8 pH	46.9	46.9	−0.39 dB
	180 μm	1.10 nH	1.09 nH	50.9	50.6	−0.35 dB
60 μm	140 μm	852.3 pH	846.0 pH	52.3	52.4	−0.37 dB
	180 μm	935.4 pH	931.2 pH	54.5	55.2	−0.32 dB

. With a symmetric, fully coupled structure, both the primary and secondary windings have the same properties, with improved Q and lower loss compared with center-tapped transformers. Four types of symmetric transformers without a center tap were evaluated, with width variations of 40 μm and 60 μm and inner diameters of 140 μm and 180 μm. All four transformers have a 2:2 turn ratio.

Figure 5a shows that the transformer inductances—primary and secondary—are nearly equal with the symmetric structures. The winding inductances range from 852.3 pH to 1.10 nH.

The Q factors are higher than those of the center-tapped transformers, as expected, ranging from 46.9 to 55.2 for both windings. These results indicate that the fully coupled symmetric structure is important for securing high-Q characteristics in differential operation. Detailed results are shown in Figure 5b.

The MAG is also better than that of the center-tapped transformers, with −0.39 to −0.32 dB achieved, as shown in Figure 5c.

3. Design of Power Amplifier with High-Q Glass Transformer

This section presents the design of a power amplifier composed of a CMOS differential PA core and an off-chip high-Q glass transformer, connected on a PCB, where the transformer provides the output-matching network. The PA core was fabricated with a 0.18 μm CMOS process. To verify the advantage of the high-Q transformer, the PA core has no on-chip output-matching network components and provides two differential pads, which are connected directly to the drains through series DC-blocking capacitors. Figure 6a shows the schematic and key specifications of the PA, with all components integrated except the output-matching network. The PA is based on a conventional differential cascode structure incorporating neutralization capacitors and RC feedback to ensure stability [23,24,25]. The common source transistors have a total gate width of 3072 μm and a gate length of 0.18 μm, while the common-gate transistors have a total gate width of 4096 μm and a gate length of 0.35 μm. The entire structure operates from a 3.3 V supply.

The PA core area, excluding the output-matching network, is 762 μm × 898 μm, as shown in Figure 6b. The detailed component values of the PA are summarized in

Table 3. Component values used in the PA.

Component	Value	Component	Value
CIS	884.8 fF	CN	803.6 fF
CIP	517.8 fF	CF	1.90 pF
COP	1.20 pF	RF	607.1 Ω
COS	2.85 pF	RB	2 kΩ

.

Two output-matching networks are compared in this section: one composed of an integrated on-chip transformer and the other employing an external off-chip transformer. Figure 7 shows the dimensions of the employed transformers. The on-chip transformer is designed with a 1:2 turn ratio with a single-turn primary with a 35 μm metal line width and a two-turn secondary with a 20 μm metal line width, resulting in an overall area of 481 μm × 600 μm. The off-chip transformer has a 1:1 turn ratio with two-turn primary and secondary windings, each with a metal line width of 30 μm, and has overall dimensions of 570 μm × 620 μm. Despite being realized as an external component, the off-chip transformer occupies a footprint only about 22.45% larger than the on-chip counterpart.

In RF transformer design, to match the network to the target impedance, the inductance of the windings is mainly considered. The inductances of the transformers are shown in Figure 8a. The on-chip transformer has inductances of 2.2 nH (primary) and 0.67 nH (secondary). While the off-chip transformer has a 1:1 turn ratio, both windings have an inductance of 0.85 nH.

In addition to inductance, the winding length should be considered to achieve tight coupling. In general, a longer coupled line length is required at lower frequencies because the signal wavelength is longer. This trend can be verified using the maximum available gain (MAG). As shown in Figure 8c, the MAG drops markedly at lower frequencies. The on-chip transformer is optimized to minimize loss in the 3–4 GHz band and exhibits a MAG of −1.45 dB at 3.5 GHz. The off-chip transformer has its loss optimum above 3.5 GHz but still shows a much lower loss of 0.37 dB at 3.5 GHz, which is 1.08 dB lower than that of the on-chip transformer.

These results show that the Q factor is a key metric indicating transformer performance. When a transformer has a low Q factor, it not only exhibits high winding loss but also suffers from poor coupling. As shown in Figure 8b,c, the MAG of the high-Q transformer at low frequencies is much higher, and the minimum Q exceeds the peak Q of the integrated transformer, indicating that a high Q enables tighter coupling between the windings.

To practically compare the characteristics of on-chip and off-chip transformers, the large-signal matching impedance of the PA was evaluated through load-pull simulation at a frequency of 3.5 GHz. As shown in Figure 9a, the optimum load impedance for maximum PAE is 6.1 + j9.8 Ω, and both the on-chip and off-chip matching networks are matched to this impedance point for comparison under the same conditions.

Unlike the integrated transformer, the matching network of the off-chip transformer, illustrated in Figure 9b, was designed with the additional effects of bond wires taken into account.

To compare the performance of the two types of transformers applied in actual PAs with simulations, a PA with the on-chip transformer was also designed. As shown in Figure 10, the PA with the external glass transformer maintains a compact footprint comparable to that of the fully integrated design. The fully integrated PA has a width of 1114 μm, while the PA with external matching and the proposed transformer has a width of 1332 μm, which is only 218 μm larger. If the external transformer is placed close to the PA output, the entire footprint could be approximately the same as that of the fully integrated PA.

While the Q of a matching network indicates both passband flatness and loss, if the network has a high-Q property, it exhibits narrower bandwidth but lower insertion loss than a low-Q network [26,27]. This means that by designing the network with a high Q, better performance can be achieved in the target frequency band. As shown in Figure 11a, the gain bandwidth of the proposed PA is narrower than that of the fully integrated PA, but it has slightly higher gain at the center frequency. Power and efficiency performance are also increased: saturation power (P_SAT) increased by about 1.7 dBm, from 28.1 dBm to 29.8 dBm, and peak PAE improved by 11 percentage points, from 32.1% to 43.1%. These simulation results indicate that the high-Q transformer can significantly improve performance due to its low loss behavior, without a considerable increase in the overall PA size.

4. Assembly and Measurement of Power Amplifier with High-Q Glass Transformer

To verify the PA with a compact hybrid configuration, which was implemented with an integrated CMOS PA and a high-Q glass transformer, the PA was assembled on a PCB. The fabricated high-Q glass transformers are shown in Figure 12.

The PCB material was FR-4, which was appropriate for operation at 3.5 GHz. To achieve compactness, the PA and the transformer were placed as closely as possible, considering wire bonding and despite a height gap between the PA and the transformer. If the PA were ground to a proper height of nearly 300 μm or if more advanced assembly (including production-grade wire bonding) were applied, the bond-wire length could be shorter, and the overall size would be more compact, approaching the size of a fully integrated circuit. The assembled PA is shown in Figure 13.

While bond-wire inductance is part of the output-matching network, the length of the bond wire should be considered carefully. To verify the wire length effect, two DUTs were assembled, one with a longer bond wire and the other with a shorter one, as shown in Figure 14. Bond-wire inductance was assumed to be 500 pH for the primary and 400 pH for the secondary when designing the output-matching network.

In the measurements, the power optimum frequency shifted from 3.5 GHz to 2.9 GHz, and power and efficiency performance degraded by additional bond-wire inductance driven by the large height gap between the PA and the transformer as well as laboratory-level assembly limitations that prevented the achievement of a shorter bond-wire length. Comparing the measurement results of the samples in Figure 14a,b, as the bond-wire becomes shorter, the measurements move closer to the simulations in terms of S parameters, power, and efficiency. As shown in Figure 15a, for S₂₁ of the PA, the longer bond wire has a peak gain of 12.3 dB at 3.04 GHz and the shorter bond wire has a peak gain of 13.9 dB at 3.43 GHz, a shift of +0.39 GHz, while the simulated peak gain is 17.7 dB at 3.8 GHz. For large-signal measurements, similar to the S-parameter trend, the measured results move closer to the simulations. In Figure 15b, the shorter bond wire achieves 25.3 dBm, which is 1.3 dBm higher than that with the longer bond wire and is closer to the simulation result of 29.8 dBm. The measured peak PAE also increased as the bond-= wire shortened, from 10.2% to 16.1%, while the simulation result was 43.1%, as shown in Figure 15c. These results are summarized in

Table 4. Comparison between measured results (bond-wire variations) and simulations.

Parameter	Long Bond Wire	Short Bond Wire	Simulation
S21,PEAK (dB)	12.3 @3.04 GHz	13.9 @3.43 GHz	17.7 @3.8 GHz
PSAT (dBm)	24.0 @2.9 GHz	25.3 @2.9 GHz	29.8 @3.5 GHz
PAEPEAK (%)	10.2 @2.9 GHz	16.1 @2.9 GHz	43.1 @3.5 GHz

.

Due to performance degradation caused by bond wires that were longer than expected, modulated-signal results were inferred from simulation, assuming a 6 dB back-off, as is typical for a conventional class-AB PA. The expected average output power and average efficiency at an EVM of −25 dB (≈5.64%) are 22.18 dBm and 24.43%, respectively.

Table 5. Performance comparison with state-of-the-art CMOS PAs.

Ref.	Tech.	Freq. (GHz)	PSAT (dBm)	PAE (%)	Size (mm2)	FoM 2
[28]	0.18 μm	5.3	30.1	18	2.96	0.062
[29]	65 nm	0.33–2.5	19.5–21.5	35–52.4	0.49	0.151
[30]	0.18 μm	2.9–5	25.7–27.2	≈15–25	3.70	0.035
[31] 1	0.13 μm	2.4	20.5	40.9	0.657	0.070
This work 1	0.18 μm	3.5	29.8	43.1	1.20 3	0.343

¹ Simulation results.; ² FoM = (P_SAT (W) × PAE) / size (mm²); ³ width: PA + transformer, height: PA.

shows a summary of the designed PA performance and a comparison with various CMOS PAs. As discussed earlier, the minimum achievable bond-wire length degraded the measured performance and masked the high-Q transformer’s performance improvement. Therefore, simulation results are presented to clearly demonstrate the performance gains. As shown by the figure of merit (FoM) for power and efficiency normalized by area, the high-Q transformer demonstrates a significant benefit in simultaneously achieving size miniaturization and PA performance improvement.

5. Conclusions

This study verifies the utility of an ultra-compact high-Q transformer for sub-6 GHz operation through simulation and fabrication, followed by validation in real-world operation when deployed as an off-chip output-matching network for a CMOS-integrated PA. While a fully integrated CMOS PA offers compactness suitable for ultra-small devices, it suffers from relatively low performance, including power efficiency; therefore, the high-Q glass transformer fabricated in this study is a promising alternative, anticipated to substantially improve the PA’s overall performance without a considerable increase in the overall circuit area. The transformer was fabricated using a photosensitive glass etching process and features high-aspect-ratio double-sided interconnects. Before fabrication, optimum winding width, spacing, the number of turns, and other parameters for sub-6 GHz PA load-pull impedance were identified using electromagnetic (EM) simulations. The simulation results show that the high-Q glass transformer can provide significantly improved performance when applied to the PA, especially in output power and efficiency compared with a fully integrated output transformer. The saturated output power increased by 1.7 dB from 28.1 to 29.8 dBm, and the peak PAE improved by 11 percentage points, from 32.1 to 43.1%. After the PA and transformers were fabricated, multiple PAs were assembled to mitigate uncertainty from the bond-wire inductance, which directly affects output-matching impedance as well as process variation in the core PA. The measurement results showed a clear trend: as the bond wire shortened, the measurements became closer to the simulation results. Improved results are expected if the PA substrate is ground to a height near that of the fabricated transformers (≈300 μm) and the assembly uses production-grade processes. The compact high-Q transformers, both as a standalone concept and when combined with a CMOS PA, demonstrate the feasibility of achieving miniaturization and high performance together.