Capacitor-Less LDO with Fast Transient Response Implemented via Bulk-Driven Technique

Abstract

Improving the transient response performance is a critical challenge in low-dropout regulator (LDO) design. This paper proposes a novel on-chip capacitor-less LDO based on substrate technology implemented in an SMIC (Semiconductor Manufacturing International Corporation) 0.18 μm CMOS (complementary metal oxide semiconductor technology) process. Central to this innovation is a fast response loop between the PMOS driver’s body and gate, which leverages the body effect to enhance driver control without complex bulk-driven techniques. The proposed LDO achieves a quiescent current of 4.5 μA, an efficiency of $88\%$, an overshoot/undershoot of $12\mathrm{mV}/22\mathrm{mV}$, and a settling time of 1.2 μs. The comparative analysis confirms that this structure increases the maximum load current and reduces the loop response time relative to those for conventional LDOs. These results validate a significant improvement in the transient performance, marking an important advance in integrated voltage regulator technology.

1. Introduction

Recent advancements in information technology have enabled the ubiquitous deployment of electronic instruments across diverse domains. Innovations in artificial intelligence, the Internet of Things (IoT), and 5G technology are driving the evolution of electronic systems towards enhanced performance and miniaturization. Within these systems, power management modules are indispensable, with low-dropout linear regulators (LDOs) serving as critical components.

LDOs are broadly categorized into two types: conventional LDOs requiring external capacitors and capacitor-less LDOs. The former necessitate larger external capacitors to ensure system stability, which occupy a substantial circuit area, leading to an increased device footprint, a reduced integration density, and higher costs. In contrast, capacitor-less LDOs offer superior miniaturization, higher integration, and improved cost effectiveness. Consequently, designing capacitor-less LDOs with a fast transient response holds significant value in applications demanding low supply voltages, particularly where an ultra-low quiescent current and the elimination of external capacitors are critical. Such scenarios include IoT sensor nodes, medical implants, and portable medical monitors, where stringent power efficiency constraints and extreme miniaturization requirements are paramount.

In existing reports, many scholars have proposed various methods to enhance the transient response of capacitor-less LDOs. Reference [1] introduces an enhanced multi-path nested Miller compensation (EMNMC) scheme that achieves a loop bandwidth exceeding 100 MHz, but its static current is as high as 112 μA, which fails to meet low power requirements. In 2019, reference [2] designed a class AB error amplifier and adopted a power transistor current enhancement structure. The LDO had a response time of 220 ns during a 100 ns load transition from 1 mA to 100 mA, indicating that the slope enhancement circuit did not significantly improve the response speed of the LDO. Reference [3] designed a capacitance-free LDO aimed at enhancing the frequency compensation stability and proposed a dual active feedback frequency compensation scheme. Although the static current is 14 μA, which meets the requirements in terms of the stability and transient response, its response time is as long as 3.2 μs, which fails to meet the requirement of a fast response. In 2021, reference [4] introduced a low-power fast-transient-response LDO based on a super transconductance structure. During the edge time of the maximum change in the load current of 20 ns, the peak output voltage is less than 11.2 mV, and the response time is 0.054 μs. However, its static current is as high as 124 μA, and the LDO also requires an additional external large capacitor to ensure system stability. These studies generally indicate that the existing methods predominantly enhance the performance by incorporating additional circuit structures at the gate terminals of the power transistors, such as augmenting transient circuits to increase charge and discharge currents [5,6]. However, this approach inevitably leads to increased circuit power consumption and a larger chip area and fails to address the low-voltage-difference problem [7,8]. The shortcomings of these conventional methods are that they either necessitate a trade-off in the bandwidth or response speed at the expense of an elevated static current or fail to provide a fundamental solution for achieving a fast response under low-voltage conditions. Consequently, a more optimized solution is urgently required.

This study mainly explores the scientific issues in substrate-driven capacitor-less LDOs, clarifies the high-power-consumption problem in the fast response circuit module structure of an LDO, and proposes a novel substrate-driven enhanced-transient-response LDO structure, as shown in Figure 1. Taking PMOS power transistors as an example for the analysis, two loops are formed by adding substrate driving loops. The main loop ensures a high loop gain to maintain the accuracy of the output voltage, while the substrate loop has a higher loop bandwidth to shorten the loop stabilization time. The substrate terminal of the power transistor driven by the substrate amplifier is biased in the same direction as the gate terminal to reduce the threshold voltage of the PMOS transistor. This enables operation at lower supply voltages, increases the overdrive voltage, facilitates a larger current handling capability, and ultimately improves the transient characteristics. Based on an analysis of the existing methods’ shortcomings, this study aims to provide an effective approach to achieving a fast transient response with low power consumption.

The rest of this article is arranged as follows: Section 2 introduces the basic structure of an LDO and the details of each module. Section 3 provides a detailed introduction to the design of an LTE-LDO circuit system based on substrate driving technology. Section 4 describes the layout design and overall layout arrangement and analyzes simulation verification data of the DC characteristics, AC characteristics, and transient characteristics of the circuit in detail. The results are quantified as quality factors and compared with other research results. Section 5 provides an overview and summary of all of the work presented in this paper.

2. An Overview of a Typical LDO

As shown in Figure 2, the diagram illustrates the typical structure of the basic modules of an LDO [9].

As an important part of the voltage regulator, the LDO can stabilize the output voltage under different input voltages and output currents [10,11]. When the output stage circuit switches from the standby state to the working state, the discharge of the load capacitor $C_L$ will cause the output voltage to decrease, and the feedback signal is provided to the positive input of the error amplifier through the resistance voltage divider feedback network [12,13]. Compared with the reference voltage, the output signal of the error amplifier is adjusted, and then the power tube is driven to generate more current, and finally, the output voltage of the LDO is raised. Similarly, when the output stage circuit switches from the working state to the standby state, the excess charge will charge the load capacitor to increase the output voltage [14]. The feedback signal is transmitted to the input of the error amplifier through the feedback network and compared with the reference voltage; the output signal of the amplifier is adjusted; and the power device is driven to reduce the external current and reduce the output voltage of the LDO [15]. Figure 2 shows an equivalent working schematic diagram of the LDO. The power device is equivalent to the adjustable resistance of $R_P$, and the load and feedback network are equivalent to the impedance of $R_L$ and $R_F$. The power resistance $R_P$ is adjusted by dynamically adjusting the feedback voltage ($V_F$) to complete the voltage regulation process.

3. The Proposal Substrate-Driven LTE-LDO

3.1. The Overview

This section elaborates on the implementation of substrate-driven technology in analog integrated circuits, focusing on the proposed LTE-LDO (low-power transient-enhanced low-dropout regulator). Conventional fast-transient-response LDO architectures typically incorporate slew-rate enhancement circuits, fast feedback loops, error amplifiers, and over-/undershoot detection modules. Departing from the established approaches, we propose a novel capacitor-less topology that eliminates the off-chip capacitance requirements. The key innovation lies in the integration of a substrate-driven fast-response loop, which applies same-direction biasing to both the gate and substrate terminals of the power transistor. This configuration reduces the threshold voltage and enhances the transconductance, thereby improving the current handling capability and transient performance. Figure 3 presents a system block diagram of the LTE-LDO architecture.

Figure 4 presents a schematic diagram of the core circuit structure of the LTE-LDO designed in this section. The complete circuit consists of the main error amplifier, the substrate amplifier, and the power stage. To ensure high loop gain in the main loop, a super AB-class transconductance amplifier is used as the main error amplifier. To ensure the stability of the main loop, a compensation structure is also added to the main loop. The substrate loop employs a five-transistor amplifier structure to increase the loop bandwidth and reduce the loop response time.

3.2. The Main Error Amplifier

A folded cascode amplifier (FC) is often used in the error amplifier structure in LDO design. This traditional error amplifier is widely used and has a stable structure. However, its tail current source leads to a limited range of current variation at the gate of the power tube and low charging and discharging currents. In order to solve this problem, JuAn A. Galan et al. proposed the class $AB$ transconductance amplifier OTA [16]. This structure can drive the power transistor in the LDO through the adaptive bias current of the input transistor; to maximize the current efficiency, it can achieve a high output voltage swing at a low static current; and it can improve the slew rate (SR) of the amplifier, increase the charge and discharge currents of the power tube gate, and, finally, improve the transient characteristics of the LDO. In addition, the equivalent resistance at the output of the amplifier is low, which will bring a poor loop gain. In order to improve the gain and achieve a good adjustment rate, this paper adds the local common-mode feedback (LCMFB) structure based on the class $AB$ OTA circuit. It can be increased to the original circuit $g_m$R times so as to effectively improve the adjustment rate. A detailed comparative quantitative analysis of the performance of the three amplifiers is presented below.

3.2.1. The Slew Rate

Figure 5a shows a schematic of the complete circuit of the FC amplifier. It is represented by a tail current source composed of MOS transistors denoted as $I_t$, where $M_1$ and $M_2$ are input transistors; $M_3$, $M_4$, $M_5$, and $M_6$ form the cascode current mirror; $M_7$ and $M_8$ constitute cascode transistors; and $M_9$ and $M_{10}$ serve as current sources. $V_{N1}$, $V_{N2}$, and $V_p$ are the bias voltages for $M_9$ and $M_{10}$, $M_7$ and $M_8$, and $M_5$ and $M_6$, respectively. The output voltage swing ($V_{ovs}$) of this amplifier can be expressed as

$$V_{OD9,10}+V_{OD7,8}\le V_{OVS1}\le VDD-V_{OD3,4}-V_{OD5,6}$$

(1)

$V_{OD}$ represents the overdrive voltage of the MOS transistor, and VDD denotes the power supply voltage of the amplifier.

Figure 5b provides a complete schematic of the class $AB$ transconductance amplifier. The core consists of the adaptive bias current source formed by $M_3$ and $M_4$, the input transistors $M_1$ and $M_2$, and the fixed tail current source transistors $M_{11}$ and $M_{12}$, with the remaining transistors $M_7$ and $M_9$, $M_5$ and $M_6$, and $M_8$ and $M_{10}$ serving as current mirror replication transistors. $M_6$ and $M_{10}$ act as output load transistors. The output voltage swing of this amplifier is

$$V_{OD10}\le V_{OVS2}\le VDD-V_{OD6}$$

(2)

The output voltage swing rate of the amplifier is calculated as follows.

$$SR={\displaystyle \frac{I_o}{C_L}}={\displaystyle \frac{V_o}{t}}$$

(3)

$I_o$ is the output current of the amplifier, $C_L$ is the load capacitance, and t is the settling time of the output.

In the SMIC 180 nm mmrf process, the overdrive voltage $V_{OD}$ of the n33 series transistors is usually around 200 mV. As indicated by Equation (3), under the same power supply voltage conditions, the output swing of the class $AB$ amplifier is significantly higher than that of the FC amplifier. In an LDO, when driving power transistors of the same size at the gate end, the charging and discharging currents of the former are greater than those of the latter. The working principle of the adaptive bias current source in this structure is as follows: when the output load current of the LDO changes, the output voltage is fed back to the input, increasing or decreasing the currents of $M_1$ and $M_2$. Since $M_{11}$ and $M_{12}$ provide a fixed current source IB, the currents of $M_3$ and $M_4$ dynamically increase or decrease in the same manner. The changing current $I_1$ passes through $M_7$, $M_9$, $M_5$, and $M_6$ to the output. In comparison to the FC amplifier, this output current $I_o$ is not limited by the bias current source, thereby significantly increasing the charging and discharging currents and benefiting an improvement in the transient response.

3.2.2. DC Gain

By analyzing the internal nodes of the amplifier in Figure 5b, it can be observed that due to the diode-connected configuration of $M_7$ and $M_8$, points A and B are low-impedance nodes. The DC gain of this amplifier can be expressed as

$$A_{V1}=2g_{M_{1a,2b}}{g}_{m9,10}{R}_{X,Y}{R}_O$$

(4)

$g_{M_{1a},2b}$ and $g_{m9,10}$ are the equivalent transconductances of $M_{1a,2b}$ and $M_{9,10}$, respectively. $R_{X,Y}$ represents the equivalent resistance between nodes X and Y. $R_o$ denotes the output impedance of the amplifier. Further analyzing the loop gain, $R_{X,Y}$ can be approximated as and simplified to

$$A_{V1}=2{\displaystyle \frac{g_{m9,10}}{g_{m7,8}}}{g}_{M_{1a},2b}{R}_O=2K_1{g}_{m9,10}{R}_O$$

(5)

$g_{m7,8}$ represents the transconductance of $M_{7,8}$. It can be seen that $K_1$ denotes the ratio of the current mirror. Clearly, without adding additional static current, the gain of traditional class $AB$ amplifiers is limited by $K_1$ and cannot meet the requirements for high voltage regulation adjustment rates in low-power conditions in LDOs.

Therefore, to address this issue, the proposed LDO without off-chip large capacitors utilizes a super class $AB$ error amplifier with local common-mode feedback [17].

As shown in Figure 6, a resistor is added in the red section on the basis of the traditional $AB$ amplifier, increasing the AC impedance at points A and B while keeping the DC impedance unchanged, effectively boosting the amplifier’s gain. At this point, the DC gain of the amplifier can be expressed as

$$A_{V1}=2g_{M_{1a},2b}{g}_{m9,10}{R}_{1,2}{R}_O$$

(6)

$R_{1,2}$ are the equivalent resistances at points A and B, serving as the feedback resistors used in LCMFB [18,19], significantly smaller than $R_{1a,2b}$ and $R_{7,8}$. Combining the above expressions leads to the conclusion that compared to the traditional structure, adding feedback resistors $R_{1,2}$ does not consume additional static current, effectively enhancing the gain. However, $R_{1,2}$ should not be set too large, with values typically ranging between 400 k and 1 M; otherwise, this pole will shift to lower frequencies, resulting in a decreased phase margin and posing loop stability issues.

3.2.3. The Output Current

Compared to a traditional class $AB$ transconductance amplifier, the amplifier shown in Figure 6 significantly enhances the charging and discharging currents at the gate of the power transistor. Next, a detailed quantitative analysis will be conducted [20].

Assuming both amplifiers are driving the same power transistor, when Figure 5 acts as the error amplifier, transitioning from a light load to a heavy load current in the LDO causes the output voltage $V_{out}$ to instantaneously drop by $\delta$V. This change is fed back to the input of the amplifier, causing the gate voltages of $M_{1a}$ and $M_{2a}$ to decrease by a factor of $\alpha$ times $\Delta V$. Since the source voltage of $M_{1a}$ is constant, the current flowing through $M_{1a}$, denoted as $I_1$, increases. As the bias current is fixed, the source voltages of $M_{2a}$ and $M_{2b}$ also decrease, resulting in a decrease in the current flowing into $M_{2b}$, denoted as $I_2$. Here, $\alpha$ represents the feedback coefficient for output impedance voltage division. $I_1$ and $I_2$ can be represented as follows:

$$I_1={\displaystyle \frac{1}{2}}K{\beta }_{1a}{\left(\sqrt{{\displaystyle \frac{2I_B}{{\beta }_{1a}}}}+\alpha \Delta V_{\mathrm{under}}\right)}^2$$

(7)

$$I_2={\displaystyle \frac{1}{2}}K{\beta }_{2b}{\left(\sqrt{{\displaystyle \frac{2I_B}{{\beta }_{2b}}}}+\alpha \Delta V_{\mathrm{under}}\right)}^2$$

(8)

$\beta$, appearing in all the expressions in this paper, is defined as

$$\beta =\mu C_{\mathrm{ox}}{\displaystyle \frac{W}{L}}$$

(9)

The power tube gate discharge current $I_{disc}$ can be defined as follows.

$$I_{\mathrm{disc}}\approx {\displaystyle \frac{1}{2}}K{\beta }_{1a}{\left(\sqrt{{\displaystyle \frac{2I_B}{{\beta }_{1a}}}}+\alpha \Delta V_{\mathrm{under}}\right)}^2$$

(10)

When the output of the LDO without an off-chip large capacitor switches from a heavy load to a light load, overshoot voltage will be generated. At this time, the charging current $I_c$ of the power tube gate can be expressed as follows.

$$I_{\mathrm{c}}\approx {\displaystyle \frac{1}{2}}K{\beta }_{2b}{\left(\sqrt{{\displaystyle \frac{2I_B}{{\beta }_{2b}}}}+\alpha \Delta V_{\mathrm{under}}\right)}^2$$

(11)

Compared to the traditional amplifier structure in Figure 5b, to enhance the switching speed of the power transistor’s gate, this paper employs an efficient error amplifier, as shown in Figure 6. When the proposed LDO generates an undershoot voltage $V_{\mathrm{under}}$, the current $I_3$ increases while $I_4$ decreases, causing an increase in the voltage at node A and a decrease in the voltage at node B. This results in an increase in the current $I_{M9}$ flowing into M10 and a decrease in the current $I_{M10}$ flowing into M10. Therefore, the charging current $I_c$ is described as

$$I_c\approx -I_{M10}\approx {\displaystyle \frac{{\beta }_{9,10}}{2}}\left[{\displaystyle \frac{{\beta }_{1a,2b}}{2{\beta }_{7,8}}}+{\displaystyle \frac{{\beta }_{1a,2b}^2{R}_{1,2}^2}{16}}{\left(\alpha \Delta V_{\mathrm{under}}\right)}^4\right]$$

(12)

When an overshoot voltage is generated, the discharge current $I_{disc}$ of the power tube can be defined as follows.

$$I_{disc}\approx -I_{M9}\approx {\displaystyle \frac{{\beta }_{9,10}}{2}}\left[{\displaystyle \frac{{\beta }_{1a,2b}}{2{\beta }_{7,8}}}+{\displaystyle \frac{{\beta }_{1a,2b}^2{R}_{1,2}^2}{16}}{\left(\alpha \Delta V_{\mathrm{under}}\right)}^4\right]$$

(13)

Through the large-signal analysis, it can be seen that compared with the traditional topology, when the error amplifier of super class $AB$ drives the power tube under the same static power consumption, the output terminal can generate a fourth power charge and discharge current. Therefore, the structure shown in Figure 6 greatly increases the conversion rate of the power transistor gate, which greatly improves the transient response.

3.2.4. Small-Signal Analysis

Figure 7 shows the equivalent small-signal flow chart of the error amplifier proposed in this paper. There are a few caveats to the flow chart before calculating the system’s functions:

(1)

There is a Flipped Voltage Follower (FVF) structure [21] in the amplifier. When the input tube changes $\Delta V_{\mathrm{in}}$, the branch of the FVF structure will change about $-\Delta V_{\mathrm{in}}$. To simplify the analysis, a change of 2 times is directly assumed in the flow chart.

(2)

$R_B$ and $C_B$ are the equivalent resistance and capacitance of point B. The size of $R_B$ is the feedback resistance $R_{1,2}$, and the value of $C_B$ is small due to the small size of M10.

(3)

$R_O$ and $C_O$ are the equivalent capacitance and resistance of the amplifier output node. Since the amplifier drives the large-size load tube, the value of $C_O$ should not be ignored.

According to the above block diagram, the system function of the super class $AB$ error amplifier can be expressed as follows.

$$A_{v1}\left(s\right)={\displaystyle \frac{2g_{m2b}{g}_{m10}{R}_{1,2}{R}_o}{(s{C}_B{R}_{1,2}+1)(s{C}_o{R}_o+1)}}$$

(14)

The results show that the low frequency is the same as that in Equation (7), and the amplifier has two poles. Since the equivalent capacitance at the output of the amplifier is much larger than that at point B, it can be determined that the main pole is located at the output of the amplifier, which can be expressed as

$$P_0=-{\displaystyle \frac{1}{R_o{C}_o}}$$

(15)

The secondary primary poles are located at two feedback resistor nodes A and B, which can be expressed as follows.

$$P_1=-{\displaystyle \frac{1}{R_{1,2}{C}_B}}$$

(16)

The gain bandwidth product $GB{W}_{SAB}$ of the amplifier can be expressed as follows.

$$GB{W}_{SAB}={\displaystyle \frac{2g_{m2b}{g}_{m10}{R}_{1,2}}{C_o}}$$

(17)

Further, it can be expressed as follows.

$$GB{W}_{SAB}={\displaystyle \frac{4\sqrt{{\beta }_{M_{2b}}{I}_{D{M}_{2b}}}\sqrt{{\beta }_{m10}{I}_{Dm10}}{R}_{1,2}}{C_o}}$$

(18)

In order to ensure the stability of the loop, the resistance value of $R_{1,2}$ should not be too large and should be set within 100 k. Moreover, the current flowing through each branch of the amplifier is small, so $GB{W}_{SAB}$ will be limited. According to the above gain expression, this amplifier has higher gain but a smaller bandwidth.

3.2.5. The Substrate Amplifier

The substrate amplifier employs a low-power, stable five-transistor amplifier, as illustrated in Figure 8.

In the diagram, $M_{b1}$ and $M_{b2}$ serve as input transistors, with $M_{b1}$ connecting to the feedback voltage at its gate and $M_{b2}$ to the reference voltage. $M_{b3}$ and $M_{b4}$ function as the load current mirrors, Vbias provides a fixed bias for the tail current mirror $M_{b5}$, and the output terminal connects to the substrate of the power transistor. The function, pole frequency locations, and bandwidth $GB{W}_{ot{a}_b}$ of this amplifier can be expressed as

$$A_{v2}\left(s\right)={\displaystyle \frac{g_{m\_b1}{R}_{o\_b}}{s{C}_b{R}_{o\_b}+1}}$$

(19)

$$P_0=-{\displaystyle \frac{1}{C_b{R}_{o\_b}}}$$

(20)

$$GB{W}_{ota\_b}={\displaystyle \frac{g_{m\_b1}}{C_b}}={\displaystyle \frac{\sqrt{I_{tail}{\beta }_{b1}}}{C_b}}$$

(21)

$R{o}_b$ represents the output resistance of the substrate amplifier, and $C_b$ denotes the total parasitic capacitance of the power transistor substrate, which can be expressed as

$$C_b=C_{bs\_p}+C_{bd\_p}$$

(22)

These parameters, respectively, represent the parasitic capacitances at the source and the drain of the power transistor substrate, which are significantly lower than the gate-source parasitic capacitance $C_{gs}$ of the power transistor. The bandwidth is directly proportional to the tail current, indicating a large gain–bandwidth. On the other hand, the DC gain is inversely proportional to the square root of the tail current, allowing for appropriate adjustment of the tail current value to meet the high-bandwidth and low-gain requirements of the substrate amplifier.

3.2.6. The Frequency Response

In order to analyze the frequency response of the overall LTE-LDO, Figure 9 shows a block diagram of transconductance of the complete circuit under small signals [22], in which case the loop structure is not affected, as reflected.

There are two loops in the system, blue and red, as shown in the figure [23]. Among them, the first loop mainly ensures high loop gain so that the output steady-state voltage can be stabilized at the ideal output value, and the second loop mainly ensures a high loop bandwidth so that the power tube can sense that the output load current changes faster and ensure a fast response of the loop. This is because loop 1 cannot guarantee a high bandwidth due to the limitation of static power consumption; in general, the substrate’s transconductance $g_{mb}$ is about 0.25 times the gate-source transconductance $g_m$, so the loop gain is low under the same conditions, but the tail current can be adjusted to ensure a high loop bandwidth. In the following, the specific expressions of the signal gain, bandwidth, and pole position of the two loops will be detailed, respectively.

3.2.7. The Main Loop

In order to ensure the stability of loop 1, the Miller capacitor Cm is connected to the gate end of the power tube and the output end of the LDO, and the equivalent capacitance of the gate end is increased to separate the main pole and the secondary main pole further, and the secondary main pole is pushed to a higher frequency. However, due to the introduction of a new signal path, a zero in the right-half plane is generated, and the PM drops 90°, which deteriorates the stability. Therefore, it is necessary to add $R_z$ by setting the value of the resistance; the zero in the right-half plane can be transformed into a zero in the left-half plane or can disappear so as to improve the phase margin and ensure the high stability of the loop. The complete results of calculation of the transfer function of loop 1 are

$$H_v^1\left(s\right)={\displaystyle \frac{2g_{m2b}{g}_{m10}{R}_{1,2}{r}_o\alpha }{b\{a(s{r}_o{C}_L+1)+\left[(s{r}_o{C}_L+1)(s{R}_z{C}_m+1)+s{r}_o{C}_m\right]\left(g_{m,p}+\frac{s{C}_o{R}_o+1}{R_o}\right)\}}}$$

(23)

a and b are denoted as follows:

$$a=s{C}_m{r}_o-g_{m,p}(s{C}_m{R}_z+1)$$

(24)

$$b=s{C}_B{R}_{1,2}+1$$

(25)

The error amplifier is equivalent to the overall structure’s transconductance, and the transfer function after simplification can be approximately expressed as follows.

$$H_v^1\left(s\right)\approx {\displaystyle \frac{2g_{M_{2b}}{g}_{m10}{g}_{m,p}{R}_{1,2}{r}_o{R}_0\left[1+s{C}_m\left(R_z-\frac{1}{g_{m,p}}\right)\right]}{c{s}^2+ds+r_o{C}_L\left[R_0(C_o+C_m)+R_m{C}_m\right]+R_m{C}_m{R}_0{C}_o}}$$

(26)

c and d are denoted as follows:

$$c=r_o{R}_0{R}_m{C}_o{C}_L{C}_m$$

(27)

$$d=r_o\left(C_L+C_m+g_{m,p}{R}_0{C}_m\right)+R_0(C_o+C_m)+R_m{C}_m$$

(28)

From the above transfer function, it can be seen that there are mainly two left half-plane poles in this loop, which are $P_0$ and $P_{1,1}$, respectively. The equivalent impedance of the common-mode feedback resistance point inside the amplifier is small, and the capacitance $C_B$ is very small, so the poles caused by this node are located at a very high frequency and can be ignored in the analysis. The primary pole is located at the output of the amplifier, while the secondary primary pole is located at the output of the LDO, which is expressed as follows.

$$P_0=-{\displaystyle \frac{1}{R_0{C}_m{g}_{m,p}{r}_o}}$$

(29)

$$P_{1,1}=-{\displaystyle \frac{g_{m,p}}{C_L}}$$

(30)

The specific expression of $Z_0$ is as follows:

$$Z_0={\displaystyle \frac{1}{C_m\left(\frac{1}{g_{m,p}}-R_z\right)}}$$

(31)

If the value of $R_z$ is very small, the loop will produce a zero point in the right-half plane, which will deteriorate the loop’s stability. However, when $R_z$ is appropriately chosen, the loop will produce a zero point in the left-half plane $Z_0$, which will improve the phase margin (PM) and ensure loop stability. This loop bandwidth can be approximated as follows.

$$GB{W}_{LTE}^1={\displaystyle \frac{2g_{M_{2b}}{g}_{m10}{R}_{1,2}}{C_m}}$$

(32)

Following from the expression, $g_{m_p}$ of the LDO will increase and the output resistance will increase under small load currents, which will cause the output poles to move to low frequencies, leading to a decrease in the phase margin and the worst loop stability. Figure 10 shows a diagram of the simulated frequency response of loop 2 without an AC signal at 100 μA. The results show that the DC gain of loop 1 is about 67 dB, the bandwidth is 1.6 MHz, and the phase margin after compensating for the Miller capacitor and the zero resistance is about 53°. At this time, the circuit is operating at the minimum load current. Its phase margin is the worst, so the stability of loop 1 under a full load current is guaranteed.

3.2.8. The Substrate Driving Loop

The transfer function of loop 1 can be expressed as

$$H_v^2\left(s\right)={\displaystyle \frac{g_{m\_b1}{g}_{m\_b}{R}_{o\_b}{r}_o}{(s{C}_b{R}_{o\_b}+1)(s{r}_o{C}_L+1)}}$$

(33)

The loop mainly has two left-half plane poles, $P_0$ and $P_{2,1}$, respectively. Also, because there is no Miller capacitor, the main pole $P_0$ is located at the output end of the LDO, and the other pole $P_{2,1}$ is at the output end of the amplifier at the substrate of the power tube. The specific expression is as follows:

$$P_0=-{\displaystyle \frac{1}{r_o{C}_L}}$$

(34)

$$P_{2,1}=-{\displaystyle \frac{1}{R_{o\_b}{C}_b}}$$

(35)

The bandwidth of loop 2 can be expressed as follows.

$$GB{W}_{LTE}^2={\displaystyle \frac{g_{m,b1}{g}_{mb,p}{R}_{o,b}}{C_L}}$$

(36)

Figure 11 shows the simulation of the frequency response of loop 1 without the AC signal passing through loop 2 under a 100 μA load current. The results show that the DC gain of this amplifier is only 37 dB, but the bandwidth reaches 19 MHz, indicating that the response speed of the loop is fast, which is approximately consistent with the theoretical value.

3.2.9. The Complete System

The total open-loop gain is as follows.

$$H_v\left(0\right)=H_v^1\left(0\right)+H_v^2\left(0\right)$$

(37)

The total open-loop gain is expanded as

$$H_v\left(0\right)=-\left(2g_{M_{2b}}{g}_{m10}{g}_{m,p}{R}_{1,2}{R}_o{r}_o+g_{m\_b1}{g}_{m\_b,p}{R}_{o\_b}{r}_o\right)$$

(38)

It can be seen that the LTE-LDO has a higher gain with an open-loop frequency response at any frequency. In the full load range, the frequency of the main pole in the system $P_0$ is fixed at the output end and will not change with a change in the output load current. The equivalent capacitance of the substrate of the power tube is mainly composed of $C_{bs}$ and $C_{bd}$ and is much smaller than the equivalent capacitance $C_o$ of the gate. Therefore, the secondary main pole of the whole system is located at the output of the main amplifier. Since the substrate amplifier meets the high-bandwidth demand, a large load current is needed, so a < b, and the third pole is $P_{1,2}$. In order to study $Z_1$ further, the transfer function is added. Since the two loops share the output load, $g_{m_p}$ and $g_{m{b}_p}$ and the subsequent power stage circuits can be approximately ignored for convenience of the calculation, and only the independent poles of the two amplifiers are considered to obtain the total system’s function, as shown below:

$$H_v^1\left(s\right)\approx A_{v1}\left(s\right)g_{m,p}{r}_o{\displaystyle \frac{1+\frac{s}{Z_0}}{(s{r}_o{C}_L+1)}}$$

(39)

$$H_v^2\left(s\right)\approx A_{v2}\left(s\right)g_{m\_b,p}{\displaystyle \frac{r_o}{(s{r}_o{C}_L+1)}}$$

(40)

$$A_v\left(s\right)\approx A_{v1}\left(0\right){\displaystyle \frac{1}{1+\frac{s}{p_{1,1}}}}+A_{v2}\left(0\right){\displaystyle \frac{1}{1+\frac{s}{p_{2,1}}}}$$

(41)

This can be simplified into

$$A_v\left(s\right)\approx A_{v1}\left(0\right)A_{v2}\left(0\right){\displaystyle \frac{1}{\left(1+\frac{s}{p_{1,1}}\right)\left(1+\frac{s}{p_{2,1}}\right)}}$$

(42)

The above expression represents the equivalence of the two loops to a single-pole system, with the zero point generated by multiple loops denoted as $Z_1$, given that it is greater than $GB{W}_{ot{a}_b}$.

$$A_{v1}\left(0\right)\times p_{1,1}\gg A_{v2}\left(0\right)\times p_{2,1}$$

(43)

Solving for the zero point $Z_1$ generated by the two loops approximately,

$$Z_1\approx {\displaystyle \frac{p_{1,1}{A}_{v1}\left(0\right)}{A_{v2}\left(0\right)}}$$

(44)

The zero point introduced is located at the frequency where the gains of the two amplifiers are equal. This zero point is greater than the frequency of pole $P_{1,1}$, compensating for the phase drop caused by the second pole, thereby improving the phase margin. In order to show the excellent frequency response of the LDO with the substrate driving loop, Figure 12 shows a diagram of the frequency response of an LDO without a substrate driving loop and an LDO with a substrate driving loop in this design. The figure shows that the DC gain is increased from 75 dB to 77 dB, and the bandwidth is increased from 2.5 MHz to 6.9 MHz.

This shows that $Z_1$ plays a compensatory role, broadening the loop bandwidth and improving the loop response speed without reducing the phase margin.

3.3. Summary

This section first summarizes the technical structure of traditional fast-transient-response LDOs and then provides an overview of the LTE-LDO. It proceeds with a structural analysis, sequentially introducing the design and implementation of the main error amplifier and the substrate amplifier. Finally, it analyzes the frequency response of the complete structure.

4. Layout Design and Verification

The LDO designed in this paper is based on the SMIC 0.18 μm process. The design and simulation were performed using Cadence IC software. Figure 13 shows the whole layout of the LTE-LDO system, where the bipolar transistor has a large area; R is the local common-mode feedback resistance; C is the Miller capacitor; M-OTA and B-OTA, respectively, represent the error amplifier of the main loop and the error amplifier of the substrate loop; MP represents the power transistor; and the layout’s area is 0.0417 mm².

4.1. LTE-LDO Simulation Verification Results

This section shows the detailed post-simulation results of the overall LTE-LDO circuit, which include the DC, AC, and transient characteristics under the simulation conditions of a standard tt process with a supply voltage of 2.5 V and a temperature of 27 °C.

4.1.1. DC Characteristics

(1)

The linear adjustment rate: Figure 14 shows the variation in the output voltage under different load currents when the input voltage changes from 2.5 V to 3.3 V. It can be observed that the best and worst adjustment efficiencies occur under light and heavy load currents, respectively. This is due to the negative correlation between the output resistance and the load current, leading to a low loop gain under light loads and a high loop gain under heavy loads.

(2)

The load adjustment rate is illustrated in Figure 15, which depicts the output voltage variation under different input voltages as the load current changes linearly from 100 μA to 1 mA. The simulation details the output voltage behavior across input voltages ranging from 2.5 V to 3.3 V in 0.1 V increments.

4.1.2. AC Characteristics

Figure 16 shows plots of the frequency response of the LTE-LDO under different load currents. This figure verifies that the fast substrate loop adopted in this paper plays a role in improving the loop bandwidth. In addition, a phase margin above 50° can be achieved in the full-load range, which ensures the fast-transient-response characteristics and loop stability of the LTE-LDO.

Figure 17 shows the PSR simulation results at different current loads from 1 Hz to 100 MHz. According to the figure, under load current conditions of 100 μA, 25 mA, 50 mA, 75 mA, and 100 mA, the PSR results at a low frequency are −71.70 dB, −70.01 dB, −67.78 dB, −65.44 dB, and −63.17 dB, respectively, while the noise suppression ability is gradually weakened at a high frequency.

4.1.3. Transient Characteristics

To provide a clearer comparison of the transient characteristics with and without the substrate-driven loop, Figure 18 illustrates the output voltage response for both structures during a 100 μA to 100 mA current transition within 100 ns. Under a 2.5 V input, a TT process, and 27 °C, the conventional structure exhibits an undershoot of 188 mV, an overshoot of 195 mV, and a recovery time of 70 ns, while the LTE-LDO achieves an undershoot of 130 mV and an overshoot of 190 mV and stabilizes in 40 ns. The highlighted recovery times of 40 ns versus 70 ns demonstrate a significant improvement in the transient response, which is critical for high-speed signal processing applications where faster stabilization reduces data errors and enhances the signal integrity. In power management systems, this reduction in the recovery time enables more stable voltage regulation during rapid load transients, improving the efficiency and reliability for modern processors and FPGAs that require quick current transitions.

In order to systematically compare the parameter indexes of the proposed LDO with those of previous traditional structures, this section gives a detailed performance comparison, which is shown in the following table. In order to compare the performance more intuitively, a calculation formula is used for the LDO quality factors FoM1 and FoM2.

The proposed LTE-LDO has a strong load capacity by driving a load capacitor of 100 pF and a load current of 100 mA at a static current consumption of only 37 μA, demonstrating its low-power-consumption characteristics. The LTE-LDO shows a greatly improved transient response while consuming a low quiescent current. In addition, the FoM2 value of this structure is the smallest, which verifies that the LTE-LDO can achieve an excellent comprehensive performance.

Through a comparison with all of the literature, it is found that the structure with the substrate loop can improve the trade-off between the power consumption and load current compared with that in the traditional structure without a substrate driver; effectively improve the maximum load current and reduce the loop response time; and significantly enhance the transient characteristics of the traditional structure.

Table 1. Comparison of performance parameters.

Parameter	[24]	[25]	[26]	[27]	[28]	[29]	[30]	This Work
Year	2018	2019	2021	2021	2022	2023	2024	2025
Size of process (μm)	0.13	0.13	0.18	0.18	0.18	0.18	0.18	0.18
Power tube	PMOS	PMOS	PMOS	PMOS	PMOS	PMOS	PMOS	PMOS
Dropout voltage (mV)	200	200	160	200	200	100	200	200
Quiescent current (μA)	3.2–208	4	26	10–50.25	24.2	0.22–660	0.054	37
Maximum load capacitance (pF)	50	125	100	100	100	300	0.4	100
Load current (mA)	1–25	0.1–3.1	0–50	0.1–100	10	0.01–30	10	0.1–100
Linear adjustment rate (mV/V)	0.308	29	37.14	0.75	-	0.45	11.7	2.94
Load adjustment rate (μV/mA)	124	1200	0.64	480	670	0.35	-	8.38
Output voltage variation (mV)	112	210	245	296	271.3	215	600	320
Edge time (ns)	100	200	300	500	100	100	15	100
Current efficiency (%)	99.92	99.80	99.95	99.95	99.76	97.8	-	99.96
FOM2 (μV)	663.0	775.38	382.2	448.5	656.5	128.3	90	119.5

shows that the structure proposed in Reference [24] has a lower overshoot and undershoot, but it has a maximum load capacitance of only 50 pF and a maximum load current of just 25 mA. The structure proposed in Reference [25] achieves a static current of only 4 μA, but similarly, its maximum load current is very small, at just 3.1 mA, which cannot meet the requirements of electronic devices demanding large load currents. The structure proposed in Reference [26] demonstrates an improvement in the load current compared to the previous two references, but its line regulation is poor, reaching as high as 37.14 mV/V. The structure proposed in Reference [27] enhances the maximum load current further, but it suffers from a long edge time (500 ns) and poor load regulation (480 μV/mA). The structure proposed in Reference [28] has a limited load current range of only 10 mA and also exhibits poor load regulation at 670 μV/mA. Among these recent structures, none achieve an effective trade-off between the static power consumption and load current. In contrast, the LTE-LDO proposed in this paper effectively addresses this issue, driving a 100 pF load capacitance and a 100 mA load current while consuming only 37 μA of static current, demonstrating a strong load driving capability. The LTE-LDO significantly improves the transient response while maintaining a low static current consumption. Furthermore, the FoM2 value of this structure is the lowest, validating that the LTE-LDO achieves an outstanding comprehensive performance.

5. Conclusions

In this work, a novel design methodology for an on-chip capacitor-less LDO based on substrate technology has been proposed and successfully implemented using the SMIC 0.18 μm CMOS process. Comprehensive post-layout simulations were conducted to validate the design, confirming its feasibility. The proposed LTE-LDO effectively addresses the critical challenges of reducing the static power consumption and improving the load transient response. Through a systematic comparison between AB class and super AB class transconductance amplifiers, it was demonstrated that the super AB class amplifier significantly enhances the slew rate, DC gain, and output current, thereby overcoming the bandwidth limitations of traditional designs.

To optimize the transient performance further, a fast feedback path was integrated at the substrate end, enabling the rapid detection of small-signal disturbances and minimizing the loop response time. This work not only provides a qualitative explanation of the overall circuit’s operation but also presents complete analytical derivation of the transfer function, accounting for the interaction between the substrate loop and the main loop. Finally, a comparative analysis with state-of-the-art LDO designs confirms the superior performance of the proposed work in terms of the low static current consumption and high transient response.

This paper focuses on theoretical analysis and simulation but lacks chip fabrication and comprehensive experimental validation. Future research endeavors should focus on bridging the gap between a theoretical analysis and empirical validation through physical implementation of the LTE-LDO architecture. The fabrication and characterization of an actual chip would provide critical insights into performance discrepancies between the simulation results and measured data, thereby enhancing the scientific rigor of the findings.