Design and Evaluation of Radiation-Tolerant 2:1 CMOS Multiplexers in 32 nm Technology Node: Transistor-Level Mitigation Strategies and Performance Trade-Offs
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThis paper explores the radiation - hardening design of 2:1 CMOS multiplexers in 32nm technology, using circuit - level mitigation methods and analyzing performance trade - offs. But the study of radiation - hardening falls short in some aspects, undermining the paper's completeness and persuasiveness. A major revision is recommended. The revision suggestions are as follows:
- The paper doesn't specify the targeted radiation particles (gamma rays, protons, neutrons, etc.). Different particles cause damage via different mechanisms. For instance, gamma rays ionize through photoelectric effects and Compton scattering, while protons and neutrons cause radiation effects via direct and indirect ionization. Without specifying particle types, readers can't accurately grasp the circuit's anti - radiation application scenarios.
- The specific irradiation dosage isn't mentioned. As a key parameter for evaluating anti - radiation performance, it significantly impacts the circuit's response and damage level. Omitting this info prevents a comprehensive assessment of the circuit's effectiveness and reliability in real - world radiation environments.
- It's unclear whether the anti - radiation performance is obtained via simulation or actual testing. If it's simulated, the tools, models, and assumptions should be detailed. If it's tested, the equipment, environment, and methods must be specified. Also, the paper doesn't mention in - situ measurement post - irradiation and annealing, which are crucial for assessing anti - radiation performance.
- The background section is overly lengthy and convoluted. Please distill the key scientific issues and highlight the innovations of this work.
Author Response
Detailed Response to Reviewers
Dear Editor and Reviewers,
Thank you for reviewing our submission. We sincerely appreciate your comments and constructive feedback on our manuscript. To facilitate clarity in our response, we have organized this letter into sections addressed to each reviewer, following the order of comments as presented in the decision e-mail. Within each section, we reproduce the original content the editorial staff provided, with our responses highlighted in blue for easy reference. Once again, we are grateful for your valuable input and insights, which have undoubtedly enhanced the quality of our manuscript.
Reviewer 1
This paper explores the radiation - hardening design of 2:1 CMOS multiplexers in 32nm technology, using circuit - level mitigation methods and analyzing performance trade - offs. But the study of radiation - hardening falls short in some aspects, undermining the paper's completeness and persuasiveness. A major revision is recommended. The revision suggestions are as follows:
R1.Q1. The paper doesn't specify the targeted radiation particles (gamma rays, protons, neutrons, etc.). Different particles cause damage via different mechanisms. For instance, gamma rays ionize through photoelectric effects and Compton scattering, while protons and neutrons cause radiation effects via direct and indirect ionization. Without specifying particle types, readers can't accurately grasp the circuit's anti - radiation application scenarios.
R1.A1. We appreciate your comment regarding the specification of the targeted radiation particles in our study. We would like to clarify that our work is conducted at the electrical level, considering that various radiation particles — such as gamma rays, protons, and neutrons— can interact with integrated circuits through different ionization mechanisms. We acknowledge that factors, including particle type, angle of incidence, and other parameters, influence the energy deposited in the material.
However, our approach focuses on the energy deposited in the device, independent of the specific particle involved. For example, different interactions may result in an energy deposition of approximately 5 MeV within the circuit [1]. Based on this representative energy value, we perform electrical simulations following established methodologies in the literature that employ TCAD tools to model radiation effects and evaluate circuit response [2] [3] [4]. We improve this discussion on the new version of the manuscript.
By abstracting the analysis to a generic scenario in which any particle may cause this energy deposition, we define our protection parameters without the need to detail every possible particle type and interaction mechanism. This methodological choice effectively avoids the complexity and high computational cost associated with extensive simulations, such as Monte Carlo analyses, while maintaining a focus on the circuit’s electrical response under representative radiation conditions. We believe this approach provides a practical and rigorous framework for assessing radiation hardness without compromising the generality of the results.
[1] KANNAUJIYA, Aryan; SHAH, Ambika Prasad. Radiation Effects in VLSI Circuits–Part I: Historical Perspective. IETE Technical Review, v. 41, n. 6, p. 716-735, 2024.
[2] SCHVITTZ, R. B. et al. Comparing analytical and monte-carlo-based simulation methods for logic gates set sensitivity evaluation. Microelectronics Reliability, v. 114, p. 113871, 2020.
[3] WROBEL, Frédéric; SAIGNÉ, Frédéric. MC-ORACLE: A tool for predicting soft error rate. Computer Physics Communications, v. 182, n. 2, p. 317-321, 2011.
[4] Aguiar, Y.Q.; Wrobel, F.; Autran, J.-L.; Leroux, P.; Saigné, F.; Pouget, V.; Touboul, A.D. Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions. Aerospace 2020, 7, 12. https://doi.org/10.3390/aerospace7020012
R1.Q2. The specific irradiation dosage isn't mentioned. As a key parameter for evaluating anti - radiation performance, it significantly impacts the circuit's response and damage level. Omitting this info prevents a comprehensive assessment of the circuit's effectiveness and reliability in real - world radiation environments.
R1.A2. Thank you for the comment. It is important to emphasize that our focus lies on analyzing the energy deposited within the integrated circuit. While radiation dose is indeed a relevant parameter for characterizing real-world environments, its precise determination depends on multiple factors, including the particle spectrum and fluence, which can vary considerably depending on the application scenario. Accordingly, we have adopted an approach that abstracts the dose in terms of deposited energy, enabling a direct evaluation of the circuit’s electrical response under a representative ionization condition. We acknowledge that this approach considers a worst-case scenario evaluation, but it allows for a targeted analysis of electrical effects without the need to detail all environmental and statistical variables associated with dose. Therefore, although the dose was not explicitly specified, we believe that the chosen approach provides a robust assessment of the circuit’s radiation hardness, ensuring practical applicability across diverse environments without compromising the technical rigor of the study.
R1.Q3. It's unclear whether the anti - radiation performance is obtained via simulation or actual testing. If it's simulated, the tools, models, and assumptions should be detailed. If it's tested, the equipment, environment, and methods must be specified. Also, the paper doesn't mention in - situ measurement post - irradiation and annealing, which are crucial for assessing anti - radiation performance.
R1.A3. Thank you for the comment. We included a new figure - Figure 6 - to better illustrate the simulation scenario. We also improved the discussion about the necessary configuration setup to run the simulation in our methodology section. These new modifications improved our methodology description and analysis focus.
R1.Q4. The background section is overly lengthy and convoluted. Please distill the key scientific issues and highlight the innovations of this work.
R1.A4. Thank you for the suggestion. We have improved the background section, removing the concepts that are well known in the literature and giving more focus to the innovation of our work.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for AuthorsThe manuscript presents design and evaluation of radiation-tolerant 2:1 CMOS multiplexers in 32nm: transistor-level mitigation strategies and performance trade-offs.
[1] Please fix the following phrase on page 2.
"While prior research has extensively evaluated multiplexer designs for power and delay characteristics [CITAR]"
[2] For comparison with other designs, performance numbers should be used instead of simple Yes or No. Authors need to evaluate the power, delay, and area under normal operation. Then, SEE sensitivity/response can be added for irradiated conditions.
[3] Detailed information of SEE simulation set for complex circuits should be clarified with justification of fair comparison among circuits.
[4] Selection of 5 MeV is somewhat arbitrary. Proper generalization is required.
[5] The caption of Figure 3 has a typo.
[6] In Fig. 2 (b), "Q-1" is not a standard notation and should be fixed.
[7] Applications of SEE hardened design to a simple logic gate are not useful enough in practical digital circuit implementation. Radiation-hardening idea needs to be investigated in a functional block or system level.
Author Response
Detailed Response to Reviewers
Dear Editor and Reviewers,
Thank you for reviewing our submission. We sincerely appreciate your comments and constructive feedback on our manuscript. To facilitate clarity in our response, we have organized this letter into sections addressed to each reviewer, following the order of comments as presented in the decision e-mail. Within each section, we reproduce the original content the editorial staff provided, with our responses highlighted in blue for easy reference. Once again, we are grateful for your valuable input and insights, which have undoubtedly enhanced the quality of our manuscript.
Reviewer 2:
The manuscript presents design and evaluation of radiation-tolerant 2:1 CMOS multiplexers in 32nm: transistor-level mitigation strategies and performance trade-offs.
R2.Q1. Please fix the following phrase on page 2.
"While prior research has extensively evaluated multiplexer designs for power and delay characteristics [CITAR]"
R2.A1. Thank you for pointing this out. We made the correction.
R2.Q2. For comparison with other designs, performance numbers should be used instead of simple Yes or No. Authors need to evaluate the power, delay, and area under normal operation. Then, SEE sensitivity/response can be added for irradiated conditions.
R2.A2. We appreciate your comment and we have tried to provide a fair comparison with related work. However, the related work report data obtained for different technological nodes and evaluation conditions, for example, different supply voltages and fault mechanisms. These factors avoid a direct comparison with the related work. Because of that, we adopted a qualitative and methodological comparison. About the power, delay and area under nominal operation the results are presented together with the mitigation approaches. All results labelled as MUX in Tables 3-4 and Figures 15-17 are the nominal results without mitigation approaches. We improved the description of these results in the new version of the manuscript.
R2.Q3. Detailed information of SEE simulation set for complex circuits should be clarified with justification of fair comparison among circuits.
R2.A3. Thank you for your question. However, we would like to clarify the definition of "complex circuits" as intended in your comment. If "complex circuits" refers to larger circuits composed of sub-blocks (such as the 2:1 MUX or other elementary gates), our methodology remains applicable. In such cases, the analysis can be hierarchically extended: by first optimizing the basic block (as presented in our study), any improvements in radiation tolerance and performance at the gate or module level will propagate to higher abstraction levels, bringing overall benefits to the more complex system.
If the intention was to address circuits of higher complexity in terms of logic depth, size, or function, we note that the same SET simulation methodology can be employed, although with increased computational effort and complexity of analysis. In either case, our comparison among circuits is based on a consistent methodology: all designs and mitigation techniques are evaluated under the same conditions (e.g., same input vector set, identical particle injection methodology), ensuring a fair and meaningful comparison.
We would appreciate further clarification if a different meaning of "complex circuits" was intended, so we can address your concern in more detail.
R2.Q4. Selection of 5 MeV is somewhat arbitrary. Proper generalization is required.
R2.A4. We defined the 5 MeV based on the intensity of some of the most common radiation causing elements reported by [1] and reproduced in the Table below. We considered that different interactions may result in an energy deposition of approximately 5 MeV within the circuit and opted to adopt a moderate but significant intensity for the evaluation. We have improved this discussion on the new version of the manuscript.
Based on this representative energy value, we perform electrical simulations following established methodologies in the literature that employ TCAD tools to model radiation effects and evaluate circuit response [2] [3] [4].
By abstracting the analysis to a generic scenario in which any particle may cause this energy deposition, we define our protection parameters without the need to detail every possible particle type and interaction mechanism. This methodological choice effectively avoids the complexity and high computational cost associated with extensive simulations, such as Monte Carlo analyses, while maintaining a focus on the circuit’s electrical response under representative radiation conditions. We believe this approach provides a practical and rigorous framework for assessing radiation hardness without compromising the generality of the results.
[1] KANNAUJIYA, Aryan; SHAH, Ambika Prasad. Radiation Effects in VLSI Circuits–Part I: Historical Perspective. IETE Technical Review, v. 41, n. 6, p. 716-735, 2024.
[2] SCHVITTZ, R. B. et al. Comparing analytical and monte-carlo-based simulation methods for logic gates set sensitivity evaluation. Microelectronics Reliability, v. 114, p. 113871, 2020.
[3] WROBEL, Frédéric; SAIGNÉ, Frédéric. MC-ORACLE: A tool for predicting soft error rate. Computer Physics Communications, v. 182, n. 2, p. 317-321, 2011.
[4] Aguiar, Y.Q.; Wrobel, F.; Autran, J.-L.; Leroux, P.; Saigné, F.; Pouget, V.; Touboul, A.D. Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions. Aerospace 2020, 7, 12. https://doi.org/10.3390/aerospace7020012
R2.Q5. The caption of Figure 3 has a typo.
R2.A5. Thank you for pointing this out. We made the correction.
R2.Q6. In Fig. 2 (b), "Q-1" is not a standard notation and should be fixed.
R2.A6. Thank you for pointing this out. We made the correction.
R2.Q7. Applications of SEE hardened design to a simple logic gate are not useful enough in practical digital circuit implementation. Radiation-hardening idea needs to be investigated in a functional block or system level.
R2.A7. We appreciate the comment. We agree that the analysis of a single logic gate may seem to have limited impact on more complex circuits. However, our approach is based on the fact that ASIC designs commonly employ standard cell libraries, where basic logic gates serve as fundamental building blocks for constructing larger circuits. Therefore, by enhancing the robustness of these elementary blocks, an increase in radiation tolerance is expected at higher abstraction levels. In this way, we address an early stage of the design process, which yields cascading benefits throughout subsequent phases of circuit development.
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsThe paper presents the design and evaluation of radiation-tolerant CMOS multiplexers in 32 nm, based on the previous work published in LASCAS 2025 proceedings. The conclusion is useful for radiation-harden circuit design. The main comments are listed as follows.
- The paper presents several versions of multiplexers, as shown in Fig.6. However, the difference between them is mentioned. It it not easy for reader to understand. The related sentences are hoped to be added.
- Trade-off is mentioned in title. Each simulated performance is presented Section 4. Maybe the design method about the trade-off is not given. How to choose the optimized version, according to the design requirements?
- This work is the expanded version of a paper published in LASCAS 2025 proceedings. What’s the contribution of this paper? The content cannot be almost same, because these are two papers. It is suggested that the content mentioned in previous paper is hoped to be deleted. The length of this paper maybe too long.
- Fig.2.b, Q should be inverse with X and Y.
- Fig.5. Why Y is inverse with D1, when D1 is selected?
- Fig.6. Too many circuits are given. However, the description about them is lacked. The working principle of radiation tolerance is hoped to be given.
- Fig.7. Where is bout, cout, n6? It is suggested to label them in the circuit.
- Table 1. I’m confused about the results. How to simulate the circuit to give a probability? Monte Carlo simulation? The technique mentioned is not clear to be understood. It is helpful to give one circuit example.
- I think Table 3 is useless, since little information is given.
Author Response
Detailed Response to Reviewers
Dear Editor and Reviewers,
Thank you for reviewing our submission. We sincerely appreciate your comments and constructive feedback on our manuscript. To facilitate clarity in our response, we have organized this letter into sections addressed to each reviewer, following the order of comments as presented in the decision e-mail. Within each section, we reproduce the original content the editorial staff provided, with our responses highlighted in blue for easy reference. Once again, we are grateful for your valuable input and insights, which have undoubtedly enhanced the quality of our manuscript.
Reviewer 3
The paper presents the design and evaluation of radiation-tolerant CMOS multiplexers in 32 nm, based on the previous work published in LASCAS 2025 proceedings. The conclusion is useful for radiation-harden circuit design. The main comments are listed as follows.
R3.Q1. The paper presents several versions of multiplexers, as shown in Fig.6. However, the difference between them is mentioned. It is not easy for the reader to understand. The related sentences are hoped to be added.
R3.A1. Thank you for the comment. We have revised the text to provide a clearer explanation of the primary differences between each multiplexer design.
R3.Q2. Trade-off is mentioned in the title. Each simulated performance is presented in Section 4. Maybe the design method about the trade-off is not given. How to choose the optimized version, according to the design requirements?
R3.A2. We thank the reviewer for raising this important point. As the reviewer noticed, each simulated design’s performance metrics (area, delay, and radiation robustness) are presented in Section 4. To address the topic of trade-off more explicitly, we have now included a dedicated discussion in Section 5 that explores multiple scenarios and highlights the decision process involved in selecting the most suitable design and mitigation technique, depending on specific design requirements. Therefore, the trade-off between area, delay, power, and radiation tolerance is documented and discussed, allowing the designer to prioritize these criteria according to the requirements of the intended application. We believe the added discussion now clarifies how to select the optimal design for various scenarios.
R3.Q3. This work is the expanded version of a paper published in LASCAS 2025 proceedings. What’s the contribution of this paper? The content cannot be almost same, because these are two papers. It is suggested that the content mentioned in previous paper is hoped to be deleted. The length of this paper maybe too long.
R3.A3. We thank the reviewer for the comment. This work uses the values presented in the previous study to assist in the selection of the best designs, considering aspects of radiation tolerance. However, the analysis conducted here is substantially different. Our main contribution lies in a comprehensive analysis of the trade-offs between different applications of radiation fault mitigation techniques with respect to circuit area, power consumption, and delay. The designs analyzed were selected based on the best results presented in [1]. We chose the designs that demonstrated the greatest robustness to radiation effects. Subsequently, based on the literature, we applied radiation hardening methods to improve the behavior of these circuits under radiation scenarios. Finally, we analyzed all possible techniques and evaluated their impact on key metrics, including power consumption, delay, and area. Therefore, we emphasize these differences and highlight the main contribution of the current submission from the previous study.
[1] Ana Flávia D., R.; Bernardo B., S.; Cristina, M.; Adriano V., W.; Rafael B., S. Evaluation of Transient Fault Tolerance in Different Logic Styles of 2: 1 Multiplexers. In Proceedings of the 2025 IEEE 16th Latin America Symposium on Circuits and Systems (LASCAS), 2025, Vol. 1, pp. 1–5. https://doi.org/10.1109/LASCAS64004.2025.10966333.
R3.Q4. Fig.2.b, Q should be inverse with X and Y.
R3.A4. Thank you for pointing this out. We corrected this issue.
R3.Q5. Fig.5. Why Y is inverse with D1, when D1 is selected?
R3.A5. Thank you for pointing this out. You are correct. We fixed this issue.
R3.Q6. Fig.6. Too many circuits are given. However, the description about them is lacked. The working principle of radiation tolerance is hoped to be given.
R3.A6. Thank you for pointing this out. We improved the explanation about the designs.
R3.Q7. Fig.7. Where is bout, cout, n6? It is suggested to label them in the circuit.
R3.A7. Thank you for pointing this out. We fixed this issue.
R3.Q8. Table 1. I’m confused about the results. How to simulate the circuit to give a probability? Monte Carlo simulation? The technique mentioned is not clear to be understood. It is helpful to give one circuit example.
R3.A8. Thank you for the comment. To clarify how the probability is determined, we evaluated the number of input vectors for each design and mitigation technique. Table 2 was updated to present the LETth values for all individual input vectors, and Table 3 was added to summarize key statistical parameters, such as minimum LETth, mean, and standard deviation. Furthermore, we expanded the text to include a detailed discussion on the calculation of this probability.
As an example, for design V4 using the X4+DC mitigation technique, 4 out of 8 input vectors exhibit LETth values above 5 MeV. Therefore, this configuration is robust for 4 out of 8 input scenarios, corresponding to 50%.
R3.Q9. I think Table 3 is useless, since little information is given.
R3.A9. We reorganize the text, bringing the Table 3 discussion on the related work section. We opt to keep this table to provide a visual and fast comparison with related work that emphasises the lack of multiplexers evaluation considering performance, power, area and reliability. We have also improved the discussion of the related work revision on the new version of the manuscript.
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsThis manuscript can be accepted.
Reviewer 2 Report
Comments and Suggestions for AuthorsThe manuscript has been revised carefully to address the reviewer's questions. I have no other technical comments.
Reviewer 3 Report
Comments and Suggestions for AuthorsThanks the authors' good revision.
