A Reduced-Order Small-Signal Model for Four-Switch Buck–Boost Under Soft-Switching Current Shaping Control Strategy

Abstract

The four-switch buck–boost (FSBB) converter, which possesses both step-up and step-down capabilities, is highly suitable for applications where input and output voltages have overlapping ranges. Correspondingly, the current shaping control (CSC) strategy is investigated for the FSBB converter, which shapes a quadrilateral inductor current waveform featuring the minimum RMS value to improve efficiency and power density. However, the small-signal model for the CSC algorithm has not yet been established, and the traditional and common modeling method requires considering multiple duty cycles and phase shifts of the FSBB converter, whose calculation is complex and inconvenient to use. For the special case of the CSC strategy using cycle-by-cycle current detection, an additional constraint of the averaged volt-second on the inductor can be regarded as zero, making the inductor current no longer a variable of the state-space, which eliminates the pole generated by the inductor and reduces the order of the small-signal model. Thus, this paper greatly simplifies the computation and design of the compensator by using the constraint condition mentioned above. This one-pole first-order model is simplified, maintains enough accuracy in the low-frequency domain, and can be corrected using only a simple PI controller. Finally, a prototype of the 300 W FSBB converter under the digital CSC algorithm was built to validate the precision and dynamic performance of the proposed first-order small-signal model.

1. Introduction

In applications such as intermediate bus converters of data centers, photovoltaic energy storage systems, and electric vehicles [1,2,3,4], non-isolated dc-dc converters are usually required to have the ability to step up and step down due to the wide variation of input and output voltages and the overlapping voltage range. The four-switch buck–boost (FSBB) circuit can not only meet the requirements for wide-range step-down and step-up but also features fewer passive components and high-frequency ZVS operation. As shown in Figure 1, the FSBB converter has four switches, Q₁, Q_2, Q₃, and Q₄, which form the leg of the input side and the leg of the output side. Among them, the MOSFET Q₁ and Q₂ on the input side are controlled by PWM1, whose control variable is defined as the duty cycle d₁. The MOSFET Q₃ and Q₄ on the output side are controlled by PWM2, whose control variable is defined as d₂. The phase shift between PWM1 and PWM2 is defined as Φ, which is the third control dimension for the converter. Since the control of the FSBB circuit has three degrees of freedom, making it more flexible and complex, many control strategies for the FSBB have been proposed to achieve high efficiency and high-frequency operations. These can generally be divided into traditional hard-switch control and soft-switch control.

The traditional multi-mode hard-switching control has buck mode, boost mode, and buck–boost mode [5,6]. Through the detection and comparison of input and output voltages, only the PWM1 of the input side leg is controlled, and the duty cycle of the output side leg (d₂) equals 1 when operating in the step-down mode. Similarly, when operating in the step-up mode, d₁ = 1, and only the PWM2 of the output side leg is controlled. When the input and output voltages are close, both the input and output side legs are controlled. This control strategy has a large peak-to-peak current value and high switching loss, especially when operating in buck–boost mode with twice the number of switch operations compared to buck or boost modes. In order to reduce the peak-to-peak and RMS values of the inductor current, papers [7,8] proposed a three-mode double-edge modulation strategy, which transformed the triangular inductor current wave into a quadrilateral waveform, thereby improving the efficiency. However, since the current is always continuous, the losses of the hard-switching limit the switching frequency and power density.

To address losses of the hard-switching and achieve high-frequency soft switching, reference [9] presented a strategy where the inductor current crosses zero, as shown in Figure 2a. The PWM1 and PWM2 satisfy d₁ = 1 − d₂. Thus, zero-voltage switching can be achieved during the dead time, which greatly reduces the switching loss in high-frequency operation. However, due to the large peak-to-peak and RMS values of the triangular current waveform, the conduction loss and turn-off loss increase.

As shown in Figure 2b,c, the strategies proposed in [10,11,12,13,14,15,16,17,18] make full use of the three control variables of the FSBB. Compared with the triangular wave in Figure 2a, the quadrilateral current waveform greatly reduces the peak-to-peak value and RMS value by introducing the phase shift Φ, thereby achieving precise control of the inductor current shape. To minimize the losses as much as possible, paper [11] established an optimal look-up table of {d₁, d₂, Φ} for various input voltages and load conditions through complex offline computation under the constraint of the minimum RMS value of the inductor current. However, when faced with wide variations in both input and output voltages, the data volume of the three-dimensional look-up table becomes excessively large, far exceeding the storage capacity of the MCU. Consequently, both analog and digital real-time computing methods have been proposed in [12,13,14,15,16,17,18]. These real-time CSC strategies not only reduce DSP resource consumption but also enable full-range soft-switching with high frequency and high efficiency. By the way, the concept of shaping the current can also be applied in isolation topology, such as dual half-bridge power converters in paper [19], which provides the algorithm and modeling method that allows the designer to obtain a linear input-to-state representation of the converter and to “cancel” the dominant nonlinearities.

In the past two years, more implementation methods of the CSC control strategy have been proposed, including both analog [16,17] and digital real-time computing [18] methods. However, their goal is to optimally adjust d₁, d₂, and the phase shift in order to maximize the proportion of the mode where G_Q1 and G_Q3 are turned on, as shown by the red line in Figure 2c. For the analog control in [16], the minimized RMS value of the inductor is realized by two coupled closed loops. The loop of the duty cycle for voltage regulation affects the loop of the phase-shift regulation, causing the compensator parameter designs to be difficult and potentially unstable. To solve these problems, paper [17] proposed an approximate phase-shift method to avoid the closed loop of the phase shift. However, the result of the approximate method tends to be larger than the theoretical value, resulting in an increase in the inductor current RMS value. On the other hand, through digital control methods [18], the flexible computing ability of digital processors avoids the approximate phase shift of the analog method. In order to solve the problem of variable frequency under heavy load in digital CSC control [14], method [18] increase the output current by increasing the phase shift and maintaining the constant frequency by reducing the time proportion of the mode where G_Q1 and G_Q3 are both turned on, shown as the red line in Figure 2c. Compared with the variable frequency method [14], the trapezoidal waveform gradually degenerates into a triangular waveform, resulting in larger RMS values and losses.

As digital control is flexible and programmable, the advantages of the simplified real-time digital algorithm [14] are reviewed and implemented for the intermediate bus converter (IBC) as a voltage pre-regulation converter in the data center. However, the digital CSC algorithm is usually divided into multiple segments and mainly controls the shape of the inductor current, which is different from the traditional PWM-duty control. Paper [14] only presents the control scheme but does not propose the relevant small-signal modeling method. Thus, CSC strategies bring challenges to the actual design of closed-loop compensators and stability analysis. The traditional small-signal modeling methods [20,21] of the FSBB converter consider the independent variations of three variables (d₁, d₂, Φ), and the boundary condition of the inductor current is free. Therefore, its small-signal model is more fundamental with two state-space variables, but the multiple variables bring complexity to the design, and there are two low-frequency poles owing to the inductor and output capacitor of the converter. For the CSC strategy [14] that uses a comparator to limit the boundary of the inductor current, the averaged volt-second on the inductor can be regarded as zero, making the inductor current no longer a variable of the state-space, meaning that the small-signal modeling processes can be simplified.

In this paper, an averaged switching model and a first-order small-signal model are developed with reduced complexity via systematic analysis. The digital high-frequency soft-switching CSC strategy [14] has constraint conditions on the inductor boundary. Due to the implementation of the comparator for current detection (CD), the moving average of the inductor voltage seems equal to zero or approximately zero [22], causing the inductor to lose its inertia. The controlled inductor current is no longer a free state-space variable and is directly determined by the controller. Thus, the digital CSC algorithm is similar to the current mode control. Approximately one pole of the small signal transfer function is eliminated, which greatly simplifies the design of the controller parameters and enhances the robustness and stability of the converter. Subsequently, a simple PI controller was designed based on the reduced-order small-signal model, and experimental comparisons validated the method presented in this paper.

2. Analysis of Four-Switch Buck–Boost Converter Under Digital High-Frequency Soft-Switching Current Shaping Control Strategy

2.1. A Brief Introduction to the Operation Mode and Simplified Real-Time Digital CSC Scheme of FSBB

In Section 2.1, first, the specific implementation method of the CSC algorithm is introduced. The output of the compensator (PI output) does not directly control the duty cycle as usual, but rather, the variable T₂ controls the inductor current. Thus, it is difficult to directly obtain the transfer function from T₂ to the inductor current because T₂ affects d₁ and d₂ simultaneously. However, based on the current detection by the comparator, the approximated constraint condition is introduced to simplify the transfer function from T₂ to the inductor current. Finally, the first-order small-signal model can be derived by using the general perturbation and linearization method.

In order to analyze and derive the small-signal model, a brief introduction to the simplified real-time digital CSC strategy of FSBB is provided here. Whether it is the step-up mode or the step-down mode, shown in Figure 3, the quadrilateral inductor current control scheme referred to as CSC control is usually composed of four segments called T₁, T₂, T₃, and T₄ in a cycle, which are given by the CSC algorithm. However, to shape the current of the inductor into four segments, the variables T₁–T₄ need to be converted into the corresponding duty cycle d₁, d₂, and phase shift Φ of the legs, which are the variables used for PWM modulation. Equation (1) can be used to determine the phase shift Φ between the input leg and output leg, and Equations (2) and (3) determine the duty cycle d₁ and d₂ of the switch legs. Additionally, Equation (4) determines the T₄ value required at a constant frequency. Thus, the control variables d₁, d₂, and phase shift $\mathsf{\Phi }$ of the FSBB circuit legs can be transformed through the modulation relationship corresponding to Equations (1)–(4). Ts is the period of the fixed frequency.

$$T_1={\displaystyle \frac{\Phi }{2\pi }}\ast T_s$$

(1)

$$T_2=d_1\ast T_s-{\displaystyle \frac{\Phi }{2\pi }}\ast T_s$$

(2)

$$T_3=\left(d_2-d_1\right)\ast T_s+{\displaystyle \frac{\Phi }{2\pi }}\ast T_s$$

(3)

$$T_4=T_s-\left(T_1+T_2+T_3\right)$$

(4)

$$\left|I_{ZVS}\right|\ge {\displaystyle \frac{2C_{oss}\ast \mathit{max}\left(V_{in},V_{out}\right)}{t_d}}$$

(5)

The corresponding operation modes of the four segments T₁–T₄ are shown in Figure 4. Among them, T₁ corresponds to mode (a), where Q₁, Q₄ are turned on and Q₂, Q₃ are turned off; T₂ corresponds to mode (c), where Q₁, Q₃ are turned on, and Q₂, Q₄ are turned off; T₃ corresponds to mode (e), where Q₂, Q₃ are turned on and Q₁, Q₄ are turned off; and T₄ corresponds to mode (g), where Q₂, Q₄ are turned on and Q₁, Q₃ are turned off. Thus, these four modes shape the inductor current into a quadrilateral current waveform. Among T₁, T₂, T₃, and T₄ are four dead zones, t_dead1–t_dead4 of the switching leg’s PWM, as shown in Figure 3, and the corresponding operation modes for those four dead zones are shown in Figure 4b,d,f,h. For instance, as shown in Figure 4b, the inductor current charges the output capacitor C_oss of Q₄ and discharges the C_oss of Q₃, ensuring the ZVS turn-on of Q₃ in the dead zone. Figure 4d,f,h illustrate the same principle. The minimum inductor current needed for fully ZVS-on is defined as the parameter I_ZVS expressed in Equation (5) (assuming Q₁–Q₄ are the same MOSFET). $I_1,{ I}_2\ge I_{ZVS}$, and the negative inductor current is set to −I_zvs.

The digital CSC strategy and proof of the minimum RMS value of inductor current control have been presented in Reference [14]. In conclusion, as shown in Figure 3, to realize the minimum volt-second of the inductor, the proportion of T₂ in the whole cycle should be as large as possible to reduce the peak and RMS values of the inductor under the constraints of the given operating conditions. As shown in Figure 5, when V_in > V_out, the constraint condition for the minimum RMS of the inductor current can be simplified as I₁ = I_zvs, and T₂ is the only control variable for closed-loop regulation, which is determined by the PI controller. Thus, the MCU just calculates T₁ using (6). The end of T₃ can be detected by the comparator. When V_in < V_out, the only difference is that I₂ = I_zvs, which means the value of T₃ is given by Equation (7). Therefore, it is sufficient to calculate T₁ in advance using the volt-second balance of the inductor, as expressed in Equation (8). In conclusion, there is only one control variable (T₂) in the digital high-frequency soft-switching CSC strategy, which brings great convenience for small-signal modeling and closed-loop system design.

$$T_1={\displaystyle \frac{2I_{ZVS}·L}{V_{in}}}$$

(6)

$$T_3={\displaystyle \frac{2I_{ZVS}·L}{V_{out}}}$$

(7)

$$T_1=\left({\displaystyle \frac{V_{out}}{V_{in}}}-1\right)T_2+{\displaystyle \frac{2I_{ZVS}L}{V_{in}}}\left(V_{in}<V_{out}\right)$$

(8)

The whole closed-loop system of the FSBB converter under the digital high-frequency soft-switching CSC strategy is presented in Figure 6. The digital controller samples the input and output voltages through the ADC and determines whether the step-up algorithm or the step-down algorithm should be used to calculate T₁ in real time. At the same time, according to the error between the output voltage V_out and the reference value V_ref, the control variable Tu is given by the PI, which is the only control variable used in the simplified digital high-frequency soft-switching CSC strategy FSBB circuit. Then, the control parameter T₁ obtained by the simplified algorithm and T₂ = Tu will be transformed into d₁, d₂, and the phase shift $\mathsf{\Phi }$ by the modulation part, which is used to drive the switches of the FSBB circuit.

In order to reset the inductor current cycle by cycle, as shown in Figure 7, the resistor R_s converts the current of Q₂ into a voltage signal V_RS, which contains the monitoring points of the inductor current. Then, V_RS is passed to the input of the comparator together with the reference current I_zvs to determine the end time of T₃. When V_RS reaches the value I_zvs during T₃, as shown in Figure 7, the comparator output signal CD will be pulled down. However, the switching transitions induce oscillations and overshoots that could affect the detection. As a result, the comparator usually generates multiple wrong falling edges caused by switching transitions. Thus, the drive signals $PWM1$ and $\overline{PWM2}$ are used to shield against wrong edges. As shown in Figure 7, since $PWM1$ and $\overline{PWM2}$ are both 1 (high level), except at T₃, and both 0 (low level) at T₃, the falling edge of the CD signal at T₃ can be extracted by the OR operation with $PWM1 \mathrm{a}\mathrm{n}\mathrm{d} \overline{PWM2}$. In actual implementation, the falling edge of $PWM1$ will also be appropriately delayed to shield switching transitions at the end of T₂. In conclusion, all the switching transition moments have been shielded by OR operation with $PWM1 \mathrm{a}\mathrm{n}\mathrm{d} \overline{PWM2}$. During T₃, there is no switching operation until the CD is pulled low, and the processed signal $T_{3end}$ can be obtained using a three-input OR gate, expressed as the Boolean equation $T_{3end}=PWM1+\overline{PWM2}+CD$.

2.2. The Proposed Averaged Switch Network and Linearized Reduced-Order Small-Signal Model

Since the use of a comparator to detect the inductor current under the digital high-frequency soft-switching CSC strategy, the inductor current does not have a free boundary, unlike other controls without current detection. As shown in Figure 8, the moving average of the inductor voltage seems to be equal to zero or approximately zero since Equation (9) always holds true. The current detection resets the boundary of the inductor current cycle by cycle, and $\widehat{i_L}$ does not behave as a state-space variable anymore. Then, the state-space equation of the inductor current is transformed into a constraint Equation (9). Thus, the small-signal model of the FSBB converter under the digital high-frequency soft-switching CSC strategy can reduce the order for the convenience of the closed-loop design. There is only one state-space variable remaining, which is the voltage of the output capacitor C_o. The averaged switch network of the FSBB converter is shown in Figure 8. Each switch network can be represented by a dependent voltage source and a current source using three-terminal switching network models.

$$L{\displaystyle \frac{d\widehat{i_L}}{dt}}=d_1\ast \widehat{v_{in}}+\widehat{d_1}\ast V_{in}-\widehat{d_2}\ast V_o-d_2\ast \widehat{v_o}=0$$

(9)

As shown in Figure 9a,b, the averaged inductor current${ ⟨i_L⟩}_{Ts}$ is controlled by T₂, which is no longer a state-space variable but is directly obtained from the algorithm of the constraint function in Equations (6)–(8). The control variable is incremental $∆T_2$, given by the PI controller, and will directly influence the moving averaged value of the output current${ ⟨i_o⟩}_{Ts}$, which is represented by the shadow area.

$i_L\left(t\right)$ is the inductor current of one switching period shown in Equation (10). Hence, it is a piecewise function, which can be obtained directly from Figure 3.

$$i_L\left(t\right)=\left\{\begin{array}{c}\begin{array}{c}{I}_{zvs}+{\displaystyle \frac{V_{in}}{L}}t, 0\le t\le T_1 \\ i_L\left(T_1\right)+{\displaystyle \frac{V_{in}-V_o}{L}}\left(t-T_1\right), T_1<t\le T_1+T_2 \end{array}\\ i_L\left({T_1+T}_2\right)+{\displaystyle \frac{-V_o}{L}}\left(t-T_1-T_2\right), { T}_1+T_2<t\le T_1+T_2+T_3\\ I_{zvs}, { T}_1+T_2+T_3<t\le T_s\end{array}\right.$$

(10)

Thus, the output side current source in the averaged switch model of Figure 8, ${⟨i_o⟩}_{Ts}$, which could be expressed as (11) by integrating function (10), which is the current of Q₃ shown in Figure 9c. Similarly, the input side current source in the averaged switch model of Figure 8, ${⟨i_{in}⟩}_{Ts}$, is expressed as (12).

$${⟨i_o⟩}_{Ts}={\displaystyle \frac{1}{T_s}}{\int }_{T_1}^{T_1+T_2+T_3}{i}_L\left(t\right)dt=g\left(T_2,V_{in},V_o\right)={\displaystyle \frac{I_{zvs}{T}_2{V}_{in}}{T_s{V}_o}}+{\displaystyle \frac{T_2^2{V}_{in}}{2L{T}_s}}-{\displaystyle \frac{T_2^2{V}_{in}^2}{2L{T}_s{V}_o}}$$

(11)

$${⟨i_{in}⟩}_{Ts}={\displaystyle \frac{1}{T_s}}{\int }_0^{T_1+T_2}{i}_L\left(t\right)dt=f\left(T_2,V_{in},V_o\right)$$

(12)

Equations (11) and (12) are the nonlinear large-signal model, which determine the DC Equations (13) and (14). Equations (15)–(19) are the general perturbation equations for small-signal linearization, where the average value is represented by the DC value and the small-signal perturbation. According to the small-signal approximation method ($\widehat{x}\ll X)$, the coefficient needed for the output-side equivalent small-signal circuits is shown in (21) by substituting (15)–(19) into (11) and ignoring the higher-order small quantities in the result. The partial derivatives method is more convenient.

$$I_{in}=f\left(T_2,V_{in},V_o\right)$$

(13)

$$I_o=g\left(T_2,V_{in},V_o\right)$$

(14)

$${⟨v_{in}⟩}_{Ts}=V_{in}+\widehat{v_{in}}$$

(15)

$${⟨v_o⟩}_{Ts}=V_o+\widehat{v_o}$$

(16)

$${⟨T_2⟩}_{Ts}=T_2+\widehat{T_2}$$

(17)

$${⟨i_{in}⟩}_{Ts}=I_{in}+\widehat{i_{in}}$$

(18)

$${⟨i_o⟩}_{Ts}=I_o+\widehat{i_o}$$

(19)

$$\widehat{i_{in}}={\displaystyle \frac{\partial f\left(T_2,V_{in},V_o\right)}{\partial T_2}}\widehat{T_2}+{\displaystyle \frac{\partial f\left(T_2,V_{in},V_o\right)}{\partial V_{in}}}\widehat{v_{in}}+{\displaystyle \frac{\partial f\left(T_2,V_{in},V_o\right)}{\partial V_o}}\widehat{v_o}=k_{i{T}_2}\widehat{T_2}+{\displaystyle \frac{-1}{r_i}}\widehat{v_{in}}+k_{ivo}\widehat{v_o}$$

(20)

$$\begin{gathered} \widehat{i_o}={\displaystyle \frac{\partial g\left(T_2,V_{in},V_o\right)}{\partial T_2}}\widehat{T_2}+{\displaystyle \frac{\partial g\left(T_2,V_{in},V_o\right)}{\partial V_{in}}}\widehat{v_{in}}+{\displaystyle \frac{\partial g\left(T_2,V_{in},V_o\right)}{\partial V_o}}\widehat{v_o}=k_{o{T}_2}\widehat{T_2}+k_{o{v}_{in}}\widehat{v_{in}}+{\displaystyle \frac{1}{r_o}}\widehat{v_o}= \\ {\displaystyle \frac{V_{in}\left(I_{zvs}L-T_2{V}_o+T_2{V}_{in}\right)}{T_s{V}_{o}L}}\ast \widehat{T_2}+{\displaystyle \frac{T_2\left(2I_{zvs}L-T_2{V}_o+2T_2{V}_{in}\right)}{2T_s{V}_{o}L}}\ast \widehat{v_{in}}-{\displaystyle \frac{V_{in}{T}_2\left(2I_{zvs}L+T_2{V}_{in}\right)}{{2T}_s{V}_o^{2}L}}\ast \widehat{v_o} \end{gathered}$$

(21)

With the simplified formulas (20) and (21), it is very easy to obtain the equivalent circuit diagram of the FSBB circuit under digital high-frequency soft-switching CSC strategy for small ac signals, as shown in Figure 10a. Among them, the input side independent source of the averaged switch network model, after being approximated by small signals, is composed of three parts: the input impedance defined as $r_i$, the controlled current source $k_{i{T}_2}\widehat{T_2}$, and the controlled current source $k_{ivo}\widehat{v_o}$. Similarly, the output side independent source of the averaged switch network model is composed of three parts: the output impedance defined as $r_o$, controlled current source $k_{o{T}_2}\widehat{T_2}$, and controlled current source $k_{o{v}_{in}}\widehat{v_{in}}$.

According to Figure 10a, the input of the converter is a constant voltage source V_in in most applications, meaning that $\widehat{v_{in}}=0$. In order to discuss the load transient stability and regulate the output voltage, only the output part of the small-signal model is needed to design the PI parameter. So, the whole closed-loop model is shown in Figure 10b. Briefly speaking, $H\left(s\right)$ is the sensor gain transfer function and is usually composed of a voltage divider with resistor R₁ = 100 kΩ, R₂ = 3.3 kΩ, and a filter capacitor C₁ = 8.8 nF, as expressed in Equation (22) and shown in Figure 11. Additionally, $PI\left(s\right)=k_p+{\displaystyle \frac{ki}{s}}$, where k_p and k_i are parameters of the proportional–integral controller.

$$H\left(s\right)={\displaystyle \frac{1}{1+\frac{R_1}{R_2}+R_1{C}_{1}s}}$$

(22)

According to Figure 10b, the controller directly controls the output current with T₂, and the FSBB converter under digital high-frequency soft-switching CSC control is modeled as a first-order system, whose single pole is owing to the only state-space component C_o = 180 uF. Thus, according to the equivalent circuit in Figure 10b, the transfer function from $T_2\left(s\right)$ to $v_o\left(s\right)$ is expressed as (24). The reduced-order method simplifies the output small-signal modeling for application.

$$R_e=r_o\left|\right|R_L\hspace{1em}\hspace{1em}{k}_{o{T}_2}={\displaystyle \frac{V_{in}\left(I_{zvs}L-T_2{V}_o+T_2{V}_{in}\right)}{T_s{V}_{o}L}}$$

(23)

$$G_{v_o{T}_2}\left(s\right)={\displaystyle \frac{v_o\left(s\right)}{T_2\left(s\right)}}={\displaystyle \frac{k_{o{T}_2}{R}_e}{R_e{C}_{o}s+1}}$$

(24)

Figure 12a,b show the calculation (lines) and simulation results (points) of the circuit transfer function $G_{v_o{T}_2}\left(s\right)$ at different operation points. As discussed before, the transfer function is related to the load condition R_e and the only state-space component C_o, which determines the pole of $G_{v_o{T}_2}.$ Because the first-order system only has one pole, the PI controller with one zero is enough to correct the control system. There is a moderate design that places the zero of the PI controller near the pole of the circuit to compensate for the phase drop at the pole.

In engineering practice, Reference [23] compares the differences of bode diagrams under the approximate methods and non-approximate methods. The assumption for reducing the order of the model is usually valid up to 1/10 of the switching frequency because the eliminated pole is close to the switching frequency and does not affect the bode diagrams in the low-frequency domain, as shown in Figure 12a,b.

2.3. The Closed-Loop Parameter Design Using Proposed Reduced-Order Small-Signal Model

In the previous section, the first-order small-signal model was proposed by eliminating the state-space equation of the inductor. The closed-loop block diagram and its equivalent ac small-signal model are shown in Figure 10b. In order to design the PI parameters, the loop gain of the system is defined as T_s(s), which is shown in (25).

$$T_s\left(s\right)=H\left(s\right)\ast PI\left(s\right)\ast G_{v_o{T}_2}\left(s\right)=\left({\displaystyle \frac{1}{1+\frac{R_1}{R_2}+R_1{C}_{1}s}}\right)\ast \left(k_p+{\displaystyle \frac{ki}{s}}\right)\ast {\displaystyle \frac{k_{iou}{R}_e}{R_e{C}_{o}s+1}}$$

(25)

The gain of T_s(s) and PI(s) is shown in Figure 13. The red and blue dotted lines are the transfer function of the circuit model $G_{v_o{T}_2}\left(s\right)$, the black dotted line represents the gain PI(s) of the PI controller, and the solid red and blue lines represent the loop-gain T_s(s) after compensation. Obviously, there is a pole in the circuit itself, and the gain at low frequency is relatively low. So, the zero ${(\omega }_{zero}={\displaystyle \frac{k_i}{k_p}})$ of the PI controller can be set near the pole of the system ${(\omega }_{pole}={\displaystyle \frac{1}{C_o\ast R_e}})$. After compensation, the loop gain function of the system is approximately a straight line with a slope of −20 dB/decade. Furthermore, the loop gain of the DC and low-frequency sections is significantly increased, reducing the static and low-frequency error of the system. Meanwhile, the loop gain can be adjusted by regulating the parameter k_p of the PI controller to control the cut-off frequency f_c. However, as shown in Figure 14, the transfer function H(s) of the voltage divider resistor and the first-order RC filter before ADC sampling introduce two additional poles (pole_(H(s)) = 6 kHz, pole_(filter) = 2.13 kHz) in the higher frequency range of the system, which will cause a phase drop of the system. Thus, to maintain a phase margin of 45° for this design, the maximum k_p can be 48, and the corresponding k_i can be 6 × 10⁴ under this condition.

3. Experimental Verifications

In order to verify the accuracy of the reduced-order small-signal model and the feasibility of the designed PI parameter, a Si-based 300 W four-switch buck–boost converter under digital high-frequency soft-switching current shaping control strategy is built for experiment. The proposed small-signal model loop-gain was measured using a network analyzer and compared with the theoretical curves. The key parameters of the converter are listed in

Table 1. Key parameters of the FSBB converter.

	Specifications
Input voltage	36–60 V
Output voltage	48 V
Output power	300 W
Switching frequency	800 kHz
Output capacitor Co	180 uF
Inductance	0.86 uH
Switches	4 × Si MOSFET CSD19532Q5B (100 V 5.6 m)
Driver	2 × UCC27210
Comparator	TLV3501
Inductor core	DMR51w
Controller	TMS320F28069
PI parameters	kp = 48, ki = 6 × 104

. Figure 15 shows the photos of the prototype, which mainly consists of two parts: Figure 15a shows the main power devices, such as the inductor and switches, and Figure 15b shows the digital controller used.

Figure 16 shows the step-down and step-up capabilities of the digital soft-switching CSC algorithm, and the soft-switching operation is also verified. As shown in Figure 16a, V_ds2 is the drain-to-source voltage of Q₂, V_gs2 is the gate-to-source voltage of Q₂, and i_L is the inductor current. Obviously, the turn-on of the Q₂ gate occurs after the V_ds2 drops to zero, as does the Figure 16b.

According to the digital CSC strategy, T₂ is the only closed-loop control variable for regulating the output voltage. Shown in Figure 17, (a) is the light load (I_o = 2 A) waveform of the inductor current, and (b) is the heavy load (I_o = 4 A) of the inductor current. T₁, T₂, T₃, and T₄ have been marked on the graph. By comparing the two waveforms, it is apparent that the closed-loop regulation of the converter is only adjusted by T₂, which is the direct output of the PI controller.

Figure 18 and Figure 19 are the bode diagrams of the loop gain function T_s(s) for the FSBB converter under the digital CSC strategy. They are used to verify the reduced-order small-signal model of the system under different load conditions (V_in = 48 V, V_o = 48 V). For instance, the red dotted line and solid line, respectively, represent the theoretically calculated gain and the measured gain of the network analyzer, and the blue dotted line and solid line, respectively, represent the theoretically calculated phase and the measured phase of the network analyzer. The measured results of the network analyzer are in good agreement with the calculation results of the proposed reduced-order small-signal model. Meanwhile, the measured results prove that the PI parameters designed in Section 2.3 ensure a phase margin of 30°, guaranteeing the stability of the circuit.

In Figure 20 and Figure 21, V_o is the output voltage, $∆t$ is the settling time of the load transient, and $∆V$ is the output voltage overshoot. When the small-signal model of the system is unknown, in engineering practice, the trial-and-error method and the empirical method are usually used to obtain a PI parameter [24]. The dynamic performance of the load transient using the PI parameters obtained by the trial-and-error method (k_p = 61, ki = 1.38 × 10⁶) is shown in Figure 20a and Figure 21a, where both usually exhibit larger overshoot and settling time. However, based on the reduced-order model and PI parameter designed in Section 2.3 (k_p = 48, ki = 6 × 10⁴), the FSBB converter shows smaller overshoot and shorter settling time in Figure 20b and Figure 21b compared to the traditional method.

In order to verify the robustness of the designed algorithm to V_in, the input voltage transient tests are conducted on the prototype. The input voltage switches from 42 V to 54 V within 1 ms with a 48 V output. Due to the quasi-symmetry shown in Figure 5, the switching mode of the CSC strategy, the large-signal averaged switch model, and the small-signal model are nearly the same, as shown in Figure 12. Figure 22 shows the inductor current waveforms during the input voltage transition period, and the converter is kept stable.

4. Conclusions

This paper proposed a reduced-order small-signal model based on the digital high-frequency soft-switching current-shaping control algorithm. However, different from the traditional continuous current control method, the digital CSC algorithm uses a comparator to reset the inductor current cycle by cycle, limiting the boundary of the inductor current. This control method converts the state-space variable of the inductor current into a constraint equation. Therefore, this current-mode control approximately shorts the inductor in the ac small-signal model. Through this small-signal modeling method, one pole in the original small-signal model is eliminated, which greatly simplifies the small-signal model and reduces the design complexity of the controller, facilitating engineering applications. This paper mainly analyzes the small-signal model and stability of the FSBB converter in the low-frequency domain, where the error of the averaging method could be small enough (MPPT application, IBC converter, and battery charging system). Additionally, the bandwidth of the converter has not yet exceeded the applicable range of the averaging method. Judging from the simulation analysis in Figure 12 and experimental results, the accuracy is sufficient to design the PI parameters. Finally, dynamic experiments compared with the conventional PI design have verified the accuracy of the model on a physical prototype.