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Volume 11
Issue 23
10.3390/electronics11234022
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Article

A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components

by
Kewei Wang
1,2,3,
Xinyi Zhang
1,2,3,
Bo Li
1,2,
Duoli Li
1,2,
Fazhan Zhao
1,2,
Jianhui Bu
1,2,* and
Zhengsheng Han
1,2,3,*
1
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2
Key Laboratory of Science and Technology on Silicon Device, Chinese Academy of Sciences, Beijing 100029, China
3
University of Chinese Academy of Sciences, Beijing 100029, China
*
Authors to whom correspondence should be addressed.
Electronics 2022, 11(23), 4022; https://doi.org/10.3390/electronics11234022
Submission received: 3 November 2022 / Revised: 1 December 2022 / Accepted: 2 December 2022 / Published: 4 December 2022
(This article belongs to the Section Microelectronics)
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Abstract

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results.
Keywords: FDSOI; compact model; SET; back-gate voltage FDSOI; compact model; SET; back-gate voltage

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MDPI and ACS Style

Wang, K.; Zhang, X.; Li, B.; Li, D.; Zhao, F.; Bu, J.; Han, Z. A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components. Electronics 2022, 11, 4022. https://doi.org/10.3390/electronics11234022

AMA Style

Wang K, Zhang X, Li B, Li D, Zhao F, Bu J, Han Z. A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components. Electronics. 2022; 11(23):4022. https://doi.org/10.3390/electronics11234022

Chicago/Turabian Style

Wang, Kewei, Xinyi Zhang, Bo Li, Duoli Li, Fazhan Zhao, Jianhui Bu, and Zhengsheng Han. 2022. "A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components" Electronics 11, no. 23: 4022. https://doi.org/10.3390/electronics11234022

APA Style

Wang, K., Zhang, X., Li, B., Li, D., Zhao, F., Bu, J., & Han, Z. (2022). A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components. Electronics, 11(23), 4022. https://doi.org/10.3390/electronics11234022

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