Design for the Package-Board Transition and Its Testability Design in the Fan-Out Wafer-Level Package

Abstract

A fan-out wafer level package (FOWLP) with double-sided four redistribution layers (RDLs) and the mega pillars connecting the front and back RDLs has been proposed for millimeter-wave applications. A well-matched package-board transition has been designed in this paper. The simulated insertion loss for the transition is about 0.82 dB at 79 GHz, and the simulated return loss is better than 10 dB from 72 GHz to 86 GHz. More importantly, two different measurement methods based on the port reduction technique and the Thru-Reflect-Line (TRL) calibration technique have been proposed to get the S parameters of the transition. Moreover, the feasibility of the two methods has been verified by simulation.

1. Introduction

Since being introduced by Infineon in 2001 [1], because of the advantages of better thermal and electrical performance, lower cost, and good feasibility, fan-out wafer-level package (FOWLP) technology has been widely used in millimeter-wave applications [2,3,4,5,6,7,8]. Thanks to the researchers, various types of FOWLP have emerged: Freescale proposed the redistributed chip package in 2007 [9], IME extended the technology to multi-die packaging in 2008 [10] and demonstrated the reliability of 3D FOWLP [11], a package-on-package concept with the FOWLP was proposed by STATS ChipPAC in 2012 [12], TSMC also developed their InFo wafer-level packaging [13,14] at basic of the FOWLP, and in 2014, the Infineon applied the through encapsulant via (TEV) in embedded wafer level ball grid array (eWLB) for vertical interconnection [15]. In addition, heterogeneous integration of four chips and four capacitors by the FOWLP method has been demonstrated [16].

FOWLP has attracted the interest of many scholars: extensive researches on warpage prediction [17,18,19,20], thermal performance [21,22] and electrical performance [23,24,25,26] have been carried out. Electrical performance is significant for millimeter-wave applications, such as the 77 GHz automotive radar and wireless communication systems. As the frequency increases, how to achieve the low loss radio frequency (RF) transition becomes a major challenge. For the Long Range Radar (LRR), due to the high gain requirement, the antennas are generally series fed rectangular microstrip patch arrays on the printed circuit board (PCB). According to the radar equation, the automotive radar will have a larger detection range if the antennas get more input power. Smaller interconnection losses mean more input power to the antennas. Therefore, a well-matched chip-package-board transition is needed for the LRR. It is the same for wireless communication systems [4]. In addition, it is not easy to test the antennas directly in FOWLP. The FOWLP samples are usually soldered on the PCB for the evaluation and characterization of the antennas [27]. For more accurate performance evaluation, the package-board transition should be de-embedded. Thus, it is important to get the S parameters of the package-board transition in FOWLP.

Currently, the transition for chip-package-board or package-board in FOWLP have been studied by many researchers, like in [4,5,24,25,26]. In [4], a channel from microstrip on the chip to microstrip on PCB was simulated, and the simulated loss is about 2 dB from 56 GHz to 70 GHz. In [5], at 77 GHz, a chip-package-board RF transition with the insertion loss of about 1 dB and return loss of about 20 dB was achieved in the eWLB package for the automotive radar transceiver. However, the measurement technique and results for the transition in FOWLP have been rarely reported. In [23], using the output power measured by the package and on-wafer, the insertion loss of the transition has been calculated. However, the specific transmission parameters have not been solved. It is a huge challenge to measure the package-board transition in FOWLP directly because the probe cannot be placed at the test ports on the test board and redistribution layers (RDL) at the same time.

Although few studies have reported the FOWLP transition measurement technique, many similar studies can be used for reference. [28] proposed a novel concept based on the Thru-Reflect-Line (TRL) calibration algorithm for the characterization of a single transition through the wafer. [29] demonstrated the feasibility of characterizing the singled–ended electronic packages using experimental S-parameters up to 30 GHz. TRL calibration and transmission line theory techniques were used here.

This study designed a good package-board transition in the FOWLP for the 77 GHz automotive radars. Within 76–81 GHz passband, the simulated insertion loss is less than 0.91 dB, and the return loss is better than 16 dB. More importantly, two different measurement methods based on the port reduction technique [30,31] and the TRL calibration technique [32,33] have been proposed to get the S parameters of the transition. Furthermore, we verified the feasibility of these two methods by simulation.

2. Structure and Process of the FOWLP

As shown in Figure 1, the FOWLP includes the four RDLs (M1, M2, M3, M4), four dielectric layers (PI1, PI2, PI3, PI4) (${\epsilon }_r$ = 3.08, tan$\delta$ = 0.02), epoxy molding compound (EMC) (${\epsilon }_r$ = 3.7, tan$\delta$ = 0.009, h = 200 $\mathsf{\mu }$m), mega pillars, silicon chip, and solder ball arrays. The mega pillars are developed for vertical interconnection. The RDLs have a minimum line width and line spacing of 10 $\mathsf{\mu }$m. The pitch of the solder balls is 450 $\mathsf{\mu }$m, and the diameter is 250 $\mathsf{\mu }$m.

The FOWLP used in this study follows the RDL-First process, as shown in Figure 2. Firstly, spin coating a laser release layer on the glass wafer. Then, front side RDLs and the dielectric layers are fabricated on the release layer. After that, the mega pillars are made as the through-mold vias to achieve the vertical interconnection. Next, the thermal compression bonding of the chip should be accomplished. That step is followed by molding the whole reconstituted wafer using the thermal compression method. Next comes the back grinding process to get the designed thickness of the EMC. And then, the back side dielectric layer and RDL are formed. The next step is debonding the carrier wafer and attaching the solder balls. Finally, the reconstituted wafer is diced into individual packages.

3. Package-Board Transition in FOWLP

3.1. Selection of the Test Board

Ground–signal–ground (GSG) probes with 100 $\mathsf{\mu }$m or 150 $\mathsf{\mu }$m pitch should be used here to measure the S parameters of the transition up to 86 GHz. However, the minimum line width and space of standard PCB are 100 $\mathsf{\mu }$m, and then the probes can not be appropriately placed. In [23], a 50 $\mathsf{\Omega }$ ceramic-based coplanar waveguide (CPW) transmission line has been wire-bonded to the grounded coplanar waveguide (GCPW) on the PCB to complete the probe-based testing. However, extra de-embedding structures must be used to remove the influences of the GCPW-Bond wire-Ceramic CPW transition. Therefore, to avoid extra de-embedding work, we use the ceramic substrate instead of the PCB and then the probe can touch the GCPW lines properly. The thickness of the ceramic substrate is 127 $\mathsf{\mu }$m. The minimum line width and line spacing of the ceramic substrate is only 15 $\mathsf{\mu }$m.

3.2. Design for the Package-Board Transition

Usually, the transition for the chip-package-board should be considered for the electrical performance of the package. In this paper, the CPW transmission line was chosen as the transmission line in FOWLP because it can be easily connected to the GSG die pad on the chip. Since no test chip was fabricated, as shown in Figure 3, only the CPW transmission line on M1 of the FOWLP and the package-board transition will be optimized and measured.

As shown in Figure 3, the transition model was established in 3-D electromagnetic simulation software, as were other models in this study. Quarter wave impedance transformation technology was utilized to match the package-board transition as shown in Figure 4. The GCPW was chosen as the transition line for the test board. Port 2 was on the package side, and port 1 was on the board side. As shown in Figure 5, the simulated insertion loss for the transition is about 0.82 dB at 79 GHz, and the simulated return loss is better than 10 dB from 72 GHz to 86 GHz. It covers the working frequency band of the automotive radar very well, which is generally from 76 GHz to 81 GHz.

However, the probe cannot be placed at the test ports on the test board and RDL at the same time as shown in Figure 3. It is difficult for us to measure the package-board transition directly.

4. Measurement Methods for the Package-Board Transition

Considering the structure of the package-board transition, which is difficult to measure directly, in this paper, two methods based on the port reduction technique [30,31] and TRL calibration technique [32,33] were used to calculate the S parameter of the transition, respectively.

4.1. Measurement Method Based on the Port Reduction Technique

Figure 6 is the block diagram of the port reduction technique [30]. As shown in Figure 6, we can use a vector network analyzer to perform single-port tests on the reference planes B and A, respectively. The $Z_L$ represents the standard load. The S-parameter matrix of the two-port network can be expressed as

$$\begin{array}{c}\hfill b_1=S_{11}{a}_1+S_{12}{a}_2\\ \hfill b_2=S_{21}{a}_1+S_{22}{a}_2\end{array}$$

(1)

where $a_1,a_2$ represent the waves incident upon the two-port network and $b_1,b_2$ denote the waves reflected from the two-port network. The measured $S_{11}^A$ or $S_{11}^B$ at the A or B reference plane is equivalent to the reflection coefficient and can be expressed as:

$$\begin{array}{c}\hfill S_{11}^B=\frac{b_L}{a_L}\\ \hfill S_{11}^A=\frac{b_1}{a_1}\end{array}$$

(2)

Considering that: $a_L=b_2$, $b_L=a_2$. $S_{11}^A$ can be represented by the $S_{11}^B$ and the S-parameter matrix of the two-port network:

$$S_{11}^A=\frac{b_1}{a_1}=S_{11}+\frac{S_{21}{S}_{12}{S}_{11}^B}{1-S_{22}{S}_{11}^B}$$

(3)

Because the transition network is reciprocal, the $S_{12}$ is equal to $S_{21}$. Then, there will be only three parameters that remain unknown in Equation (3). If three different loads ($Z_{L1},Z_{L2},Z_{L3}$) are designed, we can get three groups of the $S_{11}^A$ and $S_{11}^B$. Thus, the three parameters $S_{11},S_{21},S_{22}$ can be calculated.

$$\begin{array}{c}\hfill S_{11}^{A1}=S_{11}+\frac{S_{21}{S}_{12}{S}_{11}^{B1}}{1-S_{22}{S}_{11}^{B1}}\\ \hfill S_{11}^{A2}=S_{11}+\frac{S_{21}{S}_{12}{S}_{11}^{B2}}{1-S_{22}{S}_{11}^{B2}}\\ \hfill S_{11}^{A3}=S_{11}+\frac{S_{21}{S}_{12}{S}_{11}^{B3}}{1-S_{22}{S}_{11}^{B3}}\end{array}$$

(4)

Usually, an open circuit, a short circuit, and a 50 $\mathsf{\Omega }$ or 75 $\mathsf{\Omega }$ resistance could be used as the standard loads. In this study, as shown in Figure 7, three open-ended transmission lines with different lengths on the RDL were used as the loads $Z_{L1},Z_{L2},Z_{L3}$. The reference plane B in Figure 7 represents the test port on the RDL, and the reference plane A represents the test port on the test board. The reference planes in Figure 7 are the same as that in Figure 6. Before the package is mounted on the test board, the $S_{11}^{Bi}$ (i = 1, 2, 3) of the three one-port standards should be measured by the probe at the pads on the reference plane B. Then, after mounting, the $S_{11}^{Ai}$ could be measured at reference plane A on the test board. With the measurement results, we can get a system of equations as shown in Equation (4), and the S parameter of the transition can be easily calculated at every basic frequency.

4.2. Measurement Method Based on the TRL Technique

In this paper, the TRL calibration technique is used to calculate the S parameter of the transition. As Figure 8 shows, the transitions can be thought of as the error boxes. And thru, reflect, delay line structures are formed on the RDL between the two transitions. The corresponding simulation models are shown in Figure 9. An open structure is used as the reflect standard. Since no open circuit structure was initially designed, we cut the package to obtain the required reflect standard, as shown in Figure 9b.

We should perform tests on port 1 and 2 in Figure 9a to get S parameters ($S_{Thru}$, $S_{Delay}$) of the networks containing the thru, delay line structures. And we should get the reflection coefficient ($S_{Ref}$) of the network with the open structure on port 2 in Figure 9b. For networks containing the thru and delay line structures, we get their wave cascading matrix ($R_{Thru},R_{Delay}$) [32] from the S parameters as shown in Equations (5)–(7). Equation (5) can be obtained from Equation (1). The matrix R in Equation (5) is known as the wave cascading matrix.

$$\left(\begin{array}{c}{b}_1\\ a_1\end{array}\right)=\frac{1}{S_{21}}\left(\begin{array}{cc}-\Delta & S_{11}\\ -S_{22}& 1\end{array}\right)\left(\genfrac{}{}{0pt}{}{a_2}{b_2}\right)=R\left(\genfrac{}{}{0pt}{}{a_2}{b_2}\right)$$

(5)

where

$$\Delta =S_{11}{S}_{22}-S_{12}{S}_{21}$$

(6)

and

$$R=\frac{1}{S_{21}}\left(\begin{array}{cc}-\Delta & S_{11}\\ -S_{22}& 1\end{array}\right)$$

(7)

From Equation (5), we can know that the R matrix for two or more two-ports in cascade is merely the product of the individual R matrices. So, the $R_{Thru},R_{Delay}$ can be expressed as Equations (8) and (9).

$$R_{Thru}=R_{Btp}{R}_{Ptb}$$

(8)

$$R_{Delay}=R_{Btp}{R}_{Line}{R}_{Ptb}$$

(9)

where $R_{Line}$ represents the wave cascading matrix of the delay line on the RDL. If $\gamma$ and l represent, respectively, the propagation constant and the length of the delay line, the $R_{Line}$ can be written as Equation (10) with the assumption that the line is nonreflecting.

$$R_{Line}=\left(\begin{array}{cc}{e}^{-\gamma l}& 0\\ 0& e^{\gamma l}\end{array}\right)$$

(10)

$R_{Btp},R_{Ptb}$ are the wave cascading matrix of the board to package and package to board transitions. They can be calculated through the Equations (8) and (9), and the $S_{Ref}$ using the TRL calibration technique [32]. Thus, we can obtain the S parameter of the package to board transition.

5. Discussion

The fabricated sample of the FOWLP is shown in Figure 10. It has a size of 12 mm × 12 mm. All the structures required for both methods are formed on the RDL, and the sample of the FOWLP is soldered on the ceramic substrate as shown in Figure 11. However, since the test frequency is up to 86 GHz, we haven’t finished the test yet. To verify the feasibility of these two methods, we have performed calculations using the corresponding simulation results.

5.1. Simulation Results Based on Port Reduction Technology

As with the test steps of the port reduction technique, we use the electromagnetic simulation software to obtain the corresponding reflection coefficients of the designed structure at the reference plane A and B. The 3D model are shown in Figure 12. We obtained the reflection coefficients of the three different loads at the port1, port2, port3 ($S_{11}^{B1},S_{11}^{B2},S_{11}^{B3}$) shown in Figure 12a, and the results are shown in Figure 13a. At the same time, we get the reflection coefficients at port1, port2, port3 ($S_{11}^{A1},S_{11}^{A2},S_{11}^{A3}$) on the test board as shown in Figure 12b. Additionally, Figure 13b presents the corresponding simulation results.

With the simulation results $S_{11}^{Ai},S_{11}^{Bi}$, we can obtain the S-parameter matrix of the package-board transition by solving Equation (4) at all the basic frequencies. In addition, we performed a direct simulation of the transition as shown in Figure 14. We call it direct simulation because the ports used in this simulation cannot be used for measurement. It is part of the model in Figure 12b. The calculation and direct simulation results are shown in Figure 15. The solid black line represents the calculated S parameter of the transition. The red and blue dotted lines represent the S parameters of the transition obtained by direct simulations at channel 1 and channel 2, respectively. Although in the two channels, the structures of the package-board transition are completely the same, there are slight differences in the environment where they are. These differences lead to slight differences in their simulation results. The calculated results are consistent with the direct simulation results. The maximum difference of their insertion loss is about 0.15 dB. The little difference between the calculated results and the direct simulation results proves the feasibility of the port reduction method. Since the loads are composed of transmission lines of different lengths, when the package is soldered to the test board, the transmission line will be affected by the test board. This may be part of the reason for the difference.

5.2. Simulation Results Based on TRL Technology

The S parameters of the open, thru, and line structures shown in Figure 9 are obtained through the electromagnetic simulation software. Figure 16 shows S parameters of the thru structure. Thru 1 and thru 2 represent the thru structures shown in Figure 9a. They have the same structure, but the environment is slightly different. This leads to some differences in their S parameters. Therefore, we finally used the results of thru 1 and thru 2 to perform subsequent calculations, respectively. The return loss of the thru structures further prove that a good package-board transition has been obtained. Figure 17 shows S parameters of the line structure, and Figure 18 is for the open structure. We can see that the S${}_{11}$ of the open 1 and open 2 structure is basically the same, so we only use the S${}_{11}$ of open 1 for subsequent calculations.

After getting these S parameters, we can calculate the parameters of the package-board transition through the TRL technology described in Section 4.2. The calculation and direct simulation results are shown in Figure 19. The CPW on the RDL and the GCPW on the test board used in the TRL technique are longer than that in the port reduction technique, so the calculated S parameter is different from the S parameter calculated by the port reduction technique. Result 1 and Result 2 of the TRL calculation are calculated using the S parameters of thru 1 and thru 2, respectively. They are roughly the same, but there are some differences. This tells us that we need to ensure the consistency of the electromagnetic environment as much as possible when designing the experiment. We can find that whether it is reflection coefficient or transmission coefficient, the results calculated by the TRL method and the results obtained by the direct simulation show a relatively high consistency. Therefore, the feasibility of the TRL method is verified.

6. Conclusions

In this paper, a well-matched package-board transition has been designed by using the impedance converter. The simulated insertion loss for the transition is about 0.82 dB at 79 GHz, and the simulated return loss is better than 10 dB from 72 GHz to 86 GHz. The ceramic substrate has been chosen as the test board. Thus, the probe can touch the GCPW lines on the test board directly. In order to solve the challenge of obtaining the measured S-parameter matrix of the package-board transition, two different measurement methods based on the port reduction technique and the TRL technique have been proposed. We analyzed the principles of the two methods and designed the corresponding test structures. At the same time, we verified the feasibility of the two methods by simulation. The results calculated by these two methods are basically the same as the direct simulation results. All the simulation ports used in the two methods can be mapped to actual test ports. Thus, we can measure at the corresponding ports and then calculate the S-parameter matrix of the transition through the two methods. FOWLP and test board samples have been fabricated, and the sample of the FOWLP has been soldered on the test board successfully. The following research work will further verify the two methods through experiments.