Next Article in Journal
A Circuit-Based Wave Port Boundary Condition for the Nodal Discontinuous Galerkin Time-Domain Method
Previous Article in Journal
Single-Branch Wide-Swing-Cascode Subthreshold GaN Monolithic Voltage Reference
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer

1
State-Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
2
Zhangjiang Fudan International Innovation Center, Shanghai 200433, China
3
State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao 999078, China
*
Author to whom correspondence should be addressed.
Electronics 2022, 11(12), 1841; https://doi.org/10.3390/electronics11121841
Submission received: 1 May 2022 / Revised: 2 June 2022 / Accepted: 7 June 2022 / Published: 9 June 2022
(This article belongs to the Section Circuit and Signal Processing)

Abstract

This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s.
Keywords: split CDAC; asynchronous SAR ADC; input PGA; RV-Buffer split CDAC; asynchronous SAR ADC; input PGA; RV-Buffer

Share and Cite

MDPI and ACS Style

Xu, Z.; Hu, B.; Wu, T.; Yao, Y.; Chen, Y.; Ren, J.; Ma, S. A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer. Electronics 2022, 11, 1841. https://doi.org/10.3390/electronics11121841

AMA Style

Xu Z, Hu B, Wu T, Yao Y, Chen Y, Ren J, Ma S. A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer. Electronics. 2022; 11(12):1841. https://doi.org/10.3390/electronics11121841

Chicago/Turabian Style

Xu, Zhuofan, Biao Hu, Tianxiang Wu, Yuting Yao, Yong Chen, Junyan Ren, and Shunli Ma. 2022. "A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer" Electronics 11, no. 12: 1841. https://doi.org/10.3390/electronics11121841

APA Style

Xu, Z., Hu, B., Wu, T., Yao, Y., Chen, Y., Ren, J., & Ma, S. (2022). A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer. Electronics, 11(12), 1841. https://doi.org/10.3390/electronics11121841

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop