A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS
Abstract
:1. Introduction
2. Ring Amplifier Review
3. Proposed ADC Design
3.1. High-Linearity Front-End
3.2. TI-ADC Architecture
3.3. FIFO Details
3.4. Digital Background Calibration
4. Measurement Results
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
CMOS | Complementary metal oxide silicon |
ADC | Analog-to-digital converter |
DAC | Digital-to-analog converter |
GS/s | Giga samples per second |
HVT | High threshold voltage |
LVT | Low threshold voltage |
ESD | Electro-static discharge |
BGA | Ball grid array |
SHA | Sample and hold amplifier |
RA | Residue amplifier |
Ringamp | Ring amplifier |
SAR | Successive-approximation register |
TI | Time interleaved |
NNC | Neural Network Calibration |
FFT | Fast Fourier transform |
FIR | Finite impulse response |
FOM | Figure of merit |
LDO | Low dropout regulator |
MDAC | Multiplying digital-to-analog converter |
SNDR | Signal-to-noise-and-distortion ratio |
SFDR | Spurious free dynamic range |
FIFO | First input first output |
PCB | Printed circuit board |
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Reference | [17] | [18] | [19] | [20] | [21] | This Work |
---|---|---|---|---|---|---|
resolution [b] | 11 | 10 | 12 | 12 | 12 | 12 |
supplies [V] | 1.2/2.5 | 1.2/1.3/1.6 | 1.8 | 2.5 | 1.8 | 1.0/2.0/−0.5 |
architecture | TI-SAR | TI-SAR | TI-Pipeline | TI-Pipeline | TI-Pipeline | TI-Pipelined-SAR |
channel number | 4 × 16 | 4 × 16 | 4 | 2 | 4 | 4 |
fs [GS/s] | 3.6 | 2.6 | 2.4 | 3.0 | 3.0 | 2.5 |
technology [nm] | 65 | 65 | 40 | 40 | 40 | 28 |
area | 7.4 | 5.1 | 9 | 0.4 a | 3.9 a | 1.73 a |
SNDR [dB] | 42.0 b | 48.5 b | 49.7 b | 51.0 b | 52.3 b | 51.0 c |
SFDR [dB] | 50.0 b | 53.8 b | 60.2 b | 59.0 b | 61.5 b | 68.0 c |
power [mW] | 795 | 480 | 420 | 500 | 450 | 418.4 d |
[pJ/conversion-step] e | 2.15 | 0.85 | 0.70 | 0.58 | 0.44 | 0.48 f |
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Lan, J.; Zhai, D.; Chen, Y.; Ni, Z.; Shen, X.; Ye, F.; Ren, J. A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS. Electronics 2021, 10, 3173. https://doi.org/10.3390/electronics10243173
Lan J, Zhai D, Chen Y, Ni Z, Shen X, Ye F, Ren J. A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS. Electronics. 2021; 10(24):3173. https://doi.org/10.3390/electronics10243173
Chicago/Turabian StyleLan, Jingchao, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, and Junyan Ren. 2021. "A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS" Electronics 10, no. 24: 3173. https://doi.org/10.3390/electronics10243173
APA StyleLan, J., Zhai, D., Chen, Y., Ni, Z., Shen, X., Ye, F., & Ren, J. (2021). A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS. Electronics, 10(24), 3173. https://doi.org/10.3390/electronics10243173