Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
AbstractStatic random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC. View Full-Text
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Cargnini, L.V.; Torres, L.; Brum, R.M.; Senni, S.; Sassatelli, G. Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory. J. Low Power Electron. Appl. 2014, 4, 214-230.
Cargnini LV, Torres L, Brum RM, Senni S, Sassatelli G. Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory. Journal of Low Power Electronics and Applications. 2014; 4(3):214-230.Chicago/Turabian Style
Cargnini, Luís V.; Torres, Lionel; Brum, Raphael M.; Senni, Sophiane; Sassatelli, Gilles. 2014. "Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory." J. Low Power Electron. Appl. 4, no. 3: 214-230.