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Design of Processors with Reconfigurable Microarchitecture

School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU, UK
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J. Low Power Electron. Appl. 2014, 4(1), 26-43; https://doi.org/10.3390/jlpea4010026
Received: 2 October 2013 / Revised: 6 January 2014 / Accepted: 8 January 2014 / Published: 20 January 2014
(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)
Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor. View Full-Text
Keywords: microarchitecture; microprocessor; reconfigurability; power proportionality; Conditional Partial Order Graphs microarchitecture; microprocessor; reconfigurability; power proportionality; Conditional Partial Order Graphs
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Mokhov, A.; Rykunov, M.; Sokolov, D.; Yakovlev, A. Design of Processors with Reconfigurable Microarchitecture. J. Low Power Electron. Appl. 2014, 4, 26-43.

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