Batra, P.; Skordas, S.; LaTulipe, D.; Winstel, K.; Kothandaraman, C.; Himmel, B.; Maier, G.; He, B.; Gamage, D.W.; Golz, J.;
et al. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology. J. Low Power Electron. Appl. 2014, 4, 77-89.
https://doi.org/10.3390/jlpea4020077
AMA Style
Batra P, Skordas S, LaTulipe D, Winstel K, Kothandaraman C, Himmel B, Maier G, He B, Gamage DW, Golz J,
et al. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology. Journal of Low Power Electronics and Applications. 2014; 4(2):77-89.
https://doi.org/10.3390/jlpea4020077
Chicago/Turabian Style
Batra, Pooja, Spyridon Skordas, Douglas LaTulipe, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz,
and et al. 2014. "Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology" Journal of Low Power Electronics and Applications 4, no. 2: 77-89.
https://doi.org/10.3390/jlpea4020077
APA Style
Batra, P., Skordas, S., LaTulipe, D., Winstel, K., Kothandaraman, C., Himmel, B., Maier, G., He, B., Gamage, D. W., Golz, J., Lin, W., Vo, T., Priyadarshini, D., Hubbard, A., Cauffman, K., Peethala, B., Barth, J., Kirihata, T., Graves-Abe, T.,
... Iyer, S.
(2014). Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology. Journal of Low Power Electronics and Applications, 4(2), 77-89.
https://doi.org/10.3390/jlpea4020077
