Reduction of Interface State Density in 4H-SiC MOS Capacitors Modified by ALD-Deposited Interlayers

Abstract

This study proposed an innovative method for growing gate oxide on silicon carbide (SiC), where silicon oxide (SiO₂) was fabricated on a deposited Al₂O₃ layer, achieving high quality gate oxide. A thin Al₂O₃ passivation layer was deposited via atomic layer deposition (ALD), followed by Si deposition and reoxidation to fabricate a MOS structure. The effects of different ALD growth cycles on the interface chemical composition, trap density, breakdown characteristics, and bias stress stability of the MOS capacitors were systematically investigated. X-ray photoelectron spectroscopy (XPS) analyses revealed that an ALD Al₂O₃ passivation layer with 10 growth cycles effectively suppresses the formation of the proportion of Si-O_xC_y bonds. Additionally, the SiO₂/Al₂O₃/SiC gate stack with 10 ALD growth cycles exhibited optimal electrical properties, including a minimum interface state density (D_it) value of 3 × 10¹¹ cm⁻² eV⁻¹ and a breakdown field (E_bd) of 10.9 MV/cm. We also systematically analyzed the bias stress stability of the capacitors at room temperature and elevated temperatures. Analysis of flat-band voltage (ΔV_fb) and midgap voltage (ΔV_mg) hysteresis after high-temperature positive and negative bias stress demonstrated that incorporating a thin Al₂O₃ layer at the interface is the key factor in enhancing the stability of V_fb and midgap voltage V_mg.

1. Introduction

Due to its high breakdown electric field and thermal conductivity, SiC has emerged as one of the most promising wide-bandgap semiconductors in power electronics [1,2,3]. However, despite the high bulk electron mobility of 4H-SiC MOSFETs, their performance remains constrained by defects at the SiO₂/SiC interface, particularly carbon-related defects resulting from the oxidation of SiC [4,5,6]. Consequently, the gate oxide performance of SiC MOSFETs remains suboptimal, with field effect mobility significantly lower than the theoretical potential of SiC material, notable threshold voltage instability, and high interface trap densities. These limitations stem primarily from poor MOS interface quality, where interfacial carbon clusters, silicon and carbon vacancies, and oxide charges significantly impede carrier transport [7,8,9]. While commercial SiC MOSFETs operating at 1.2–1.7 kV have been realized, further improvements in interface quality are essential to fully exploit SiC’s high voltage capability for future 3.3–6.5 kV devices.

To enhance the channel mobility of SiC MOSFETs, various passivation techniques have been employed over the past few decades. Post-oxidation annealing (POA) processes using nitrogen, phosphorus, and other elements have elevated channel mobility [10,11,12,13,14,15,16,17]. One strategy involves initially depositing a layer of Si, followed by low-temperature oxidation to construct a theoretically carbon-cluster-free SiC/SiO₂ interface, and subsequently annealing to obtain a high-quality SiO₂ thin film [18]. However, research on this method remains limited. Some studies have indicated that the final oxidation process may lead to the formation of a SiO₂/Si/SiC structure, exhibiting poor C–V characteristics, thereby necessitating further investigation [19].

Introducing high dielectric constant (high-k) materials is a potential solution [20,21,22]. Nevertheless, electrical tests of high-k/SiC MOS devices exhibit significant frequency dispersion [23,24,25]. Several studies have attempted to use Al₂O₃/SiO₂/SiC gate stacks to reduce interface defects, achieving some success, but their C–V curves remain suboptimal, with considerable hysteresis and frequency dispersion [26,27].

Theoretical calculations have shown that carbon defects readily form and stabilize at the SiO₂/SiC interface [11], while experimental studies have found that inhibiting the oxidation of the SiC surface can effectively reduce the D_it [12]. Therefore, suppressing the oxidation of the SiC substrate during device fabrication is crucial for minimizing interfacial carbon defects and enhancing interface quality [28]. The dense Al₂O₃ film effectively inhibits the diffusion of oxygen atoms, particularly gaseous oxygen, thereby preventing oxidation of the underlying SiC [29]. In addition, Jinyu et al. proposed that Al₂O₃ can serve as a passivation layer to improve the interface performance of ErSmO/InP MOS devices, further supporting the strategy of reducing interface defects [30]. Currently, most research involves depositing Al₂O₃ onto ultra-thin thermally oxidized SiO₂ [27,31], but no studies have explored the formation SiO₂ through thermal oxidation on ultra-thin deposited Al₂O₃.

In light of these findings, we propose a novel gate oxide fabrication process: first, a thin layer of Al₂O₃ was deposited using ALD to protect the SiC surface with its exceptional density. Subsequently, Si was deposited and re-oxidized. Leveraging this thin Al₂O₃ layer, we achieved a high-quality gate oxide layer without the need for annealing. Using this method, we successfully improved the interface properties of SiC MOS capacitors and enhanced the stability of the gate flat-band voltage. The electrical performance of the SiC MOS capacitors was assessed through measurements such as I–V characteristics, HF-QS C–V, and C–V tests under positive and negative bias stress. Additionally, AFM was employed to study the morphology of the SiO₂ surface, and XPS was utilized to analyze the chemical bonding at the SiC/SiO₂ interface, revealing the effectiveness of our process from a microscopic perspective.

2. Experimental Methods

2.1. Fabrication of SiC MOS Capacitors

The substrates were n-type 4H-SiC (0001). The epitaxial layer had a doping concentration equal to 1 × 10¹⁶ cm⁻³ and a thickness of 5 μm. As shown in Figure 1, the experimental procedure was as follows:

(a)

The SiC epitaxial wafers were subjected to RCA cleaning to remove surface impurities, ensuring that the wafer surface was clean for the smooth progression of subsequent processes.

(b)

Al₂O₃ was deposited on the epitaxial wafer surface using ALD technology with 10 and 20 cycles, while a sample without Al₂O₃ deposition was prepared as a control group.

(c)

A 20 nm thick Si layer was grown on the prepared three groups of samples in a conventional plasma-enhanced chemical vapor deposition (PECVD) system. The Si film was deposited using SiH₄ gas highly diluted with H_4. The PECVD system operated at a radio frequency of 13.56 MHz, a substrate temperature of 250 °C, and an r.f. power of 50 W.

(d)

The samples underwent wet oxidation at 1100 °C for 2 h, during which the PECVD-grown silicon films were fully oxidized into SiO₂ layers, with consistent silicon growth and thermal oxidation conditions maintained across all samples to ensure experimental uniformity. The samples were classified as follows: SiO₂/SiC-A sample without Al₂O₃ deposition; SiO₂/1 nm-Al₂O₃/SiC-A sample with 10 cycles of Al₂O₃ passivation layers; SiO₂/2 nm-Al₂O₃/SiC-A sample with 20 cycles of Al₂O₃ passivation layers.

(e)

After coating a layer of photoresist on the front side of the sample, hydrofluoric acid was used to remove the excess SiO₂ from the back side of the samples. The photoresist was then removed, and square electrodes, 200 μm in width and 200 nm in thickness, were deposited on the front side using electron beam evaporation. Additionally, a 200 μm thick aluminum electrode was also deposited on the back side of the sample.

2.2. Characterization

The samples’ surface roughness (Rq) and morphology were examined using a Bruker BRK0003 atomic force microscope (AFM) over areas of the sample measuring 5 × 5 μm². Multiple measurements (n = 10) were performed on different areas of each sample, and the most reliable roughness values were determined through statistical analysis for data presentation. The surface chemical states were analyzed using an Escalab 250Xi XPS system from Thermo Scientific equipped with a monochromatic Al-Kα X-ray source at 1486.6 eV and a power of 150 W. Before the XPS analysis, the SiO₂ film on the SiC epitaxy was etched to a thickness of approximately 5 nm using a 1% HF buffered solution.

The electrical properties of the SiC/SiO₂ capacitors were characterized using a TS2000-HP probe station and a Keithley 4200A-S semiconductor analyzer. The insulation and breakdown characteristics of the oxide layer were evaluated by recording the current–voltage (I–V) curves at room temperature. The D_it was extracted using the high–low frequency method within an energy range 0.2–0.6 eV below the conduction band edge. The C–V curves were measured at 300 K using high-frequency (1 MHz) and quasi-static methods. The voltage stabilities were evaluated utilizing V_fb hysteresis after alternate positive bias stress (PBS) and negative bias stress (NBS) at different temperatures (300, 350, 400, and 450 K). The C–V curves were swept from +20 to −20 V after the PBS (+2.5 MV cm⁻¹) for 600 s. Following the same procedure, the C–V curves were swept from −20 to +20 V after the NBS (−2.5 MV cm⁻¹) for 600 s. The V_fb/midgap voltage (V_mg) hysteresis was obtained from the shift between V_fb and V_mg after PBS and NBS.

3. Results and Discussion

3.1. Interfacial Qualities and Characteristics of the SiO₂ Films

The surface roughness of the MOS capacitor was characterized using AFM with a scanning area of 5 × 5 μm². The AFM topographic image was shown in Figure 2, and the root mean square roughness values of the gate dielectric surface were calculated to be 1.15 nm, 1.64 nm, and 2.51 nm, respectively. When the passivation cycle reaches 10 times, the surface roughness of the SiO₂ layer slightly increases to 1.64 nm compared to the control sample. It is noteworthy that the surface roughness increases significantly to 2.51 nm as the passivation interlayer thickens. This increase in roughness can be attributed to the additional ALD process step, which introduces more interfaces and potentially creates more surface irregularities during the fabrication process. However, this increase in surface roughness does not negatively impact the passivation effectiveness of the Al₂O₃ interlayer, as evidenced by our subsequent electrical measurements, which demonstrate that the samples with an Al₂O₃ passivation layer exhibit lower interface defect density and wider barrier height.

XPS was used to analyze the chemical bonds at the SiO₂/SiC interface. The C 1s peak, attributed to adventitious carbon, is typically fixed at approximately 284.8 eV upon calibration of the measurements using a charge neutralizer.

Figure 3 compares the XPS results of the SiC/SiO₂ interface with different Al₂O₃ passivation layers. Two weak Al 2p peaks were detected in both Figure 3(b3,c3) compared to Figure 3(a3). The peak in SiO₂/1 nm-Al₂O₃/SiC with 10 ALD growth cycles in Figure 3(b3) is slightly weaker, while the peak in SiO₂/2 nm-Al₂O₃/SiC with 20 ALD growth cycles in Figure 3(c3) is slightly stronger.

In the Si 2p spectrum, the binding energies are 100.7, 101.7, and 103.1 eV, corresponding to Si–C, Si–O_xC_y, and Si–O bonds, respectively [32,33,34]. The Si 2p spectrum shows a decrease in the SiOxCy components after the passivation layer was added, as shown in Figure 3(b2,c2). These observations indicate that it is unrealistic to prevent oxidation of the SiC substrate solely by temperature control, as low-temperature oxidation may still introduce some issues to the interface properties. However, an appropriate Al₂O₃ passivation cycle can effectively suppress defect formation.

As shown in Figure 4, to study the effect of different passivation growth cycles on the capacitance parameters of SiC/SiO₂ capacitors, the C–V characteristics were measured in the frequency range from 1 kHz to 1 MHz. The experiment revealed that each sample exhibited varying degrees of frequency dispersion. Adding 10 cycles of Al₂O₃ passivation layer helps to suppress the generation of interface defects, allowing most carriers to accumulate effectively on the semiconductor surface, thereby improving the dielectric performance of the SiC MOS capacitors. When the passivation cycle reaches 20c, SiO₂/2 nm-Al₂O₃/SiC exhibits significant frequency dispersion. To quantitatively analyze the impact of different passivation layer thicknesses on the SiO₂/SiC interface characteristics, we extracted the values of D_it for each sample, as shown in Figure 4d. The results indicate that around E_c − E_t ≈ 0.3 eV, the D_it values for the three samples are approximately: 5 × 10¹¹, 2 × 10¹¹, and 4 × 10¹¹ cm⁻² eV⁻¹, respectively. Compared to the structure without a passivation layer, the D_it at various energy levels is reduced after adding the Al₂O₃ passivation layer, especially around the trap energy level of approximately 0.6 eV, where a more significant reduction in D_it is observed. This demonstrates that the addition of the passivation layer effectively reduces the interface state density, thereby improving the quality of the interface, with the SiO₂/1 nm-Al₂O₃/SiC structure exhibiting lower D_it values than the SiO₂/SiC structure; moreover, compared to the previously reported Al₂O₃/SiC structures [35], our composite structure also achieves a significant reduction in D_it values, further confirming the effectiveness of this passivation approach.

However, in the MOS structure with the Al₂O₃ passivation layer, the D_it value for SiO₂/2 nm-Al₂O₃/SiC configuration is obser ved to be higher than that for the SiO₂/1 nm-Al₂O₃/SiC configuration. This deterioration in interface quality with increasing Al₂O₃ thickness (from 1 nm to 2 nm) can be attributed to the underlying mechanisms governing interface formation. As reported by Boan et al. [26], when gate materials are directly deposited on SiC using ALD techniques, the resulting interface typically exhibits significantly higher D_it values compared to thermally grown oxides. Their research revealed that Al₂O₃/SiC interfaces formed through direct deposition generally exhibit poor interface quality. To address this issue, researchers have developed two main approaches: (1) Applying post-deposition annealing treatments to improve the electrical properties of the ALD-deposited dielectric layer and its interface with SiC [36,37]; (2) Adopting a multilayer structure where SiC is first thermally oxidized to form a SiO₂ layer before depositing high-K materials (such as HfO₂/Al₂O₃) on top, creating a high-K material/thermally oxidized SiO₂/SiC stack that significantly reduces interface trap densities [27,38]. Based on these findings, we propose that as the Al₂O₃ layer thickness increases from 1 nm to 2 nm, its functional role shifts from primarily acting as a passivation layer to resembling a directly ALD-deposited gate oxide in direct contact with SiC. At 1 nm thickness, the Al₂O₃ layer effectively passivates interface traps while preserving the advantageous properties of the underlying thermally grown SiO₂/SiC interface. However, at 2 nm thickness, the Al₂O₃ layer begins to dominate the interface characteristics, leading to properties that closely resemble those of direct ALD-deposited Al₂O₃/SiC structures, which inherently exhibit higher D_it values. This thickness-dependent transition in interface behavior accounts for the observed increase in D_it values despite the increased physical thickness of the passivation layer. Consequently, the careful optimization of the Al₂O₃ passivation layer thickness is crucial to prevent the Al₂O₃ layer from transitioning from a passivation effect to a layered structure.

To study the effect of the Al₂O₃ passivation layer on the insulating properties of the SiO₂ film, we performed I–V measurements. The current density–electric field (J–E) curves of the SiC MOS capacitors were shown in Figure 5. Compared to the SiO₂/SiC sample, the SiO₂/1 nm-Al₂O₃/SiC and SiO₂/2 nm-Al₂O₃/SiC exhibit lower leakage currents, with the E_bd increasing to 10.9 MV/cm, 9.94 MV/cm, respectively. All three samples show typical Fowler–Nordheim (FN) tunneling characteristics. The expression for FN tunneling is as follows [39]:

$$J={\displaystyle \frac{q^3{E}^2}{16{\mathsf{\pi }}^2\hslash {\phi }_{\mathrm{o}\mathrm{x}}}}\exp \left[-{\displaystyle \frac{4\sqrt{2m_{\mathrm{T}}^{*}{\phi }_{\mathrm{B}}^{3/2}}}{3\hslash qE}}\right]$$

(1)

where q is the elementary charge, $m_{\mathrm{T}}^{*}$ is the effective mass of the electrons in the SiO₂ film, and ℏ is the reduced Planck constant. By calculating the J–E data for the three samples, the results are shown in

Table 1. Comparison of barrier height and breakdown field for the three 4H-SiC MOS structures.

	Theoretical [28]	SiO2/SiC	SiO2/1 nm-Al2O3/SiC	SiO2/2 nm-Al2O3/SiC
φB (eV) @25 °C	2.7	2.15	2.51	2.37
Ebd (MV cm−1)	10	9.64	10.9	9.94

. We calculated the effective electron barrier heights for SiO₂/SiC, SiO₂/1 nm-Al₂O₃/SiC, and SiO₂/2 nm-Al₂O₃/SiC, which are 2.15 eV, 2.51 eV, and 2.37 eV, respectively. Therefore, it can be concluded that the passivation layer effectively prevents the diffusion of harmful chemical species during the oxidation process of SiC, as previously reported in previous studies [29]. This helps improve the insulating properties of the SiO₂ film and contributes to a more stable and improved interface structure. This also explains why the conduction band offset of SiO₂/1 nm-Al₂O₃/SiC is closer to the theoretical value.

3.2. Thermal Stability of SiC MOS Capacitors

In SiC MOS devices, the main sources of instability are typically considered to be the SiC/SiO₂ interface and its near interface charge trapping, as well as the mobile ions in the gate oxide [40,41]. As shown in Figure 6, all the high-frequency (HF) C–V curves exhibit a counterclockwise hysteresis, indicating that the impact of trap charge trapping on the C–V drift in the samples is smaller than the effect of mobile ions [33].

We also studied the changes in ΔV_fb and ΔV_mg hysteresis under alternating PBTS and NBTS at temperatures of 300 K, 350 K, 400 K, and 450 K for samples with passivation layer thicknesses. As shown in Figure 7 and Figure 8, ΔV_fb and ΔV_mg were extracted using midgap capacitance and flat-band capacitance as reference points. It was observed that in all three samples, the HF C–V curve hysteresis of SiO₂/1 nm-Al₂O₃/SiC was relatively small at different temperatures, which demonstrates that the Al₂O₃ passivation layer with ten cycles reduces the traps near the interface, thereby improving the stability of BTS. Combined with the D_it results, it can be inferred that the 10c Al₂O₃ layer effectively prevents low-temperature oxidation of SiC and reduces interface traps, thereby improving the interface quality and the V_fb stability of the SiC MOS capacitors. As the passivation cycle reaches 20c, the ΔV_fb and ΔV_mg of SiO₂/2 nm-Al₂O₃/SiC significantly increase. This increased hysteresis behavior indicates that the excessive Al₂O₃ passivation layer induces additional activated traps under high-temperature stress.

4. Conclusions

In this study, a SiO₂/4H-SiC gate dielectric with low interface state density and high stability was successfully fabricated. A novel process was employed, in which an ultra-thin passivation layer of Al₂O₃ was deposited on the SiC surface using ALD. The Al₂O₃ layer protected the SiC surface by preventing the diffusion of harmful chemical species during the oxidation process. Si was then deposited atop the Al₂O₃ layer and re-oxidized to form a high-quality gate oxide layer. We systematically investigated the influence of the Al₂O₃ passivation layer on interface properties and optimized the fabrication method. Compared to samples without the Al₂O₃ passivation layer, the SiO₂/1 nm-Al₂O₃/SiC MOS capacitor demonstrated a significant reduction in D_it. Long-term high-temperature stability was assessed via flat-band voltage bias stress tests, revealing that the Al₂O₃ layer effectively suppressed the formation of near interface oxide traps and enhanced the stability of the oxide layer. This method offers a novel avenue for overcoming the performance bottlenecks of SiC MOSFETs.