Effect of Chromium Adhesion Layer Thickness on Contact Resistance and Schottky Barrier Characteristics in WSe₂ Field-Effect

Abstract

While metal adhesion layers are commonly used in the fabrication of field–effect transistors (FETs) based on two-dimensional (2D) materials, the impact of adhesion layer thickness on device performance remains insufficiently explored. In this study, we systematically investigate how the thickness of a Cr adhesion layer influences the contact resistance and Schottky barrier characteristics of multilayer WSe₂ FETs. Contact resistance results, extracted via the transfer length method for Cr thicknesses of 1 nm, 4 nm, and 7 nm, reveal that thicker Cr layers (4 nm and 7 nm) result in significantly lower resistance (<200 kΩ·μm) compared to the much higher resistance (6.6 MΩ·μm) observed with 1 nm Cr thickness. Temperature–dependent transport measurements and Arrhenius analysis further indicate a reduction in Schottky barrier height with increasing Cr thickness, implying improved carrier injection. These results specifically demonstrate how the commonly used Cr adhesion layer thicknesses of at least 4 nm increase the electrical performance of WSe₂–based devices.

1. Introduction

Over the past several decades, two–dimensional (2D) materials such as tungsten diselenide (WSe₂) and molybdenum disulfide (MoS₂) have garnered significant attention as promising candidates for next–generation electronic and optoelectronic devices due to their unique electrical and optical properties. Applications of 2D materials include various optoelectronic devices such as 2D material–based photodetectors, memory devices, gas sensors, and field–effect transistors (FETs). The fundamental architecture of these devices typically features metallic source and drain electrodes in contact with a 2D semiconductor channel that allows to evaluate electrical performance. Utilizing this 2D electronic platform, extensive research has been conducted to explore the interesting electrical properties of 2D materials, including high carrier mobility, tunable bandgaps, high on/off current ratio, and low power consumption [1,2,3,4,5,6,7]. Nevertheless, realizing higher performance 2D electronic devices remains a technical challenge. Particularly, one of the primary limiting factors playing a critical role in device performance is the contact resistance at the interface between the metal electrodes and the 2D semiconductor channel [8,9].

Contact resistance at the metal–semiconductor interfaces is influenced by several factors, including the choice of contact metal, resist residues left from fabrication processes, adsorption of ambient molecules such as water and oxygen, and trapped charges at the interface. Among these, selection of the electrode metal has a significant effect on charge injection through Schottky barrier formation, metal–induced gap states, and interfacial contamination [10,11,12,13,14,15]. Specifically, Au, a commonly used electrode metal, exhibits relatively weak van der Waals bonding with both SiO₂ and WSe₂ surfaces, resulting in poor adhesion [16]. To overcome this weak adhesion, reactive metals such as Cr or Ti are often employed as adhesion layers that enhance the interface characteristics between the electrode metal and the 2D material [17]. Additionally, the work function of Cr (≈4.5 eV) is lower than that of Au (≈5.1 eV), leading to a lower Schottky barrier height (SBH) when Cr is in contact with n–type WSe₂. In contrast, Au with a higher work function induces stronger band bending and a higher SBH, making electron injection more difficult and increasing contact resistance [18].

While 5 nm and 10 nm adhesion layer thicknesses are commonly employed for the electrodes of WSe₂ FETs, more comprehensive studies are required to justify their selection and assess their impact on device performance. Given that even nanometer–scale changes at the metal–semiconductor interface can affect charge transport, optimizing the thickness of the Cr adhesion layer is crucial for improving the device characteristics. Furthermore, although adhesion layers have been relatively well studied in devices based on graphene and MoS₂, their impact on WSe₂–based devices also warrants investigation due to different material properties, including the work function.

In this study, we investigate the role of Cr adhesion layer thickness in determining contact resistance and SBH in WSe₂–based FETs. Using the transfer length method (TLM), we first extract contact resistance in devices with Cr thicknesses of 1 nm, 4 nm, and 7 nm. While the 4 nm and 7 nm Cr devices exhibit low contact resistance below 200 kΩ·μm, the 1 nm Cr device shows a significantly higher resistance of 6.6 MΩ·μm. We then conduct temperature–dependent transport measurements and Arrhenius analysis, with the results demonstrating that the SBH decreases as the Cr layer thickness increases. This trend suggests that thinner Cr layers generate higher Schottky barriers, leading to reduced carrier injection efficiency.

2. Experimental Methods

Figure 1a shows an optical microscopic image of a fabricated WSe₂ FET device. Multilayer WSe₂ and hexagonal boron nitride (hBN) were stacked on 300 nm SiO₂ on a highly p–doped Si substrate using a dry pick–up method with a polypropylene carbonate stamp [19]. Placing hBN under WSe₂ flakes maintains the intrinsic properties of WSe₂ and reduces gate–induced hysteresis, which helps systematic electrical measurement [20,21,22]. As shown in the inset of Figure 1a, the thickness of the WSe₂ was measured to be approximately 12 nm using atomic force microscopy (AFM) (Park systems, Suwon, Republic of Korea). While this image represents a single device, multiple WSe₂ FETs were fabricated and investigated in this study, using WSe₂ flakes with thicknesses ranging from 10 to 20 nm. The Au electrodes with a Cr adhesion layer were fabricated using e–beam lithography and e–beam evaporation. To obtain the contact resistance of the fabricated devices using the TLM, the channel length was varied between 1, 2, 3, and 5 μm, while the channel width was fixed at 8 μm. Figure 1b illustrates a schematic of the device structure and a representative plot showing the concept of the TLM to calculate the contact resistance [23]. In this method, we determine the contact resistance from the y–intercept, corresponding to zero channel length, by measuring the total resistance across multiple channels with varying lengths (d₁ to d₄). To investigate the effect of Cr thickness on contact resistance, Cr layers of 1, 4, or 7 nm were deposited as adhesion layers before depositing the Au layers of identical 50 nm thickness. Because the WSe₂–metal interface critically influences the contact resistance, the Cr adhesion metal layer in contact with the WSe₂ flake was deposited at a slower deposition rate, with the aim to reduce damage to the 2D material surface during the deposition process (0.1 Å/s for Cr and 0.5 Å/s for Au). The electrical characteristics of all devices were measured using a Keithley 2502 picoammeter (Keithley Instrument, Cleveland, OH, USA), with the gate voltage (V_G) applied via a back–gate configuration. All measurements were conducted under vacuum conditions to reduce the effects of surface contaminations due to ambient molecules [22,24].

3. Results and Discussion

3.1. Calculation of Contact Resistance Using TLM

Figure 2a,b show the transfer and output curves of a WSe₂ FET with varying channel lengths with a fixed Cr thickness of 7 nm. Here, V_G was swept from −50 V to +50 V with the drain–source voltage (V_DS) fixed at 0.2 V. The observed n–type behavior is consistent with a previous report using Cr/Au electrodes [25]. As shown in Figure 2c,d, the drain–source current (I_DS) decreases with increasing channel length due to general resistive properties, which allows for the calculation of the contact resistance using the TLM [23]. Notably, a substantial reduction in contact resistance was observed at higher doping concentrations. This reduction is attributed to a decrease in the width of the depletion layer near the metal–semiconductor interface, which reduces the width of the barrier for tunneling [26,27]. As a thinner tunneling barrier allows a higher current to flow, the contact resistance decreases.

To investigate the role of the adhesion metal layer thickness in the contact resistance, we obtained the transfer curves of WSe₂ FETs with Cr thicknesses of 1, 4, and 7 nm and extracted the corresponding contact resistance, as shown in Figure 3a. We observe significantly higher contact resistance in the device with a Cr thickness of 1 nm, reaching ≈6.6 MΩ∙μm at V_G − V_TH = 50 V. In comparison, the device with 4 nm Cr shows a markedly lower contact resistance of ≈45 kΩ∙μm under the same doping concentration, representing a reduction by a factor of ≈150. The 7 nm Cr device also shows a resistance much lower than that of the 1 nm device, indicating that dramatic improvement occurs once the Cr thickness reaches 4 nm. Analyzing the dependence of contact resistance on doping concentration for different Cr thicknesses, we consistently observe that higher doping levels result in lower contact resistance independently of Cr thickness. Figure 3b plots the contact resistances at V_G = 50 V for several devices fabricated under the same conditions, where the resistance variation by thickness originates from unintended fabrication variation. The contact resistance for a Cr thickness of 1 nm remains in the megaohm range, while in contrast, the contact resistances for Cr thicknesses of 4 nm and 7 nm are below 200 kΩ∙μm. These results indicate that a Cr thickness of at least 4 nm is required to achieve efficient n–type carrier injection in WSe₂ FETs.

3.2. Schottky Barrier Height by Cr Thickness

The contact resistance in these FETs is strongly influenced by the interface between WSe₂ and Cr. When WSe₂ and Cr come into contact, Fermi level alignment according to the difference in their Fermi levels leads to band bending, which in turn forms a Schottky barrier [18]. To contribute to the drain–source current, charge carriers must overcome the Schottky barrier via either thermionic emission or tunneling [28]. In order to find the relation between the contact resistance and the Schottky barrier as a function of Cr thickness, we extracted the SBH from temperature–dependent resistance measurements of WSe₂ FETs with varying Cr adhesion layer thickness.

According to the Arrhenius equation, the current density changes with temperature under the following equation,

$$J=A^{\ast \ast }{T}^2\mathit{exp}\left(-{\displaystyle \frac{q{\varphi }_B}{k_{B}T}}\right)\left[\exp \left({\displaystyle \frac{q{V}_{DS}}{k_{B}T}}\right)-1\right]$$

(1)

Here, $J$ is the drain–source current density, $A^{\ast \ast }$ is the Richardson constant, $k_B$ is the Boltzmann constant, and ${\varphi }_B$ is the Schottky barrier height. Taking the logarithm of both sides of the equation, we get:

$$\mathit{ln}\left({\displaystyle \frac{I_{DS}}{T^2}}\right)=\mathit{ln}\left({AA}^{**}\right)-{\displaystyle \frac{q({\varphi }_B-V_{DS})}{k_{B}T}}$$

(2)

Figure 4a presents the temperature–dependent transfer curves of WSe₂ FETs with a 7 nm Cr layer. We observe an increase in the on–current with temperature, implying enhanced thermionic emission over the Schottky barrier at elevated temperatures, thereby improving carrier injection at the metal-semiconductor interface. These transfer curves were then used to generate Arrhenius plots of $\mathit{ln}\left({\displaystyle \frac{I_{DS}}{T^2}}\right)$ versus 1000/$T$ for the WSe₂ FETs, as shown in Figure 4b, with gate voltages ranging from −20 V to +50 V in 10 V steps. Steeper slopes at negative gate voltages indicate stronger temperature dependence, while flatter slopes at higher gate voltages suggest less dominant thermal dependence and possible contribution by tunneling. By extracting the slope at each gate voltage in the Arrhenius plots, the effective SBH can be obtained as a function of V_G, which is plotted in Figure 4c. In this plot, the effective SBH initially varies linearly at negative gate voltage, but deviates from linearity beyond a certain point, as marked with the black arrow. This transition point is used to determine the SBH [28]. For the device with 7 nm Cr, the extracted SBH is ≈31 meV. In order to explain the transition point in more detail, in Figure 4d we present simplified band diagrams for gate voltages below, at, and above the flat–band voltage (V_FB), referring to the gate voltage at which the band flattens in the semiconductor region. When V_G is less than V_FB, thermionic emission dominates the electron transport owing to the large Schottky barrier width, resulting in the effective barrier height scaling linearly with V_G. However, when V_G is higher than V_FB, tunneling begins to contribute via the narrower Schottky barrier width from increased doping concentration, breaking the linear relationship between the effective barrier height and the gate voltage [29,30]. Therefore, the point at which linearity ends in the graph of effective Schottky barrier versus gate voltage can be considered as the SBH.

Additionally, we extracted the SBH for Cr thicknesses of 1 nm and 4 nm and present the results in Figure 5a and Figure 5b, respectively. Figure 5c summarizes the contact resistance and SBH as a function of Cr thickness in fabricated WSe₂ FETs. As the Cr thickness increases, the SBH decreases from 100 meV at 1 nm to 56 meV at 4 nm. Both contact resistance and barrier height decrease with increasing Cr thickness. These experimental results confirm that the higher contact resistance observed with the thin Cr adhesion layer (1 nm) can be attributed to the increased SBH.

To validate the SBH extraction methodology used in this study, next we investigated the variation in SBH induced by image force lowering. Near a metal-semiconductor interface, electrons or holes experience additional attractive forces from their induced image charges, which reduces the potential energy barrier and facilitates transport. This phenomenon, known as image force lowering, decreases the effective SBH [31,32,33,34]. The barrier height decreased by this effect is determined by the following equation:

$$∆{\varphi }_B=\sqrt{{\displaystyle \frac{qE}{4\pi {\epsilon }_s}}}$$

(3)

where q is the charge, ε_s is the dielectric constant of the semiconductor, and E is the electric field inside the semiconductor. As V_DS increases, the electric field E increases, and accordingly, Δϕ_B increases, and the effective barrier height Δϕ_B^eff that the electrons must overcome is lowered according to

$${\varphi }_B^{eff}={\varphi }_B-{∆\varphi }_B$$

(4)

Figure 6a shows the change in the effective SBH for the 1 nm Cr device at a drain–source voltage of 0.05 V and as it increases from 0.1 V to 1.2 V in 0.1 V steps. The effective barrier height decreases nearly linearly with increasing V_DS, consistent with the image force lowering effect. In Figure 6b, we plot the effective SBH versus V_DS. The results show that the effective SBH decreases as V_DS increases, providing evidence that the reduction in SBH is due to the image force lowering effect caused by the increased electric field inside the semiconductor.

4. Conclusions

In summary, we showed the effect of Cr adhesion layer thickness on the contact resistance and Schottky barrier characteristics of WSe₂–based FETs. Using a device structure compatible with the TLM, we first extracted the contact resistance as a function of Cr layer thickness. While devices with 4 nm and 7 nm Cr layers exhibited low contact resistance below 200 kΩ·μm, the device with a 1 nm Cr layer showed a significantly higher resistance of 6.6 MΩ·μm, indicating that Cr thickness critically affects the quality of the metal–semiconductor interface. Therefore, we conclude that Cr thicknesses of 4 nm and above represent the optimum thickness for minimizing contact resistance in FET devices. In addition, we extracted the SBH from temperature–dependent measurements using Arrhenius plots. The extracted SBHs were 100 meV for 1 nm Cr, 56 meV for 4 nm, and 31 meV for 7 nm. This trend supports that thinner Cr layers result in higher Schottky barriers, leading to poor carrier injection and increased contact resistance. Furthermore, we examined the image force lowering effect and found that the SBH decreased linearly with increasing drain–source voltage, confirming the theoretical predictions and the reliability of our SBH results. Our findings demonstrate that optimizing the Cr adhesion layer thickness is essential for minimizing contact resistance and improving device performance in WSe₂–based FETs. These insights offer valuable guidelines for the design of low-resistance contacts in 2D material–based electronic devices.