SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed

Abstract

Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase operation. Therefore, the gate-induced drain leakage (GIDL) erase method, which utilizes band-to-band tunneling (BTBT) to raise the channel potential, is employed. However, compared to bulk erase, the BTBT-based erase method requires a longer time to generate holes in the channel, leading to erase speed degradation. To address this issue, we propose a structure which enhances the erase speed by surrounding the bitline (BL) PAD with SiGe. In the case of a SiGe thickness (t_SiGe) of 13 nm, the lower bandgap of SiGe increases the BTBT generation rate, boosting the channel potential rise at the end of the erase voltage ramp-up by 861% compared to the Si-only structure, while limiting the reduction in read on-current to within 4%. We modeled the voltage and electric field across the SiGe layer, as well as BTBT generation rate and GIDL current in the SiGe layer, by varying t_SiGe, Ge composition ratio (SiGe_X), and the voltage difference between V_BL and V_{GIDL_TR}.

1. Introduction

Early planar NAND Flash technology pushed integration density by shrinking cell dimensions while adding more wordlines (WLs). However, as the cell pitch decreased, capacitive coupling between adjacent cells exacerbated program-and-read disturbances, limiting further scaling in the 2D planar architecture [1]. To address these issues, a vertically stacked 3D NAND structure was proposed [2,3]. This architectural transition to a vertically stacked array significantly improved data storage density, marking a technological breakthrough. In the first stage of 3D NAND Flash development, the cell array was integrated next to the peripheral circuit. Peripheral circuit area remains unchanged despite the advances in NAND array technology. To further improve integration density [4,5], the cell-over-peripheral (COP) structure was introduced [6,7,8,9,10,11], allowing more efficient use of wafer space by placing the cell array above the peripheral circuit. However, unlike in the conventional structure, the channel in the COP structure is not electrically connected to the bulk substrate. As a result, during the erase operation, it is impossible to increase the channel potential by applying a high voltage directly to the substrate. Therefore, the gate induced drain leakage (GIDL) erase method, which utilizes band-to-band tunneling (BTBT) of electrons from the valence band into the conduction band at the drain junction to generate holes in the channel and raise the channel potential, is employed in the COP structure [7,12].

However, since this hole-accumulation mechanism relies on hole generation to raise the channel potential, it requires a longer time than the bulk erase method. Moreover, as the number of WLs increases, the channel capacitance increases proportionally, further prolonging the time needed for the same hole-induced potential change and degrading overall erase throughput. Such prolonged erase time not only degrades the write performance but also raises power consumption.

Previous studies have attempted to solve this issue either by integrating undoped Si around the bitline (BL) PAD or by employing SiGe material in order to enhance BTBT and the hole generation rate [13,14]. Additionally, dynamic voltage scheduling based on machine learning has been proposed to generalize fixed-time erase profiles [15]. To further boost the erase speed, we propose a structure with SiGe surrounding the BL PAD in this work. SiGe has a narrower bandgap than Si, resulting in an increased BTBT rate and a significantly higher hole generation rate that accelerates erase speed while minimizing the reduction in read on-current after programming. We used Sentaurus TCAD simulation tool from Synopsys and modeled a single 96-WL 3D NAND string based on the COP structure and verified the effectiveness of this approach. Furthermore, we developed a quantitative model for the electrical characteristics such as BTBT rate and GIDL current by analyzing the voltage across the SiGe layer, the resulting electric field, and the channel potential with varying t_SiGe, Ge composition ratio, and the voltage difference between BL PAD and GIDL transistor (GIDL TR). We also evaluated the reduction in read on-current by varying the program voltage, erase voltage, Ge composition ratio, and SiGe thickness (t_SiGe). As a result, the SiGe-surrounded BL PAD approach improved erase speed while minimizing the reduction in read on-current.

2. SiGe-Surrounded BL PAD Structure and Erase Speed Enhancement

Figure 1 shows the cross-sectional view of a 3D NAND with 96 WLs in the COP structure used for the TCAD simulation. The diagram includes detailed material information and layer thicknesses. In this work, we propose an approach in which an undoped SiGe layer surrounds a n+ doped BL PAD. For the device simulation, the SiGe composition was specified by setting the Ge composition ratio (SiGe_X) to the desired value.

The carrier recombination model was based on Shockley–Read–Hall (SRH) processes with doping dependence, while BTBT was modeled using the Hurkx formulation [16]. Carrier transport employed the Philips unified mobility (PhuMob) model calibrated for arsenic doping, supplemented by an electric field normal to the interface (Enormal) high-field saturation correction to capture velocity saturation effects. Meanwhile, in the nitride layer, we introduced donor trap energy level of 2.5 eV below the conduction band and acceptor traps 1.0 eV below the conduction band, each at a density of 1 × 10²⁰ cm⁻³ with electron and hole capture cross-sections of 1 × 10⁻¹³ cm².

Next,

Table 1. Bias Conditions for Program, Erase, and Read Operations in 3D NAND Flash.

Contact	Erase	Program	Read
BL	VERS	0 V	0.2 V
CSL	VERS	0 V	0 V
SSL	10 V	7 V	7 V
GSL	10 V	7 V	7 V
GIDL transistor	10 V	7 V	7 V
Selected WL	0 V	VPGM	VRead
Unselected WLs	0 V	7 V	5 V

shows the operating voltages for the program, erase, and read operations in 3D NAND Flash. Figure 2 presents the timing diagrams for the erase sequences. As shown in Figure 2, the erase voltage V_ERS is applied simultaneously to the BL and common source line (CSL), while the GIDL transistor (GIDL TR), string-select line (SSL), and ground-select line (GSL) are held at a fixed 10 V. The erase operation is divided into a 0.1 ms ramp-up phase followed by a 1 ms erase execution phase. The V_PGM is applied to the selected WL for 30 µs, while the SSL, GSL, GIDL TR, and unselected WLs are held at 7 V and the BL and CSL are held at 0 V. The erase operation is performed across the entire string, while the program operation is carried out only on the selected WL.

Figure 3 shows the portion of the energy band diagram along the A–A′ cut in Figure 1 for a SiGe thickness of 5 nm. The band diagram was taken immediately after the 0.1 ms ramp-up of the 14 V erase voltage. It highlights how the bandgaps of the pure Si (SiGe₀) and SiGe_0.5 materials differ. The horizontal axis shows the position along the A–A′ direction, and the vertical axis shows energy level. Because SiGe_0.5 has a narrower bandgap than Si (SiGe₀), electrons can tunnel more readily from the valence band into the conduction band, yielding a higher BTBT rate. This explains the differences in average channel potential rise and GIDL current observed in Figure 4 and Figure 5 as functions of Ge composition ratio and t_SiGe.

Figure 4 shows the average channel potential for various Ge composition ratios. The SiGe bandgap shrinks as x increases [17], directly boosting the BTBT rate in the SiGe layer, which in turn accelerates the average channel potential rise and boosts the GIDL current during the erase operation. Figure 4 confirms that the SiGe-surrounded device sustains higher GIDL current than the Si-only case, with SiGe_0.5 achieving 2775% higher GIDL current than SiGe₀ at 0.1 ms.

Figure 5 illustrates how t_SiGe affects the average channel potential at a fixed Ge ratio of 0.5. When calculating capacitance for a parallel-plate capacitor, the capacitance is inversely proportional to its dielectric thickness. For a cylindrical capacitor, the capacitance is inversely proportional to the natural logarithm of the ratio of its outer radius and inner radius. If we define this value as the effective thickness of a cylindrical capacitor, the effective thickness increases superlinearly with the layer thickness. This means the capacitance of a cylindrical capacitor decreases more rapidly as thickness increases, compared to the parallel-plate structure. Therefore, the voltage-division rule causes the voltage across the SiGe layer in the cylindrical structure to increase superlinearly with the layer thickness. Consequently, the electric field in the SiGe layer increases as the thickness increases, causing higher BTBT rate and accelerating the rise of the average channel potential. However, beyond a t_SiGe of 16 nm, the BL PAD area reduction causes a steep rise in its series resistance. Although the BTBT-active region grows, the high resistance of cylindrical BL PAD region hinders the potential increase and hole generation, so the erase operation time increases significantly and limits its use in actual devices.

Figure 6 shows a detailed comparison of the erase threshold voltage shift (ΔV_th) as a function of Ge composition ratio for different t_SiGe values under (a) a 0.5 ms and (b) a 1 ms erase execution time. When the erase execution time is shorter, the Ge composition ratio has larger impact on the threshold voltage shift. This indicates that increasing Ge composition ratio is essential for reducing the erase execution time. Additionally, for a Ge composition ratio exceeding 0.3, a thinner t_SiGe layer results in the highest ΔV_th. This is due to the increased series resistance caused by the thicker undoped SiGe layer itself, inducing 0.2~0.3 V of voltage drop in the SiGe region and reducing the maximum voltage reaching the channel. The reduced voltage eventually limits the saturating channel potential level. However, since a higher erase voltage at the BL can easily offset this voltage drop effect, we can fully obtain the erase speed improvement benefit resulting from the increased SiGe thickness.

We confirmed that applying a SiGe layer does not degrade the read performance. As shown in Figure 7, increasing the Ge ratio reduces the read on-current because the electron and hole mobility of SiGe drop by up to 80% and 25%, respectively. In Figure 7, the read on-current gradually decreases as the t_SiGe increases, reflecting both the material’s lower mobility and the increased series resistance of a thicker layer. However, on-current decrease relative to the mobility degradation is small because the SiGe layer occupies only a small fraction of the total area, limiting its impact on overall current. Since the maximum on-current reduction remains within 4%, the erase process can still be accelerated by up to 861% with only a minimal effect on read performance. Considering the large resistance and capacitance of WL and BL of 3D NAND array, 4% on-current degradation of the 3D NAND string is ignorable for read latency.

As shown in Figure 4 and Figure 5, the GIDL current reaches its peak at 0.1 ms, which corresponds to the end of the ramp-up phase of the erase operation. Therefore, we designated this timepoint as the reference for modeling in Section 3.

3. Modeling of GIDL Erase with SiGe Surrounded Structures

In this section, we provide a detailed explanation of the methodology and modeling results of the erase operation of the SiGe integrated structure. First, we derived the capacitance of each layer between the BL PAD and the GIDL transistor over the A–A′ region in Figure 1 using the cylindrical capacitance calculation method to calculate the voltage across all layers during the erase operation. Figure 8 compares the voltage across the SiGe layer of cylindrical capacitor modeling results and the TCAD simulation results for different t_SiGe values. When t_SiGe is below 15 nm, the difference between the modeling results and the TCAD simulation results is at most 5%, demonstrating a high accuracy of the model. However, when t_SiGe is thicker than 16 nm, as mentioned in Section 2, the reduction in the BL PAD area causes its resistance to increase, preventing the BL PAD potential from reaching the intended level in time. As a result, a voltage discrepancy arises between the TCAD simulation and the modeling results. Therefore, we excluded the electrical characteristics modeling for the cases of t_SiGe over 16 nm in this work.

Figure 9 shows the distribution of the induced electric field and the resulting net generation–recombination rate via BTBT ($R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$) in the SiGe layer when t_SiGe is 13 nm, Ge composition ratio is 0.5, and 14 V applied to BL. Here, r_in denotes the radius of the BL PAD, and r_out denotes the outer radius including the SiGe layer. The average electric field (E_{avg_SiGe}) in the sidewall and bottom region of the SiGe layer was modeled as a function of t_SiGe as Equation (1). C_total is the equivalent series capacitance of bandgap-engineered ONO layer, channel poly-Si layer, and SiGe layer. Since the electric field in the surface region near the BL is significantly larger than elsewhere and $R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$ in this area dominates the total hole generation, this part was mainly considered in the modeling. The calculated E_{avg_SiGe} was used to determine the surface electric field (E_sur) as defined in Equation (2). The parameter α in Equation (2) is a fitting parameter that adjusts the surface electric field according to the V_ERS-V_{GIDL_TR} value. Additionally, the electric field in the corner region (E_cor) was also separately modeled, as described in Equation (3).

$$E_{avg\_SiGe}={\displaystyle \frac{V_{SiGe}}{t_{SiGe}}}=(V_{ERS}-V_{GIDL\_TR}){\displaystyle \frac{C_{total}}{C_{SiGe}{t}_{SiGe}}}$$

(1)

$$E_{\mathrm{s}\mathrm{u}\mathrm{r}}(r)\left[\mathrm{V}/\mathrm{c}\mathrm{m}\right]=(E_{\mathrm{a}\mathrm{v}\mathrm{g}\_\mathrm{S}\mathrm{i}\mathrm{G}\mathrm{e}}-\left({\displaystyle \frac{r_{\mathrm{i}\mathrm{n}}+r_{\mathrm{o}\mathrm{u}\mathrm{t}}}{2}}-r\right){\displaystyle \frac{d{E}_{\mathrm{s}\mathrm{u}\mathrm{r}}(r)}{dr}})\alpha$$

(2)

$$E_{\mathrm{c}\mathrm{o}\mathrm{r}}(r,\theta )\left[\mathrm{V}/\mathrm{c}\mathrm{m}\right]=E_{\mathrm{s}\mathrm{u}\mathrm{r}}(r)\cos \theta$$

(3)

Based on the individually calculated E_sur and E_cor, we calculated the $R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$ occurring in each region during the erase operation using Equations (4) and (5) from the Hurkx model [16,18]. Equation (5) defines the correction factor D used in the Hurkx model when computing the $R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$. Here, n and p are the electron and hole concentrations, respectively, and n_i is the intrinsic carrier concentration. The parameter β in Equation (4) is a correction factor varying with the Ge composition ratio and V_ERS-V_{GIDL_TR}, and E_sur or E_cor is assigned to E in Equation (4) depending on the location of $R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$. As Ge composition ratio increases, the bandgap narrows and $R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$ increases.

By integrating $R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$ for the whole SiGe region at the 0.1 ms point during the erase operation, we modeled the total GIDL current I_{BTBT_total} as Equation (6). The comparison results between the TCAD simulation and modeling for various t_SiGe, Ge composition ratio, V_ERS-V_{GIDL_TR} are shown in Figure 10.

$$R_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}} [/{\mathrm{c}\mathrm{m}}^3·\mathrm{s}\mathrm{e}\mathrm{c}]=3.5\beta D{E}^{2}exp(-2.25/E)$$

(4)

$$D=\left({\displaystyle \frac{np-{n_{\mathrm{i}}}^2}{(n+n_{\mathrm{i}})(p+n_{\mathrm{i}})}}\right)$$

(5)

$$I_{\mathrm{B}\mathrm{T}\mathrm{B}\mathrm{T}\_\mathrm{t}\mathrm{o}\mathrm{t}\mathrm{a}\mathrm{l}} \left[A\right]={\iiint }_{SiGe}q{R}_{\mathrm{n}\mathrm{e}\mathrm{t}}^{\mathrm{b}\mathrm{b}}$$

(6)

4. Conclusions

This study demonstrates the feasibility of a SiGe-based structure for improving the erase speed of 3D NAND Flash. For this approach, a simple low-pressure chemical vapor deposition (LPCVD) process is used to deposit undoped poly-Si, followed in the same step by the introduction of GeH₄ to form SiGe, thereby ensuring full compatibility with standard 3D NAND fabrication flows. Through a simple SiGe deposition that is fully compatible with 3D NAND fabrication process, it can be a solution to achieve faster erase speed in future COP structures of which the number of WLs exponentially increases and the channel capacitance becomes significantly larger. Since GIDL erase is expected to be used in next-generation 3D NAND with hybrid bonding technology [19], our proposal remains effective and applicable.