A New Asymmetric H-6 Structured Multilevel Inverter with Reduced Power Components
Abstract
:1. Introduction
2. Proposed Topology
3. Simulation and Experimental Investigation
4. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Algorithm | Voltage Sources Values and Max. Output Voltage | No. of Voltage Levels | Blocking Voltage |
---|---|---|---|
Proposed Algorithm 1 | (8 × n) + 1 | 27nVdc | |
Proposed Algorithm 2 | (12 × n) + 1 | 44nVdc | |
Proposed Algorithm 3 | 44Vdc; n = 1 [44 + (5 × 2n) + (17 × 2n − 1)] × Vdc; n > 1 | ||
Proposed Algorithm 4 | 27Vdc; n = 1 27 × [1 + 3n − 1] × Vdc; n > 1 | ||
Proposed Algorithm 5 | 27Vdc; n = 1 [27 + (22 × 2n] × Vdc; n > 1 | ||
Proposed Algorithm 6 | 27Vdc; n = 1 [27 + (44 × 3n − 1] × Vdc; n > 1 | ||
Proposed Algorithm 7 | 34Vdc; n = 1 27 × [1 + 4n − 1] × Vdc; n > 1 | ||
Proposed Algorithm 8 | [44 × 5n − 1] × Vdc | ||
Proposed Algorithm 9 | [44 × 7n − 1] × Vdc | ||
Proposed Algorithm 10 | [95 × 25n − 1] × Vdc |
Stages | PA3 | PA4 | PA5 | PA6 | PA7 | PA8 | PA9 | PA10 |
---|---|---|---|---|---|---|---|---|
I (S = 13) | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 5Vdc Vd(2,1)’ = 5Vdc |
III (S = 39) | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc Vd(1,2) = 2Vdc Vd(2,2) = 2Vdc Vd(1,2)’ = 4Vdc Vd(2,2)’ = 4Vdc Vd(1,3) = 4Vdc Vd(2,3) = 4Vdc Vd(1,3)’ = 8Vdc Vd(2,3)’ = 8Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = 3Vdc Vd(1,2) = 3Vdc Vd(2,2) = 3Vdc Vd(1,2)’ = 3Vdc Vd(2,2)’ = 3Vdc Vd(1,3) = 9Vdc Vd(2,3) = 9Vdc Vd(1,3)’ = 9Vdc Vd(2,3)’ = 9Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc Vd(1,2) = 2Vdc Vd(2,2) = 2Vdc Vd(1,2)’ = 4Vdc Vd(2,2)’ = 4Vdc Vd(1,3) = 4Vdc Vd(2,3) = 4Vdc Vd(1,3)’ = 8Vdc Vd(2,3)’ = 8Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc Vd(1,2) = 3Vdc Vd(2,2) = 3Vdc Vd(1,2)’ = 6Vdc Vd(2,2)’ = 6Vdc Vd(1,3) = 9Vdc Vd(2,3) = 9Vdc Vd(1,3)’ = 18Vdc Vd(2,3)’ = 18Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = Vdc Vd(2,1)’ = Vdc Vd(1,2) = 4Vdc Vd(2,2) = 4Vdc Vd(1,2)’ = 4Vdc Vd(2,2)’ = 4Vdc Vd(1,3) = 16Vdc Vd(2,3) = 16Vdc Vd(1,3)’ = 16Vdc Vd(2,3)’ = 16Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc Vd(1,2) = 5Vdc Vd(2,2) = 5Vdc Vd(1,2)’ = 10Vdc Vd(2,2)’ = 10Vdc Vd(1,3) = 25Vdc Vd(2,3) = 25Vdc Vd(1,3)’ = 50Vdc Vd(2,3)’ = 50Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 2Vdc Vd(2,1)’ = 2Vdc Vd(1,2) = 7Vdc Vd(2,2) = 7Vdc Vd(1,2)’ = 14Vdc Vd(2,2)’ = 14Vdc Vd(1,3) = 49Vdc Vd(2,3) = 49Vdc Vd(1,3)’ = 98Vdc Vd(2,3)’ = 98Vdc | Vd(1,1) = Vdc Vd(2,1) = Vdc Vd(1,1)’ = 5Vdc Vd(2,1)’ = 5Vdc Vd(1,2) = 25Vdc Vd(2,2) = 25Vdc Vd(1,2)’ = 125Vdc Vd(2,2)’ = 125Vdc Vd(1,3) = 625Vdc Vd(2,3) = 625Vdc Vd(1,3)’ = 3125Vdc Vd(2,3)’ = 3125Vdc |
Ref. | IGBTs | Gate Drivers | DC Sources | TBV | Levels |
---|---|---|---|---|---|
14 | 10n | 9n | 4n | 33n | 16n + 1 |
19 | 5n + 6 | 5n + 6 | 3n + 1 | 7(2(n + 2)) − 22 | (2(n + 3)) − 5 |
23 | 6n + 8 | 6n + 7 | 4n + 1 | 144n + 12.5 | 12n + 13 |
26 | 8n | 8n | 3n | 2(7n − 1) | 7n |
28 | 10n | 9n | 4n | 17(15n − 1)/7 | 15n |
Proposed MLI (PA10) | 13n | 13n | 4n | 95(25(n − 1)) | 25n |
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Radhakrishnan, A.; Arasan, E.S.; Ramalingam, B.C.; Chandrasekaran, K. A New Asymmetric H-6 Structured Multilevel Inverter with Reduced Power Components. Symmetry 2024, 16, 72. https://doi.org/10.3390/sym16010072
Radhakrishnan A, Arasan ES, Ramalingam BC, Chandrasekaran K. A New Asymmetric H-6 Structured Multilevel Inverter with Reduced Power Components. Symmetry. 2024; 16(1):72. https://doi.org/10.3390/sym16010072
Chicago/Turabian StyleRadhakrishnan, Annadurai, Elankurisil S. Arasan, Balamurugan C. Ramalingam, and Kannan Chandrasekaran. 2024. "A New Asymmetric H-6 Structured Multilevel Inverter with Reduced Power Components" Symmetry 16, no. 1: 72. https://doi.org/10.3390/sym16010072
APA StyleRadhakrishnan, A., Arasan, E. S., Ramalingam, B. C., & Chandrasekaran, K. (2024). A New Asymmetric H-6 Structured Multilevel Inverter with Reduced Power Components. Symmetry, 16(1), 72. https://doi.org/10.3390/sym16010072