Recent Advancements in N-polar GaN HEMT Technology

Abstract

N-polar GaN HEMT technology has emerged as a disruptive technology that outperforms Ga-polar GaN HEMTs in terms of high-frequency power amplification capability. In this paper, the authors present a comprehensive review of the evolution of N-polar GaN HEMT technology from the perspective of crystal growth, dielectrics, and metals on N-polar GaN, transistor design, and performance. Specifically, the authors discuss the progress of the N-polar GaN HEMTs toward high-frequency, high-power, and high-efficiency applications with recent record-level performances, demonstrated by the authors, at mmWave frequencies.

1. Introduction

The III-Nitride material system, particularly GaN, is a leading platform for a wide range of applications in RF electronics, power conversion electronics, and optoelectronics. This arises from the combination of properties, including the high electron mobility; wide bandgap; and critical breakdown electric field, direct bandgap, and piezoelectric properties. So far, virtually every GaN device on the market has leveraged wafers grown on the (0001) c-plane, where large area wafers can be grown hetero- and homo-epitaxially with high electronic and optical material quality. These wafers are referred to as Ga-polar as the crystal unit cell is oriented with the metal atoms at the surface, enabling the success of the AlGaN/GaN high electron mobility transistor (HEMT). GaN HEMTs leverage a strongly polarized (Al,Ga)N or other barrier to induce a two-dimensional electron gas (2DEG) on top of a GaN channel, whose conductivity is modulated by a gate electrode. These devices exhibit high RF output power density and low capacitance, which have led them to become a primary technology of choice for high-power solid-state RF amplification, particularly for applications with high operating frequency, total power, bandwidth, and efficiency, which include many 5G base stations, SATCOM gateways, and RADARs. These properties led them to be adopted for power supplies as well, which require higher power density, higher efficiency, and small size, such as in the case of data center power supplies, compact portable chargers, and motor drives.

While exceptional results have been obtained from these metal-polar materials, there is always a desire for higher performance. For RF applications, three classes of challenges are highlighted here as the work reviewed in this paper: First, limited amplifier bandwidth by the transistor knee current density impacting the Bode–Fano load matching bandwidth at a given operating voltage [1,2]; second, dispersion’s long-term memory effects directly impacting power density, efficiency, and linearity [3]; and third, lower power density and efficiency at W-band and higher frequencies compared to lower operating frequencies. As discussed in previous reviews [4,5,6], the N-polar crystal orientation provides numerous and desirable advantages for HEMTs to tackle these challenges. Specifically, N-polar GaN has demonstrated differentiated performance at elevated frequencies up to the W-band (75–110 GHz) due to inverted polarization, which enables high-conductivity channels to be positioned very close to a gate electrode without the constraint of the barrier thickness-to-gate aspect ratio. The N-polar GaN deep recess HEMT structure extends on these benefits, as the GaN cap grown in situ forms a highly effective first layer of surface-state passivation for dispersion control while also enhancing the conductivity of the access regions through the inverted polarization of the N-polar structure, leading to addressing challenges on W-band power density and efficiency and Bode–Fano output matching the bandwidth limit [7,8].

In this review, the authors discuss the work on N-polar GaN RF and mm-wave transistors toward the recent world-record mmWave HEMT performance demonstrated by the authors. Firstly, the authors discuss the evolution of epitaxial growth of N-polar GaN structures with molecular beam epitaxy (MBE) and metal–organic chemical vapor deposition (MOCVD). Then, the authors discuss recent developments in dielectric and Schottky–barrier contacts on N-polar GaN for gate module development. Finally, the recent advancements in device structures and the electrical performance of these devices are discussed in depth.

2. Growth of N-polar GaN Epitaxy

There are two main techniques used to support the epitaxial growth of GaN. These consist of molecular beam epitaxy (MBE) [9,10,11,12,13,14,15,16,17] and metal–organic chemical vapor deposition (MOCVD) [5,6,18,19,20,21,22,23,24,25]. MBE enables the use of advanced in situ monitoring tools, such as reflection high-energy electron diffraction (RHEED) [26,27,28,29,30] and residual gas analysis (RGA) [31]. However, MBE requires an ultra-high vacuum (UHV) environment, maintained by multiple UHV ion and cryo-pumps, making both operation and maintenance time-consuming and expensive. Despite these challenges, the UHV conditions in MBE enable the growth of atomically precise (layer-by-layer control down to the monolayer) growth of GaN, which makes MBE particularly valuable for fundamental research and certain defense applications. As for commercial applications, MOCVD is attractive due to much faster growth rates (1.5–2 μm/h) than MBE (0.2–0.3 μm/h). This higher throughput, along with scalability and cost efficiency, has made MOCVD the preferred method for commercial device production. Moreover, for commercial LEDs and power electronics applications (based on Ga-polar), most GaN heterostructures are grown with MOCVD [32,33]. While not addressed in this report, the geometry of MOCVD reactors and other physical parameters play a critical role—particularly in commercial applications—in achieving uniform, high-quality films in large-scale reactors. These design considerations are typically informed by computational fluid dynamics, gas-phase chemistry, and surface chemistry studies [34,35,36,37,38].

We have described N-polar GaN growth using both conventional epitaxial growth methods, e.g., MBE and MOCVD, in this manuscript. In this section below, the epitaxial growth of N-polar GaN structures is discussed with molecular beam epitaxy (MBE) and metal–organic chemical vapor deposition (MOCVD) techniques.

2.1. Molecular Beam Epitaxy (MBE) Growth

The MBE growth of Ga-polar GaN has been extensively investigated over the last few decades [9,10,11,12,13,14,15,16,17]. Both Ga-polar and N-polar GaN by MBE can be grown in Ga-rich and N-rich growth regimes, resulting in smooth surfaces and rough surfaces, respectively. Although N-polar growth shares some similarities to Ga-polar growth, the surface morphologies, chemical properties, and growth kinetics differ significantly between the two polarities [39]. In particular, the presence of less than a monolayer (ML) and 2 ML Ga adlayer under Ga-rich conditions is essential for achieving a smooth surface for N-polar and Ga-polar, respectively. Therefore, for N-polar GaN, the controlled Ga-adlayer is key for enabling the growth of N-polar GaN by MBE on an on-axis substrate, whereas for N-polar GaN by MOCVD, it generally requires miscut substrates.

2.1.1. N-polar GaN on Sapphire by MBE

One of the most widely used substrates for GaN heteroepitaxy is (0001) c-plane sapphire (Al₂O₃), primarily because of its low cost despite its low thermal conductivity of 20–40 W/m·K at room temperature [40] and large lattice mismatch with GaN. Unlike N-polar GaN growth by MOCVD, which typically requires a miscut substrate, N-polar GaN can be grown on on-axis substrates by MBE. The polarity of GaN grown on sapphire is mainly dependent on nucleation layers, such as sapphire nitridation and the use of a low-temperature AlN buffer layer [17,41,42,43,44,45].

Moreover, the polarity of GaN is also influenced by the nitridation temperature and growth conditions of GaN and AlN. High-temperature growth of AlN and GaN tends to yield metal-polar and N-polar GaN, respectively. In contrast, a low-temperature GaN nucleation layer can produce GaN with mixed polarity [41]. Additionally, the polarity of (Ga-polar/N-polar) of MBE-grown GaN can be switched between Ga-polar and N-polar through extremely high Mg doping [46,47,48]. Notably, O. Ambacher and his team demonstrated the formation of 2DEG in N-polar GaN/AlGaN heterostructure grown on sapphire substrate by PAMBE in 1999 (the first demonstration) [30,42,44].

2.1.2. N-polar GaN on C-Face SiC Using MBE

The polarity of GaN grown on Si or sapphire is determined by the nucleation layer used during growth [6,49,50,51]. In contrast, the polarity of GaN grown on SiC is dictated by the substrate face of SiC. An Si- or C-face results in a Ga-face or N-face GaN, respectively. Additionally, SiC is a preferred substrate for N-polar GaN growth for high-frequency and high-power electronics due to its smaller lattice mismatch with GaN (3.4%) and superior thermal conductivity of >280 W/m·K [52] compared to sapphire. Monroy et al. first successfully demonstrated N-polar GaN on C-face SiC using the PAMBE growth technique in 2004 [39]. They confirmed the findings via reflection high-energy electron diffraction (RHEED) and enhanced etching of GaN grown on C-face SiC in KOH, a well-established property of N-polar GaN [39,53]. A growth rate up to ~1.5 μm/h has also been achieved using MBE, which is comparable to the MOCVD growth techniques [54]. Due to the challenges associated with N-polar GaN growth by MOCVD, a lot of earlier research on N-polar GaN devices utilized GaN heterostructures grown using MBE on C-face SiC substrates [50].

In the early stage of development, N-polar HEMT structures were grown on C-face SiC using PAMBE [49,50]. The N-polar GaN HEMTs exhibited step flow growth with sub-nm RMS roughness (<1 nm) and a low dislocation density on the order of 1 × 10⁹–1 × 10¹⁰ cm⁻² for film thickness up to the micron range. HEMT fabricated on the N-polar GaN on C-face SiC demonstrated two-dimensional electron gas (2DEG) density of ~6 × 10¹² cm⁻² and room-temperature hall mobilities as high as 1200 cm²/V·s [6,50].

However, MBE grown GaN on any foreign substrate, such as SiC, sapphire, or Si, generally exhibits high dislocation density (1 × 10¹⁰ cm⁻²), which can degrade the electrical and optical performance of N-polar GaN-based devices [55,56,57,58]. Therefore, to address this issue, MOCVD-grown GaN templates are often utilized as a substrate for MBE growth of Ga-polar III-nitride-based heterostructures [55,56,57,59]. Similarly, N-polar GaN templates grown using MOCVD on foreign substrates have also been used for MBE growth of N-polar heterostructures on C-face SiC [60,61]. However, these MOCVD-grown N-polar GaN templates are typically grown on miscut substrates. PAMBE growth of (Al, Ga, In)N layers on such miscut substrates can lead to several issues, such as surface pit formation, step bunching, or compositional inhomogeneity, depending on different growth conditions [60,61].

2.2. Metal–Organic Chemical Vapor Deposition (MOCVD) Growth

2.2.1. General Challenges in MOCVD Growth of N-polar GaN

At face value, the growth of N-polar GaN resembles that of Ga-polar GaN. Both polarizations typically employ trimethylgallium (TMGa) and ammonia as precursors for template growth, as well as the use of other precursors, such as trimethylaluminum to grow Al(Ga)N, bis(cyclopentadienyl)iron (CP₂Fe) for semi-insulating GaN, and disilane for Si n-type doping and in situ Si₃N_4x cap layers. Nevertheless, the growth of high-quality N-polar GaN by MOCVD lies within a tighter process window compared to the Ga-polar orientation [62,63]. With unoptimized growth conditions and unsuitable substrate surface misorientation angles, N-polar GaN suffers from infamous hexagonal hillock morphological defects, which are detrimental to device fabrication. These defects are believed to originate from the clustering of adatoms on the growth surface due to the reduced surface mobility of reactive species in N-polar GaN, and this is supported by theoretical studies which predict larger diffusion barriers for Ga adatoms on N-terminated GaN surfaces [64]. Furthermore, their presence has been reported not only on foreign substrates, but also on bulk GaN substrates [65].

Pioneering work by Keller et al. [66] revealed that the mitigation of hillock defects in N-polar GaN lies in a combination of growth conditions that favor higher adatom mobility, as well as the use of substrates with a surface misorientation. A series of growths with higher growth temperatures and lower ammonia flows resulted in smoother films [67]. From a thermodynamic perspective, these favorable growth conditions correspond to a regime of low Ga supersaturation [68]. It is worth noting that excessively high growth temperatures may avoid hillock formation but lead to a degradation in morphology through step-bunching [69] and pit formation [68].

Beyond optimized growth conditions, the incorporation of substrate misorientation angles also plays a crucial role. The same study by Keller et al. showed that N-polar GaN films grown on sapphire substrates with misorientation angles less than 2° resulted in the formation of hillock defects, while films grown on substrates with a misorientation of 2° or greater showed a greatly reduced or zero hillock defect density. Misorientation angles of 3° and 4° proved to be the most robust. This is a result of surface misorientation increasing the density of atomic steps, which in turn promotes the incorporation of impinging Ga adatoms via step-flow growth. More precisely, dense terrace widths introduced by the surface misorientation are shorter than the diffusion length of Ga adatoms associated with island growth, and as a result, hexagonal-hillock formation can be suppressed in this manner. Atomic force microscopy (AFM) images revealed substrate misorientation-induced steps in the morphology that travel parallel to the plane of substrate misorientation in sapphire, as shown in Figure 1, left. It is worth noting that the hexagonal basal plane of GaN grown on sapphire has been found to be rotated 30° with respect to that of the sapphire substrate [70]. Therefore, GaN grown on sapphire with a misorientation toward the a-plane direction <1120>_Sapphire will result in the m-plane direction of GaN <1100>_GaN traversing along the misorientation-induced steps in the m-plane of GaN, as shown in Figure 1, right and vice versa.

It was also observed that increasing misorientation angles resulted in a reduction in threading dislocation density, as determined by the full width at half maximum (FWHM) of X-ray diffraction (XRD) rocking curves. For a GaN buffer of 0.8 μm grown on a sapphire wafer with a 4° misorientation toward the a-plane, FWHM values as low as 300 arcsec and 510 arcsec were measured for the GaN (0002) and (2021) reflections, respectively. These values are comparable to those of Ga-polar GaN grown using MOCVD on sapphire.

The growth of N-polar GaN by MOCVD is also less forgiving than Ga-polar GaN with regard to impurity incorporation. The incorporation of oxygen as an impurity is a notable hurdle, which leads to unintentional n-type doping in GaN [71,72]. A study by Fichtenbaum et al. carried out across a wide range of growth conditions revealed that the oxygen concentration in regrown N-polar GaN films was always at least 10 times greater than on co-loaded Ga-polar templates [73]. In later years, the O and C concentrations in N-polar films could be reduced to levels below 10¹⁷ and 10¹⁶ cm⁻³, respectively, with optimized growth conditions and improved process purity [5].

A discussion of how growth conditions affect impurity concentrations is warranted. Higher growth temperatures sharply reduce the incorporation of oxygen and carbon, as reported in the range of 900 °C to 1050 °C [74]. It has been reported that oxygen substitutes N atoms at the group-V site in GaN, thus bonding with neighboring Ga atoms [75]. Due to the noncentrosymmetric nature of GaN, in Ga-polar growth, N and O atoms form bonds at the growth surface with a single Ga atom. However, in N-polar growth, N and O atoms bond with three neighboring Ga atoms. The resulting stronger affinity for these atoms at the growth surface causes lower O desorption rates, which leads to the higher O concentration in N-polar films. The desorption of O from these sites is enhanced by higher growth temperatures. A reduction in O concentration with increased V/III ratio, as reported by Fichtenbaum et al. [73], can also be explained by a similar argument whereby an abundance of N from higher V/III ratios reduces the extent of O substitution at the group-V site. With regard to C impurity, the main knob for C incorporation is the growth temperature, which enhances the removal of methyl groups from the growth surface [5].

2.2.2. Growth of N-polar GaN on SiC by MOCVD

The unit cells of both 4H-SiC and 6H-SiC adopt the wurtzite structure (space group P6₃mc), which inherently breaks inversion symmetry along the c-axis [76]. The earliest reported N-polar AlGaN/GaN HEMT grown by MOCVD on SiC was in 2009 by Brown et al. at UCSB [77]. The device material was grown on n-type 4H-SiC misoriented 4° toward the m-plane. The growth layers consisted of a 25 nm AlN nucleation layer grown at 1200 °C, followed by a 60 nm unintentionally doped (UID) GaN layer grown at 990 °C to confer a smooth surface to subsequent films. The remaining template consisted of a 1.3 μm semi-insulating GaN buffer.

The AlGaN back barrier consisted of 20 nm of Si-doped Al_0.25Ga_0.75N and 10 nm of UID Al_0.25Ga_0.75N. Si-doping of the AlGaN back barrier was used to shift the Fermi level away from the valence band and toward the conduction band. This doping scheme is employed in order to mitigate DC-RF dispersion caused by unintentionally modulated traps located ~60 meV at negatively polarized hetero-interfaces [50], such as the interface between the AlGaN back barrier and the GaN buffer. Near the channel, the back barrier is not Si-doped so as to avoid impurity scattering from ionized dopants.

The GaN channel was 25 nm and was capped with 5 nm of SiN_x grown in situ to serve as a gate dielectric. The two-dimensional electron gas (2DEG) density and mobility were 6.6 × 10¹² cm⁻² and 1370 cm²/V·s, respectively, as measured using a room-temperature Van der Pauw Hall setup. MIS-FETs with optical gates with a 0.7 μm gate length were fabricated with this material and were oriented such that the channel runs perpendicular to the substrate mis-orientation direction. The reasons for this are discussed in a subsequent section. Small-signal measurements of these devices yielded a considerable difference between de-embedded and intrinsic f_T and f_MAX values, suggesting that there was a considerable degree of parasitic capacitance between the pads and the n-type SiC substrate. Building on Brown et al.’s initial report, later MOCVD-grown N-polar GaN HEMTs on SiC achieved progressively higher RF performance. While still utilizing 4H-SiC misoriented 4° toward the m-plane along with an AlN nucleation layer and semi-insulating GaN buffer, Kolluri et al. introduced key modifications to the epitaxial growth of N-polar HEMTs on SiC [78]: semi-insulating substrates were used rather than the previously reported n-type in order to minimize parasitic pad-to-substrate capacitance. Furthermore, the first 20 nm of the AlGaN back barrier was not only Si-doped, but also graded from Al_0.05Ga_0.95N to Al_0.38Ga_0.62N to further minimize DC-RF dispersion [50]. An AlN interlayer between the AlGaN back barrier and GaN channel was introduced in order to enhance 2DEG mobility. On top of a 25 nm UID GaN channel, a 2 nm Al_0.60Ga_0.40N cap was grown to minimize gate leakage [50]. The growth was terminated with 5 nm of SiN_x grown in situ.

The two-dimensional electron gas (2DEG) density and mobility were measured to be 9 × 10 cm⁻² and 110 cm²/V·s, respectively, as measured using a room-temperature Van der Pauw Hall setup. MIS-FETs fabricated from this material with a 0.7 μm gate length, along with a better match between intrinsic f_T and f_MAX values to de-embedded values, suggest that semi-insulating SiC substrates are key in mitigating parasitic pad-to-substrate capacitance.

2.2.3. Growth of N-polar GaN on Sapphire by MOCVD

Unlike SiC, sapphire belongs to the R3C space group and thus does not break inversion symmetry, nor possess inherent polarization. Therefore, the initiation of N-polar GaN on sapphire necessitates the formation of a nitridation layer [79,80,81]. This step can be achieved via thermal nitridation, whereby the flow of ammonia over the sapphire substrate at high temperatures converts the surface of the sapphire (Al₂O₃) to AlN. The nitridation layer is followed by a GaN nucleation layer, which accommodates the 16% lattice mismatch between sapphire and GaN [82]. Early investigations of 2DEG properties of N-polar AlGaN/GaN heterostructures grown via MOCVD on misoriented sapphire substrates noted an inherent anisotropy in the sheet resistance of TLMs oriented parallel and perpendicular to the misorientation direction [83]. TLMs oriented such that current flow is within the misorientation-induced steps (parallel to the steps) had 85% or less measured sheet resistance than TLMs oriented perpendicular to the steps. Van der Pauw Hall sheet resistance values were generally at an intermediate value. This observation is consistent with increased carrier scattering rates associated with elevated surface roughness in GaN HEMTs [84], resulting in lower 2DEG mobility. The growth of N-polar GaN HEMT active layers on sapphire does not differ significantly from those on SiC mentioned previously once a semi-insulating template has been established [85]. Selective area regrown n++ GaN contacts by MOCVD have been studied in Ga-polar [86] and N-polar GaN as an alternative to annealed contacts.

A study by Hatui et al. has demonstrated 27 nm N-polar GaN contact layers with a carrier concentration and mobility as high as 3.5× 10²⁰ cm⁻³ and 80 cm²/V·s, respectively, leading to a sheet resistance of 57.3 Ω/☐ [87]. The contact resistance obtained with these layers with unannealed Ti/Au metal contacts was 0.032 Ω·mm. These n++ N-polar GaN layers were grown after a semi-insulating GaN template grown on sapphire substrates with a 4° misorientation toward the a-plane of sapphire. The n++ layers with the lowest sheet resistance were grown at a temperature of 850 °C, and Si-doping of GaN was achieved using disilane. The authors made use of flow-modulation epitaxy, whereby trimethylgallium and disilane were introduced separately in repeated looped steps. This method was also tested as a regrowth contact layer to an N-polar HEMT. TLMs of the regrown n++ layer itself showed a sheet resistance of 103 Ω/☐ and a contact resistance of 0.050 Ω·mm. The contact resistance as measured by TLMs for the regrown contacts to the 2DEG was 0.262 Ω·mm.

2.2.4. Growth of N-polar GaN on Silicon by MOCVD

Smooth and high-quality N-polar GaN-on-silicon films with treading dislocation densities comparable to Ga-polar GaN-on-Si films and N-polar GaN/AlGaN/GaN transistors were demonstrated via metal–organic chemical vapor deposition on (111) Si substrates with 3.5° to 6° miscut [88,89]. The N-polarity was achieved through high-magnesium doping during deposition of the AlGaN strain management layers [90]. MOCVD-grown N-polar HEMTs exhibited a sheet electron density of 9 × 10¹² cm⁻² and an electron mobility of 1135 cm²/V·s.

2.2.5. Growth Uniformity

Although there has been a limited number of studies on N-polar growth uniformity, 4-inch N-polar GaN HEMT wafers grown via Transphorm (part of Renesas) have shown excellent uniformity across the wafer. A sheet resistance non-uniformity of as low as 2% was shown in [32], with a low sheet resistance of <260 Ω/☐ on sapphire and SiC substrates. Additionally, ref. [91] demonstrated 2.16% sheet resistance non-uniformity and a very low gate voltage standard deviation of 93 mV across a 4 in HEMT wafer on SiC grown via Transphorm.

3. Dielectric and Schottky Barrier Contact Studies on N-polar GaN

In any semiconductor transistor technology, the development of dielectrics and Schottky barrier contacts is of utmost importance for the gate module, which directly governs the channel modulation, trapping, breakdown characteristics, and reliability. In this section, the studies on the dielectrics and Schottky barrier contacts on N-polar GaN are discussed, focusing mainly on the capacitance and diode characterization studies for insight into implementation in transistors later.

3.1. Dielectrics on N-polar GaN

Insulators play an important role in reducing the leakage current in the transistor through the gate. Many dielectrics on N-polar GaN have been researched, including SiO₂, Si₃N₄, HfO₂, Al₂O₃, and AlSiO. Overall, it is important to have a dielectric with a high dielectric constant to allow for proper aspect ratio when scaling devices, allow for a growth technique that can be easily added into a device process for scalability, and most importantly, to have low leakage with low trapping behavior.

Many N-polar GaN MISHEMTs have used MOCVD Si₃N₄ for the gate dielectric, which has shown the ability to handle large E-fields and keep leakage current low [8,92,93]. Si₃N₄ on N-polar GaN has shown a barrier height around 1 eV with varying metals, with Ni and Pt showing a difference in offsets less than their respective work functions. This can be explained by Fermi level pinning due to traps at the GaN/SiN interface [94]. Studies have shown that MOCVD-grown Si₃N₄ is able to handle larger E-fields compared to MOCVD-grown SiO₂ due to the presence of more traps within the SiN that creates a non-constant E-field across the SiN and reduces the peak E-field at the Insulator/N-polar GaN interface, which therefore increases the breakdown field [95]. MOCVD Si₃N₄ also showed a larger increase in trap density after stress compared to MOCVD SiO₂. Changes in trapped states under the gate of a HEMT can lead to shifts in the threshold voltage during stress conditions such as large signal measurements [96].

HfO₂ has also been studied as a high-k dielectric on N-polar GaN that can be grown with atomic layer deposition (ALD). ALD growth has the benefit of being easily achieved during processing when compared to MOCVD-grown films. HfO₂ grown at 300 °C on AlGaN showed to have excess traps when compared to films grown on GaN or MOCVD Si₃N₄ [97]. This was explained to be caused by a trap-filled Al₂O₃ film forming at the AlGaN/HfO₂ interface. Pretreatments for HfO₂ were studied, which showed that growth at 250 °C, along with a treatment of BHF, piranha, and UV ozone, was able to reduce the trap concentration and improve the breakdown field [98]. Al₂O₃, another ALD dielectric with high permittivity, has shown the importance of proper surface treatment, with variations in the flatband voltage and the size of the hysteresis [99].

Research has also been performed to combine the benefits of Al₂O₃ and SiO₂ by growing AlSiO by MOCVD. This combines the high permittivity of Al₂O₃ with the larger band offsets and breakdown voltage of SiO₂ due to its larger band gap, and, in theory, results in an improved dielectric for RF and mmWave. Initial work showed that there is nearly half the amount of interface traps at the AlSiO/GaN interface for N-polar GaN compared to Ga-polar [100]. With this promising result, research was performed to find the optimal AlSiO composition. It was shown that a Si composition of 46% can reduce the hysteresis to a minimal 0.045 V ΔV_FB, better than what is observed for MOCVD Si₃N₄ [101]. Further studies showed that post-growth annealing aided in the reduction in the ΔV_FB, with an anneal of 370 °C suppressing the hysteresis [102].

3.2. Schottky Barrier Contacts on N-polar GaN

Schottky contact-based gate modules are a choice for many semiconductor technologies. Compared to dielectrics, Schottky barrier contacts suffer less from trapping effects, as the main site for trapping for Schottky barriers is the metal–semiconductor interface, with no bulk traps, unlike in dielectrics. Additionally, the Schottky barrier contacts enable a higher gate aspect ratio by reducing the vertical distance between the gate metal and 2DEG, and thus better channel control, higher transconductance, and lower output conductance compared to a MIS structure for the same gate length. The biggest concern, however, is the potentially high reverse leakage current, which sets the minimum achievable off-state current, and high forward gate current, which limits the maximum achievable knee current, and thus power and efficiency. In 2013, a study reported Schottky barrier contacts to N-polar GaN using Cu, Au, Pd, Ni, Pt metals demonstrated IV (CV) measurement-based mean barrier heights of 0.48 eV (0.51 eV), 0.54 eV (0.60 eV), 0.64 eV (0.73 eV), 0.55 eV (0.68 eV), and 0.67 eV (0.76 eV), as well as mean ideality factors of 1.06, 1.08, 1.06, 1.11, and 1.07, respectively [103]. In 2020, ref. [104] reported N-polar GaN Ru Schottky barrier contacts with IV (CV) measurement-based barrier height of 0.77 eV (0.81 eV) at room temperature with near-ideal thermionic emission behavior. Although Ru on Ga-polar GaN showed a higher IV-based barrier height of 1 eV, the reverse leakage current was higher than that of N-polar GaN, which was attributed to the presence of additional leakage mechanisms other than thermionic emission, such as trap-assisted tunneling, and hopping conduction via dislocations for Ga-polar GaN. In 2024, ref. [105] reported the impact of annealing on Ni/N-polar GaN Schottky barrier contacts, which concluded that the best electrical performance was obtained by annealing at 450 °C for 60 s. For this condition, a barrier height of 0.77 eV and an ideality factor of 1.54 were demonstrated.

4. Device Structures and Electrical Performance of N-polar GaN HEMTs

N-polar GaN HEMTs come in a variety of device structures to accommodate the desired RF performance parameters, such as power density, gain, efficiency, linearity, and maximum operating frequency. The structures reported in the literature can be grouped under four main categories, namely, planar N-polar GaN HEMTs, fully self-aligned N-polar GaN HEMTs, trench gate N-polar GaN HEMTs, and self-aligned gate deep-recess N-polar GaN HEMTs. In this section, each of these structures is discussed in depth regarding their epitaxial structure with back barrier and channel designs, their gate module with the gate dielectrics or Schottky barrier contacts, their source and drain ohmic contacts, fabrication processes, and the impact of these design and fabrication variations on the electrical performance of N-polar GaN HEMTs.

4.1. Planar N-polar GaN HEMTs

Due to their low-complexity fabrication process and easy scalability for operation at different bias voltages and frequencies, early N-polar GaN HEMTs [50,77,83,106] and some relatively recent ones [91,107,108] have mainly utilized a planar device structure with a non-self-aligned gate. A generic depiction is shown in Figure 2.

4.1.1. MBE-Grown Planar HEMTs

4.1.1.1. MBE-Grown Planar HEMTs with GaN/AlGaN Structure

One of the earliest studies on the electrical performance of MBE-grown planar N-polar GaN/AlGaN structures was carried out to assess 2DEG properties with CV and Hall measurements in 2005 [109]. The epitaxial structure on C-face SiC consisted of a GaN buffer, a 30 nm Al_0.3Ga_0.7N back barrier with 20 nm Si-doped and 10 nm undoped sections, and a 30 nm GaN channel (cap). In such a structure, modulation doping was used to reduce the impact of the GaN surface states on the 2DEG charge. With the measurements, a 2DEG mobility of 1020 cm²·V⁻¹·s⁻¹ and a charge density of 1 × 10¹³ cm⁻² were captured. Additionally, the zero-bias capacitance value confirmed the presence of the 2DEG at the top GaN/AlGaN interface.

In 2007, ref. [50] reported some of the earliest planar HEMTs with three epitaxial variations grown on C-face SiC. These HEMTs employed a gate length (L_g) of 0.7 μm and source-drain spacing (L_sd) of 3.4 μm. The Ga-polar ohmic contact process was re-optimized with a Ti/Au/Ni/Au stack with 30 s annealing at 870 °C in N₂, which culminated in acceptably low 0.4 Ω·mm contact resistance. The transistors employed Ni/Au/Ni Schottky gate contacts. The first structure was the same as reported in [109], employing abrupt GaN/AlGaN/GaN with the modulation-doped back barrier structure. For this structure, a saturation current of 800 mA/mm, 195 mS/mm peak transconductance, and a peak f_T/f_MAX of 18/44 GHz was measured. However, these devices showed a significant dispersion in pulsed IV measurements. The presence of donor-like states 60 meV above the valence band at the back barrier–buffer interface (negative polarization interface) was claimed to cause the dispersion seen in the pulsed IV. The second structure adopted a 10 nm Si-doped GaN and a back barrier with 40 nm graded (5% to 25%) and doped AlGaN, as well as a 10 nm undoped Al_0.25Ga_0.75N layer. This structure aimed to steer the valence band away from the Fermi level at the negative polarization interface to avoid the donor-like states. This approach largely eliminated the dispersion seen in the pulsed IV, with about 0.6 A/mm saturation current and peak f_T/f_MAX of 17/36 GHz. However, these first two structures suffered from high gate leakage of 4 mA/mm at 20 V breakdown voltage. To suppress the leakage from the Schottky gate contact, the third structure employed a 10% AlGaN cap layer. The band diagrams are shown in Figure 3.

This structure effectively suppressed the gate leakage with 4 mA/mm at 70 V breakdown voltage, and maintained dispersion-free pulsed IV performance; however, it suffered from a lower saturation current of <0.5 A/mm due to the AlGaN cap depleting some of the 2DEG in the channel.

In 2012, ref. [110] demonstrated a highly scaled planar HEMT grown by MBE. Designed for high-frequency operation, these transistors employed a tall re-aligned T-gate structure, scaled gate length of 80 nm, a source-drain spacing of 250 nm, 4.5 nm MOCVD SiN_x gate dielectric, and MBE N+ GaN regrown contacts. The epitaxial structure on SiC was similar to the second structure reported in [50], except this one employed a 2 nm AlN layer between the 10 nm GaN channel and 10 nm UID Al_0.3Ga_0.7N, for separation from 2DEG to the alloyed back barrier. These devices showed a >1.7 A/mm current, a peak transconductance of 387 mS/mm at V_D of 3 V, and f_T/f_MAX of 148/351 GHz.

4.1.1.2. MBE-Grown Planar HEMTs with Non-AlGaN Back Barrier

In 2009, ref. [106] demonstrated a T-gated planar N-polar GaN HEMT with a 3 nm AlN back barrier to remove alloy scattering-induced mobility degradation and to enhance charge confinement. On C-face SiC, a UID GaN buffer, 5.5 nm Si-doped GaN, 4 nm UID GaN spacer, 3 nm AlN back barrier, and finally a 20 nm UID GaN channel, 10 periods of 2 nm highly doped GaN and 2 nm UID GaN were grown. This structure employed in situ N+ layers for contacts, which were later etched to define the channel between source and drain. Ex situ 5 nm MOCVD SiN_x was used as the gate dielectric. These devices had a L_g of 150 nm and 1000 nm L_sd. The maximum peak transconductance (g_m) of 220 mS/mm was obtained for a 15 nm thick channel HEMT, which showed a <0.8 A/mm saturation current and f_T/f_MAX of 47/81 GHz. A relatively low breakdown voltage of 20 V at 1 mA/mm was reported. In 2010, a very similar epitaxial and device structure to [106] but with 108 nm thick PECVD SiN_x passivation [111] showed a large signal power performance of 2.2 W/mm maximum P_OUT, peak PAE of 11.5%, and a linear gain (G_T) of 5.7 dB at 30 V drain bias at 30 GHz. P_OUT turned out to be low for the given drain bias, which indicated DC-RF dispersion. The authors attributed the dispersion to surface-related trapping: imperfect passivation and small 2DEG to surface distance (15 nm). In 2019, ref. [107] reported planar HEMTs with 10 periods of 1 nm AlN and 2 nm GaN superlattice back barrier to obtain an effective 33% Al grown on bulk GaN. The superlattice back barrier was preferred because linearly graded AlGaN growth was not possible without interruption using PAMBE. The transistors with L_g of 750 nm and L_sd of 5 μm showed a >1 A/mm current, 0.197 mS/mm peak g_m, f_T/f_MAX of 8.9/14.6 GHz, a breakdown voltage of 15 V, and a large signal performance of 0.56 W/mm with 23% PAE at 4 GHz.

4.1.2. MOCVD-Grown Planar HEMTs

4.1.2.1. MOCVD-Grown Planar HEMTs with GaN/AlGaN Structure

One of the earliest MOCVD-grown planar HEMTs, ref. [83] reported transistors that employed a 30 nm GaN channel and a 7 nm UID Al_0.3Ga_0.7N/19 nm Si-doped Al_0.3Ga_0.7N back barrier, annealed Ti/Al/Ni/Au contacts, Ni/Au gate, 700 nm L_g, and 3400 nm L_sd. These devices, grown on a miscut sapphire substrate, were oriented such that the current flows along the growth steps along which mobility is the highest. These devices demonstrated >0.8 A/mm current and peak f_T/f_MAX of 15/38 GHz. Using similar epitaxial layers and device dimensions to [77,83] showed HEMTs on SiC with SiN_x gate dielectric and 200 nm passivation, which demonstrated a low gate leakage current, >150 V breakdown voltage, >0.7 A/mm on-state current, and intrinsic f_T/f_MAX of 17/33 GHz. In 2009, employing a graded and doped AlGaN back barrier and a 2 nm AlGaN cap on the channel to reduce the gate leakage, ref. [112] demonstrated HEMTs on a sapphire substrate with 5 nm in situ MOCVD SiN gate dielectric, source-terminated field plate on 160 nm PECVD SiN passivation, 700 nm L_g, 4200 nm L_sd, and 3000 nm L_gd. With >0.6 A/mm DC and >0.8 A/mm pulsed current, these devices showed >150 V breakdown voltage, f_T/f_MAX of 14/36 GHz, and a large signal performance of 4.7 W/mm with 64% PAE at 30 V drain bias at 4 GHz.

In 2016, ref. [113] showed HEMTs on sapphire substrate that employed a T-gate with 5 nm ex situ MOCVD SiN_x gate dielectric, MBE re-grown contacts, 120 nm PECVD SiN_x/2 nm ALD Al₂O₃ passivation, scaled lateral dimensions of 100 nm L_g, 1300 nm L_sd, and 1000 nm L_gd. These devices demonstrated 114 V breakdown voltage, >1.3 A/mm current, f_T/f_MAX of 103/248 GHz, and a large signal performance of 5.74 W/mm with 53.4% PAE at V_D of 35 V at 4 GHz and 6.29 W/mm with 38.4% PAE at V_D of 40 V at 10 GHz. The authors of [114] reported improvement in the DC-RF dispersion with optimized 80 nm PECVD SiN_x/3 nm ALD Al₂O₃ passivation. As a result, these devices exhibited a better large signal performance of 5.43 W/mm with 52% PAE at V_d of 25 V at 10 GHz. Using a similar device and epitaxial structure to [114,115] evaluated the linearity performance of these HEMTs with OIP3/P_DC of 12 dB at V_d of 20 V at 10 GHz, showing a low third-order intermodulation distortion. With epitaxial layers similar to [114], more scaled HEMTs with 80 nm L_g, 500 nm L_sd, and 345 nm L_gd were demonstrated with >1.5 A/mm knee current, f_T/f_MAX of 110/230 GHz, and >40 V breakdown voltage in [91]. This study in 2024 showed a good performance uniformity on a 100 mm SiC substrate with a representative large signal performance of 2 W/mm with 43% PAE at V_D of 8 V at 94 GHz. For thermal management, ref. [108] demonstrated planar N-polar GaN HEMTs that integrated all-around polycrystalline diamond in 2025. A thermally stable Mo gate was used for 500 °C diamond growth for the gate-first fabrication approach, which showed the first successful diamond integration after device fabrication completion for high-frequency GaN HEMTs.

4.1.2.2. MOCVD-Grown Planar HEMTs with Non-AlGaN Back Barrier

A large tensile strain can be imposed on the channel by the AlGaN barriers, as used in the HEMTs previously discussed. Therefore, InAlN barriers were exploited in the epi structure as it is lattice-matched to GaN. In 2010, ref. [116] reported AlN/InAlN back barrier MISHEMTs with alloyed contacts grown on a sapphire substrate via MOCVD. For dimensions of 700 nm L_g, 2200 nm L_sd, and 1000 nm L_gd, these devices showed a high knee current of >1.4 A/mm thanks to the high 2DEG charge of 2.15 × 10¹³ cm⁻², f_T/f_MAX of 14/25 GHz, but a high gate leakage of 1.7 mA/mm at V_gd of −16 V. In 2012, ref. [117] showed AlN/InAlN back barrier HEMTs with similar epitaxial layers to [116], with 100 nm L_g and 175 nm L_sd, MBE regrown contacts, a T-gate structure with 4.5 nm MOCVD SiN gate dielectric. These devices showed a high knee current of >1.7 A/mm and a high f_T/f_MAX of 142/400 GHz. In 2013, ref. [118] demonstrated HEMTs with a similar device structure to [117], yet with an AlN/InAlN/AlGaN back barrier, which enabled scaling the channel thickness to 5 nm while sustaining a high charge density of 2 × 10¹³ cm⁻² with 1100 cm⁻²/V·s mobility. This study scaled the devices further, both vertically by employing a 5 nm GaN channel and 2 nm MOCVD SiN gate dielectric, and laterally by implementing L_g of 60–100 nm and L_sd of 100–200 nm. The ultra-scaled geometry with high charge and mobility yielded an impressive >4 A/mm current, extrinsic DC g_m of 1.89 S/mm, f_T/f_MAX 163/405 GHz, and a breakdown voltage of 14.2 V. In 2014, ref. [119] explored the InAlN/AlGaN back barrier design for a GaN channel thickness < 5 nm, and demonstrated the sensitivity of the channel conductivity on the back barrier design when the channel thickness is sub−5 nm. With InAlN to AlN grading, a sheet charge resistance of 329 Ω/☐ was achieved, which resulted in >1.2 A/mm, peak extrinsic DC g_m of 718 mS/mm, and extrinsic f_T/f_MAX of 19.1/44.6 GHz from a transistor with 500 nm L_g, 1000 nm L_sd, and 250 nm L_gd. In 2024, ref. [120] demonstrated planar N-polar GaN HEMTs with AlN/InAlGaN back barrier grown on sapphire substrate. This novel epitaxial structure demonstrated an impressive charge density of 2.85 × 10¹³ cm⁻² with a mobility of 1048 cm⁻²/V·s. The devices with 600 nm L_g, 3100 nm L_sd, and 1500 nm L_gd showed a high current of >1.75 A/mm and f_T/f_MAX of 18/28 GHz.

4.2. Fully Self-Aligned N-polar GaN HEMTs

N-polar GaN-based high-electron mobility transistors (HEMTs) have consistently demonstrated excellent high-frequency performance. To achieve high power gain and efficiency at these frequencies, critical device dimensions, e.g., gate length and access regions, are highly scaled. Fully self-aligned fabrication technology employed in GaN-based HEMTs has shown promising results in RF performance enhancements [121]. Combined with ultra-scaled device dimensions and InN/InGaN MBE regrowth contacts, a cutting-edge f_T·L_g metric of 16.8 GHz-μm in self-aligned HEMTs was demonstrated, highlighting the significance of the highly scaled self-aligned technology. A generic fully self-aligned N-polar GaN HEMT structure is shown in Figure 4.

4.2.1. Fully Self-Aligned N-polar GaN HEMTs with GaN/AlGaN Structure

Dasgupta and Nidhi et al. made two important fabrication developments for gate-first self-aligned N-polar GaN/AlGaN HEMTs, i.e., low-temperature, high-quality InN/InGaN regrowth contacts that eliminate electron barriers and minimize contact resistance [122] and self-aligned refractory gates (W/Cr) that withstand high temperatures during contact regrowth [123]. A cross-section of the self-aligned devices is shown in Figure 5.

The first generation of the self-aligned N-polar GaN HEMTs consisted of a 10 nm GaN channel, 2 nm AlN spacer, and 5 nm SiN gate dielectric [121]. The sheet resistance of the channel was 600 Ω/☐. Several highlights were revealed by the device. First, an excellent contact resistance of 0.023 Ω·mm was achieved with InN/InGaN regrowth contacts. In addition, an exceptionally high saturation drain current of 2.4 A/mm at V_DS = 4 V and V_GS = 2 V was exhibited in a L_g = 120 nm device, with peak gate transconductance (g_m) of 530 mS/mm at V_DS = 5 V. Noticeably, the g_m profile remains relatively flat across a wide range of drain current, indicating that a source choke has been effectively eliminated in self-aligned devices. Moreover, small signal measurements resulted in a f_T and f_MAX of 132 GHz and 17.5 GHz at V_DS = 4.3 V, respectively. It is important to note that the relatively lower f_MAX value can be greatly improved by reducing the gate resistance, e.g., T-gate implementation.

Discovering the significance of the highly scaled self-aligned technology, Nidhi et al. further scaled the gate length L_g [124]. The DC measurements resulted in a saturated drain current of 1.89 A/mm at V_GS = 2V for L_g = 80 nm, though peak g_m was reduced to 337 mS/mm at V_DS = 2.5 V due to an inferior gate control; it was concluded to maintain an aspect ratio above 5.5 for good gate control. That said, the small signal measurements showed maximum f_T and f_MAX of 163 GHz and 20 GHz at V_DS = 4 V in an L_G = 100 nm device, a great f_T enhancement from 132 GHz at L_g = 120 nm. Notably, mean electron velocity enhancement was observed in these highly scaled devices: the extracted mean channel velocity was 1.51 × 10⁷ cm/s for L_g ≥ 80 nm vs. 1.28 × 10⁷ cm/s for L_g ≥ 100 nm, which supported the observed maximum drain current increases in reduced L_g devices. This outlines the tremendous benefits of self-aligned, highly scaled HEMTs in high-frequency operations.

One drawback of the aforementioned highly scaled, self-aligned HEMTs is the large gate resistance, especially when dimensions were sub-100 nm scaled. Nidhi et al. demonstrated a process for T-gate implementation [125]. As a result, the f_MAX was notably improved from 17 GHz to 127 GHz without much degradation of f_T in a L_g = 130 nm device. Very recently, in 2024, gate-first self-aligned highly scaled N-polar GaN/AlGaN HEMTs were reported on novel MOCVD-grown epitaxy with a R_sh of ~395 Ω/☐ [126]. The epitaxial layers consist of a 12 nm GaN channel, 7 nm SiN gate dielectric, and MBE GaN regrowth contacts (n+/UID). Wang et al. demonstrated that, using a similar fabrication process aforementioned, a high drain current of 2.07 A/mm at V_GS = 1 V and a peak g_m of 430 mS/mm at V_DS = 3 V was measured in a L_g = 77 nm device. The contact resistance was 0.039 Ω·mm. Small-signal measurements resulted in an excellent f_T of 143.7 GHz at V_DS = 6 V, and thus a f_T·L_g metric of 11.1 GHz·μm was calculated, which is around a 35% increase at the aspect ratio of ~4 compared to another report [127]. The peak intrinsic mean velocity was found to be over 1.5 × 10⁷ cm/s for the L_g = 77 nm device, aligning with the results reported in [124].

4.2.2. Fully Self-Aligned N-polar GaN HEMTs with Non-AlGaN Back Barrier

With InAlN barriers, outstanding device results of record-high drain current density and extrinsic g_m are reported [128]. Because of the strong spontaneous polarization of In_0.17Al_0.83N, MBE-grown N-polar GaN HEMT epitaxy of a 10 nm GaN channel resulted in a low sheet resistance of only 330 Ω/☐. Nidhi et al. exhibited a state-of-the-art drain current density of 2.8 A/mm at V_GS = 2 V and on-resistance of 0.29 Ω·mm in a L_g = 60 nm device among GaN-based devices [128]. More importantly, the peak g_m reached 1105 mS/mm at V_DS = 2 V, which is the highest g_m value reported. Furthermore, an L_g = 30 nm device achieved a f_T of 155 GHz at V_DS = 3 V; nevertheless, this value was not commensurate with the high DC g_m values. Pulsed IV measurements showed current collapse and knee walkout at a 40 ns short gate pulse, and thus the inconsistency was hypothesized to be due to fast shallow traps introduced during MBE InAlN back barrier growth.

4.3. Trench Gate N-polar GaN HEMTs

With progress on planar structures, passivation with gate recess was quickly introduced to N-polar GaN HEMTs to improve large-signal performance. In this case, the fabricated device structure features a recessed passivation layer under the gate and a slant sidewall profile of the gate recess, which is described as trench gate devices in this review, as shown in Figure 6a.

The trench-gated architecture has been central to advancing N-polar GaN MIS-HEMTs grown by MOCVD, as MBE-grown devices generally exhibited lower breakdown voltages. The thick dielectric passivation and etch formed slant sidewall under the gate can offer enhanced surface passivation and an integrated slant gate field plate, enabling the N-polar device to work at a high operation voltage regime.

Early work in 2008 by [49] introduced a trench MIS-HEMT with PECVD SiN passivation and timed etch using CF₄/O₂ plasma etch under the gate. The MOCVD-grown N-polar GaN-on-SiC devices delivered 7.1 W/mm with 58% PAE at 4 GHz, showing significant improvement in large signal performance over results on a planar structure [129]. This result demonstrated the effectiveness of passivation of N-polar GaN HEMTs with a trenched gate. Later, AlN nucleation [130] and back-barrier optimization [131] were investigated to improve device performance through optimized growth. On top of that, device fabrication also improved with efforts on the source field plate [112], where a high PAE of 67% was obtained with 2.5 W/mm at a drain bias of 20 V. In addition, an etch-stop technology [78] was implemented in device processing to further enhance large signal performance with better breakdown and gate control. The large signal performance was boosted to 20.7 W/mm with an associated 60% PAE at 4 GHz and 16.7 W/mm at 10 GHz, showing that the N-polar trench gate HEMTs are well-suited for C-band and X-band applications with high operation voltage, which is shown in Figure 6b.

Pushing toward mmWave applications, a trench gate structure was investigated by [132] in 2018 for enhanced breakdown, and a high f_MAX·V_DS,Q of 8.1 THz·V was demonstrated on aggressively scaled trench-gated MIS-HEMTs with f_MAX of 313 GHz at 26 V drain bias. Later, N-polar trench gate devices were demonstrated on commercial N-polar GaN HEMT epitaxy [32] on both 100 mm sapphire and 100 mm SiC substrates, supporting trench gate integration with uniform device performance, reinforcing the maturity of trench-gated N-polar technology for scalable RF deployment. With its maturity in epitaxy and device fabrication, the trench gate structure was also used for device fundamental research purposes, such as hot electron and impact ionization in N-polar GaN [133], as well as new process technology exploration [134].

4.4. Self-Aligned Gate Deep-Recess N-polar GaN HEMTs

Although the ex situ passivation served as a good dispersion mitigator for the previously discussed device structures, the N-polar GaN technology offers a unique capability by using a GaN capping layer as an in situ passivation layer. When adding a GaN cap on top of the channel in the access regions of the device, the threshold voltage of these regions becomes more negative, which mitigates the dispersion effects associated with trapping. On top of that, the in situ GaN cap moves the GaN surface states away from the channel, whereas in the case of ex situ passivation, the GaN surface states are not moved. Furthermore, the GaN cap brings the conduction band down in the channel with respect to the Fermi level and hence enhances the access region conductivity. Because of these advantages, self-aligned gate deep-recess N-polar GaN HEMTs emerged to take full advantage of the N-polar GaN platform by employing access regions with a GaN cap and a recessed gate structure for good gate control. Figure 7 shows a generic self-aligned gate deep-recess N-polar GaN HEMT.

4.4.1. Self-Aligned Gate Deep-Recess N-polar GaN HEMTs on SiC Substrates

Romanczyk et al. fabricated an N-polar deep-recess GaN HEMT with a 47.5 nm GaN cap, 9 nm UID GaN channel, and 5 nm of ex situ MOCVD Si₃N₄ gate dielectric [135]. The structure was highly scaled with L_g of 45 nm, L_gs of 125 nm, L_sd of 400 nm, and W_g of 2 × 25 μm. Peak f_T/f_MAX were 149/285 GHz and an excellent 34.2% PAE with associated 2.5 W/mm P_OUT were demonstrated at 87 GHz. The same epitaxial structure and intrinsic FET dimensions were employed on W_g of 2 × 37.5 μm HEMTs and measured at a 94 GHz load-pull in [136]. The transition from a T-feed to π-feed pad design resulted in a significant reduction in source inductance and a commensurate increase in linear gain. Peak PAE of 27.8% with associated P_OUT of 3 W/mm and linear G_T of 7.4 dB were demonstrated at 94 GHz. This load-pull result was measured at a V_DS,Q of 9 V. P_OUT scaled well from 7–11 V due to the dispersion mitigation provided by the UID GaN cap. A higher V_DS,Q could provide a significant boost in output power while maintaining a reasonably high associated PAE. To this end, Romanczyk et al. fabricated self-aligned HEMTs with L_g (the lateral dimension at the bottom of the gate recess) of 75 nm, L_gs of 75 nm, L_sd of 400 nm, and W_g of 2 × 37.5 μm [7]. Devices demonstrated a peak f_T/f_MAX of 113/238 GHz. A 94 GHz load-pull was measured with a high V_DS,Q of 20 V. A remarkable 7.94 W/mm with associated 26.9% PAE was achieved. In order to further increase the output power, the impact of ex situ PECVD Si₃N₄ passivation was investigated [8]. Fabricated devices had L_g of 100 nm, L_gs of 85 nm, L_sd of 450 nm, and W_g of 2 × 37.5 μm. The addition of 40 nm of PECVD Si₃N₄ passivation resulted in P_OUT of 8.84 W/mm and associated 27.0% PAE at 94 GHz with a V_DS,Q of 23 V. The linear G_T was 6.5 dB, indicating there was still sufficient gain for W-band operation despite the parasitic capacitance introduced by the passivation. The full power sweep is shown in Figure 8.

Liu et al. employed ALD Ru as the first layer of gate metal [137]. The HEMT structure consisted of a 47.5 nm GaN cap, 12 nm GaN channel, 5 nm of ex situ MOCVD Si₃N₄ gate dielectric, and 24 nm of ex situ PECVD Si₃N₄ passivation. Reported devices had an L_g of 48 nm, L_gd of 220 nm, L_sd of 340 nm, and W_g of 2 × 37.5 μm. Importantly, 94 GHz load-pull measurements at a V_DS,Q of 18 V resulted in an output power density of 6.2 W/mm and associated PAE of 33.8% with a linear transducer gain of 8.1 dB.

Thus far, 94 GHz output power has been discussed primarily in terms of power density. Of course, absolute output power is the paramount power metric in real circuit applications. Maximizing device-level output power can reduce the need for power combining and thus increase circuit efficiency. The excellent P_OUT densities demonstrated by N-polar deep-recess GaN HEMTs provided a promising path to 1 W single-device output power at W-band. Akso et al. implemented an airbridge process to scale the periphery and output power [138]. The HEMT structure consisted of a 47.5 nm GaN cap, 9 nm GaN channel, 5 nm of ex situ MOCVD Si₃N₄ gate dielectric, and 20 nm of ex situ PECVD Si₃N₄ passivation. A gate periphery of W_g 4 × 25 μm was formed by source-connected airbridges. The reported HEMT had an L_g of 48 nm, L_gd of 417 nm, and L_gs of 75 nm. The 94 GHz load-pull measurements achieved output power of 712 mW (7.1 W/mm) with an associated 31.7% PAE at V_DS,Q of 20 V. For comparison, a device with a W_G of 2 × 37.5 μm (no airbridge) was measured at the same drain bias and showed output power of 517 mW (6.9 W/mm) and 30.6% associated PAE. Next, Akso et al. demonstrated HEMTs with L_g of 54 nm, L_gs of 75 nm, and L_ds of 560 nm on an epitaxial structure with a 47.5 nm GaN cap, 9 nm GaN channel, and 5 nm of ex situ MOCVD Si₃N₄ gate dielectric [93]. A HEMT with W_g of 4 × 37.5 μm was measured with 94 GHz active load-pull [139] at a V_DS,Q of 20 V. A maximum P_OUT of 1 W (6.66 W/mm) was achieved with an associated PAE of 21.4%. This milestone further demonstrated the viability of the N-polar deep-recess GaN HEMT technology for mm-wave PAs.

Additionally, Collins et al. demonstrated peak output power density of 4.9 W/mm and associated PAE of 33.9% from corrugated HEMTs, as shown in Figure 9 [140]. The corrugated HEMTs with high power and bias-insensitive linearity demonstrated the viability of this structure for both receiver and transmitter applications. Similarly, ref. [141] demonstrated bias-insensitive linearity, but through etching the sections of the gate to create dual-threshold voltage operation.

4.4.2. Self-Aligned Gate Deep-Recess N-polar GaN HEMTs on Sapphire Substrates

As discussed above in the context of device output power density compared to total output power, there are factors other than peak intrinsic HEMT performance that must be given weight when considering circuit- and system-level applications. One such factor is the use of either SiC or sapphire substrates. Although SiC promises higher peak performance, sapphire offers a low-cost alternative. The high mm-wave output powers and efficiencies inherent to N-polar GaN can be used to leverage sapphire as a substrate. Self-aligned N-polar deep-recess GaN HEMTs on sapphire were pursued in parallel with those on SiC, and their development will be discussed in this section.

Romanczyk et al. fabricated HEMTs with L_g of 60 nm, L_gs of 125 nm, L_ds of 500 nm, and W_g of 2 × 25 μm on a structure consisting of a 22 nm GaN cap, 10 nm GaN channel, and 3 nm of ex situ MOCVD Si₃N₄ gate dielectric [142]. Gate metallization was performed via Cr/Au e-beam evaporation. Then, 94 GHz load-pull measurements taken at a V_DS,Q of 14 V achieved a peak output power of 4.2 W/mm with an associated PAE of ~7%. This early result showed that high output power was attainable on sapphire substrates from the self-aligned deep-recess process. Romanczyk et al. then fabricated HEMTs with L_g of 50 nm, L_gs of 70 nm, L_gd of 300 nm, and W_g of 2 × 25 μm on a structure consisting of a 20 nm GaN cap, 10 nm GaN channel, ex situ MOCVD Si₃N₄ gate dielectric, and 20 nm of ex situ PECVD Si₃N₄ passivation [143]. Devices were also coated with 2.7 μm-thick BCB. The 94 GHz load-pull measurements at V_DS,Q of 16 V achieved a peak output power density of 5.5 W/mm with associated 20.6% PAE.

Li et al. fabricated HEMTs with L_g of 57 nm, L_gs of 75 nm, L_ds of 420 nm, and W_g of 2 × 25 μm on a structure consisting of a 20 nm GaN cap, 10 nm GaN channel, and 5 nm of ex situ MOCVD Si₃N₄ gate dielectric [92,144]. ALD Ru was incorporated as the first layer of the gate metal. A 94 GHz load-pull was measured on devices both before and after passivation with 20 nm of ex situ PECVD Si₃N₄. Before passivation, a peak PAE of 41.8% was achieved with an associated P_out of 4.38 W/mm at V_DS,Q of 12 V. After passivation, a peak PAE of 38.5% with an associated P_out of 5.83 W/mm was achieved at a V_DS,Q of 14 V, as shown in Figure 10. This simultaneous high efficiency and high output power demonstrated the viability of sapphire as a substrate for high-performance N-polar GaN HEMTs for mm-wave.

The exceptionally high PAE reported in [92,144] suggested the potential for applications beyond 94 GHz. Akso et al. fabricated pre-matched HEMTs for operation at 132 GHz (D-band) [145]. These pre-matched structures used the same intrinsic devices as reported in [144]. Large signal performance was measured at 132 GHz with V_DS,Q of 12 V, and a record 2 W/mm P_OUT with 10.6% associated PAE was recorded. This work demonstrated output power density that exceeded all reported Ga-polar MMICs from 120 to 150 GHz and provides a promising pathway for future N-polar D-band transistor development.

4.4.3. Alternative Gate Technologies and Enhancement-Mode Operation

As the channel lengths scale, short channel effects start impacting the performance in that smaller gate lengths do not necessarily culminate in higher gain at mmWave frequencies. To address this challenge, Akso et al. proposed the use of Schottky-gated N-polar deep-recess GaN HEMTs. In their initial work [146], Akso et al. employed ALD-deposited ruthenium (Ru) as the Schottky gate metal and demonstrated a record 10.5 dB linear gain and 50.2% peak power-added efficiency (PAE) at 94 GHz, along with an f_T of 176 GHz using a 50 nm L_G—highlighting the performance advantages of Schottky gates. The forward gate leakage remained within an acceptable range of 40 µA/mm at a gate bias of +1 V. Shortly after, Collins et al. reported similar Schottky-gated N-polar deep-recess GaN HEMTs, incorporating a thin ALD-deposited titanium nitride (TiN) adhesion layer prior to Ru deposition [147]. This approach achieved a record f_T of 193 GHz and f_MAX of 335 GHz, with a sixfold reduction in reverse-bias gate leakage current compared to Ru-only devices. A peak PAE of 53.4% further demonstrated the strong potential of Schottky gates for high-frequency N-polar deep recess GaN HEMT applications. To reduce the fringe capacitance, ref. [148] used a novel process with a thick dielectric on the sidewalls, which improved the f_T·L_G product.

The second major approach to scaling the frequency performance of N-polar deep-recess GaN HEMTs involves the use of high-k insulators as gate dielectrics. While Schottky contacts maximize gate-to-channel capacitance, they suffer from drawbacks such as lower breakdown voltages and higher gate leakage, particularly under forward gate bias. High-k dielectrics offer a compelling trade-off, enabling increased gate capacitance while maintaining low leakage currents. Moreover, a high-breakdown dielectric is essential for enhancement-mode operation. However, the quality of both the bulk dielectric and the dielectric/semiconductor interface is critical to preserving large-signal performance. Initially, Odabasi et al. implemented ALD-deposited HfO₂ as the gate dielectric in N-polar deep-recess GaN HEMTs [149]. Although HfO₂ had been previously used on N-polar GaN in large-area Schottky diodes, its integration into deep recess HEMT structures posed additional challenges. While a high breakdown field of 6 MV/cm and low dispersion were achieved, unexpectedly high gate leakage and low breakdown voltages limited large-signal operation. These issues were attributed to the polycrystalline nature of HfO₂, caused by its low crystallization temperature, which degrades dielectric integrity. To address this, Odabasi et al. proposed incorporating silicon into HfO₂ to raise the crystallization temperature and enhance gate performance [150]. Using a digital ALD process to alternate HfO₂ and SiO₂ layers, they formed an amorphous HfSiO gate dielectric. Although the inclusion of SiO₂ reduced the dielectric constant to ~9.4, the crystallization temperature was increased to over 800 °C, ensuring an amorphous structure. This led to a robust forward breakdown voltage of +7 V and enabled successful enhancement-mode operation. The resulting devices demonstrated record small-signal performance among enhancement-mode GaN HEMTs, highlighting the promise of high-k dielectrics in N-polar deep recess GaN HEMTs, especially when combined with advancements in epitaxial growth.

4.4.4. Benchmarking of Performance at W- and D-Bands

Table 1. Benchmark of N-polar and Ga-polar GaN performance at W-band.

Ref.	Orientation	Year	Substrate	DUT Type	Frequency (GHz)	VDS,Q (V)	POUT,SAT (W/mm)	POUT,SAT (mW)	PAESAT (%)	PAEPEAK (%)
[7]	N-polar	2018	SiC	HEMT	94	20	7.94	595.5	26.9	27.9
[8]	N-polar	2020	SiC	HEMT	94	23	8.84	663	27	-
[93]	N-polar	2023	SiC	HEMT	94	20	6.66	999	21.4	~25
[92]	N-polar	2023	Sapphire	HEMT	94	12	4.85	242.5	40.2	40.2
[147]	N-polar	2024	Sapphire	HEMT	94	12	3.7	185	53.4	53.4
[151]	Ga-polar	2015	Si	HEMT	94	9	1.35	135	~2	12
[152]	Ga-polar	2019	SiC	HEMT	94	20	4	200	>12.5	14.3
[153]	Ga-polar	2022	SiC	HEMT	94	10	3.6	-	24.3	24.3
[154]	Ga-polar	2023	SiC	HEMT	94	12	2.2	110	13	15
[155]	Ga-polar	2023	SiC	Prematched	94	14	2.1	315	45	45
[156]	Ga-polar	2009	Si	MMIC	76	8	0.13	25	-	-
[157]	Ga-polar	2010	SiC	MMIC	88	14	1.4	842	14.8	15
[158]	Ga-polar	2011	SiC	MMIC	91	20	-	1700	11	11
[159]	Ga-polar	2011	-	MMIC	95	14	1.7	1024	19.1	19.1
[160]	Ga-polar	2012	SiC	MMIC	84	20	2.8	2000	-	15.3
[161]	Ga-polar	2012	SiC	MMIC	90	12	-	282	13.2	13.2
[162]	Ga-polar	2012	SiC	MMIC	93.5	14	1.78	2138	19	-
[163]	Ga-polar	2014	SiC	MMIC	83	12	1.71	1370	27	-
[164]	Ga-polar	2015	SiC	MMIC	84	13	-	3000	12.1	12.1
[165]	Ga-polar	2016	SiC	MMIC	86	20	3.6	1150	-	12.3
[166]	Ga-polar	2017	SiC	MMIC	91	15	3.23	3100	>12.5	~15
[167]	Ga-polar	2017	SiC	MMIC	90	15	1.03	1150	8	8
[168]	Ga-polar	2018	SiC	MMIC	80	15	2.6	724	8.6	8.6
[169]	Ga-polar	2018	SiC	MMIC	90	15	1	600	-	6.7
[170]	Ga-polar	2020	-	MMIC	95	18	-	6025	-	18.3
[171]	Ga-polar	2023	SiC	MMIC	86	-	2.35	282	14.5	-

and

Table 2. Benchmark of N-polar and Ga-polar GaN performance at D-band.

Ref.	Orientation	Year	Substrate	DUT Type	Frequency (GHz)	VDS,Q (V)	POUT,SAT (W/mm)	POUT,SAT (mW)	PAESAT (%)	PAEPEAK (%)
[145]	N-polar	2024	Sapphire	Prematched	132	12	2	100	10.6	-
[172]	Ga-polar	2025	Si	HEMT	123	10	0.67	21	1.3	~3
[173]	Ga-polar	2018	SiC	MMIC	147	10	0.66	66	1.7	1.7
[174]	Ga-polar	2019	SiC	MMIC	120	15	1.4	440	11.5	11.5
[175]	Ga-polar	2022	SiC	MMIC	136	12	0.75	223.9	-	7.9
[176]	Ga-polar	2022	-	MMIC	140	6	0.26	38.9	-	9.1
[177]	Ga-polar	2022	SiC	MMIC	133	-	0.65	97.7	6.5	6.5
[178]	Ga-polar	2023	SiC	MMIC	140	10	1.7	204	11.2	11.2
[179]	Ga-polar	2024	-	MMIC	160	10	0.92	182	2.8	-
[180]	Ga-polar	2025	SiC	MMIC	145	12	-	251	9	9

show the benchmarking of N-polar GaN deep recess HEMTs against Ga-polar GaN HEMTs and MMICs (monolithic microwave integrated circuits) at W- and D-bands, respectively, which illustrate the superior power density and efficiency performance of N-polar GaN technology at these frequencies.

5. Conclusions

In this paper, a comprehensive review of the N-polar GaN HEMT technology is presented. The authors discuss the progression of this technology in three main sections. In the first section, the MBE and MOCVD growth of N-polar GaN epitaxy is discussed. The next section discusses the dielectrics and metals on N-polar GaN for their potential use in the transistor gate module. Finally, the authors discuss the different types of N-polar GaN device structures and the electrical performance of these devices, which demonstrated outstanding performance at microwave and mmWave frequencies.