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Open AccessArticle

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

by 1,2 and 1,*
1
Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, 327 Jungang-ro, Anseong-si, Gyenggi-do 17579, Korea
2
Group for Smart energy Nano Convergence, Korea Institute of Industrial Technology, 6, Cheomdangwagi-ro 208 beon-gil, Buk-gu, Gwangju 61012, Korea
*
Author to whom correspondence should be addressed.
Micromachines 2020, 11(10), 887; https://doi.org/10.3390/mi11100887
Received: 3 August 2020 / Revised: 20 September 2020 / Accepted: 20 September 2020 / Published: 24 September 2020
(This article belongs to the Section E:Engineering and Technology)
The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET. View Full-Text
Keywords: junctionless FET; JLFET; electrical coupling; circuit simulation; parameter extraction; monolithic 3D integrated circuit (IC) junctionless FET; JLFET; electrical coupling; circuit simulation; parameter extraction; monolithic 3D integrated circuit (IC)
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MDPI and ACS Style

Ahn, T.J.; Yu, Y.S. Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs. Micromachines 2020, 11, 887. https://doi.org/10.3390/mi11100887

AMA Style

Ahn TJ, Yu YS. Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs. Micromachines. 2020; 11(10):887. https://doi.org/10.3390/mi11100887

Chicago/Turabian Style

Ahn, Tae J.; Yu, Yun S. 2020. "Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs" Micromachines 11, no. 10: 887. https://doi.org/10.3390/mi11100887

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